diff --git a/CI/update/stm32cube.py b/CI/update/stm32cube.py index a1ad9666db..a264dd4ad6 100644 --- a/CI/update/stm32cube.py +++ b/CI/update/stm32cube.py @@ -930,13 +930,13 @@ def updateCore(): print( "WARNING: OpenAmp MW has been updated, please check whether Arduino implementation:" ) - print(" * cores/arduino/stm32/OpenAMP/mbox_ipcc.h") - print(" * cores/arduino/stm32/OpenAMP/mbox_ipcc.c") - print(" * cores/arduino/stm32/OpenAMP/rsc_table.h") - print(" * cores/arduino/stm32/OpenAMP/rsc_table.c") - print(" * cores/arduino/stm32/OpenAMP/openamp.h") - print(" * cores/arduino/stm32/OpenAMP/openamp.c") - print(" * cores/arduino/stm32/OpenAMP/openamp_conf.h") + print(" * libraries/VirtIO/src/mbox_ipcc.h") + print(" * libraries/VirtIO/src/mbox_ipcc.c") + print(" * libraries/VirtIO/src/rsc_table.h") + print(" * libraries/VirtIO/src/rsc_table.c") + print(" * libraries/VirtIO/inc/openamp.h") + print(" * libraries/VirtIO/src/openamp.c") + print(" * libraries/VirtIO/inc/openamp_conf.h") print(" should be updated from Cube project:") print( " --> Projects/STM32MP157C-DK2/Applications/OpenAMP/OpenAMP_TTY_echo" diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h index 072b033d6b..e36f9db700 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h @@ -336,20 +336,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; @@ -859,84 +859,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -944,44 +947,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -990,76 +994,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2277,8 +2281,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2315,17 +2319,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3311,9 +3311,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3344,6 +3344,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3526,13 +3529,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3547,7 +3543,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3561,19 +3556,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3751,180 +3746,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4590,6 +4595,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4647,72 +4653,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4755,9 +4761,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -4840,6 +4846,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -4848,6 +4871,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -10859,8 +10883,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -11021,8 +11047,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -11038,8 +11072,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -11088,8 +11130,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -11457,6 +11507,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -11549,12 +11602,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -13090,9 +13137,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -13101,17 +13145,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -14031,9 +14064,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -14150,8 +14188,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -14653,15 +14693,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -14864,10 +14901,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -14885,6 +14922,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -15761,9 +15801,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -36392,8 +36432,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h index 361add47f6..d9c105cd76 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h @@ -302,20 +302,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; @@ -825,84 +825,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -910,44 +913,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -956,76 +960,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2243,8 +2247,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2281,17 +2285,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3277,9 +3277,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3310,6 +3310,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3492,13 +3495,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3513,7 +3509,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3527,19 +3522,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3717,180 +3712,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4556,6 +4561,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4613,72 +4619,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4721,9 +4727,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -4806,6 +4812,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -4814,6 +4837,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -10825,8 +10849,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -10987,8 +11013,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -11004,8 +11038,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -11054,8 +11096,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -11423,6 +11473,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -11515,12 +11568,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -13056,9 +13103,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -13067,17 +13111,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -13997,9 +14030,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -14116,8 +14154,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -14619,15 +14659,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -14830,10 +14867,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -14851,6 +14888,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -15727,9 +15767,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -36358,8 +36398,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h index 5e42245f2a..0971aefc68 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h @@ -336,20 +336,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; @@ -859,84 +859,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -944,44 +947,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -990,76 +994,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2277,8 +2281,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2315,17 +2319,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3363,9 +3363,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3396,6 +3396,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3578,13 +3581,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3599,7 +3595,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3613,19 +3608,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3803,180 +3798,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4642,6 +4647,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4699,72 +4705,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4807,9 +4813,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -4892,6 +4898,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -4900,6 +4923,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -11056,8 +11080,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -11218,8 +11244,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -11235,8 +11269,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -11285,8 +11327,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -11654,6 +11704,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -11746,12 +11799,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -13287,9 +13334,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -13298,17 +13342,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -14228,9 +14261,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -14347,8 +14385,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -14850,15 +14890,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -15061,10 +15098,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -15082,6 +15119,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -15958,9 +15998,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -36589,8 +36629,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h index 55c61fa1d0..4c20c60f26 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h @@ -302,20 +302,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; @@ -825,84 +825,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -910,44 +913,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -956,76 +960,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2243,8 +2247,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2281,17 +2285,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3329,9 +3329,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3362,6 +3362,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3544,13 +3547,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3565,7 +3561,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3579,19 +3574,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3769,180 +3764,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4608,6 +4613,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4665,72 +4671,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4773,9 +4779,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -4858,6 +4864,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -4866,6 +4889,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -11022,8 +11046,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -11184,8 +11210,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -11201,8 +11235,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -11251,8 +11293,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -11620,6 +11670,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -11712,12 +11765,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -13253,9 +13300,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -13264,17 +13308,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -14194,9 +14227,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -14313,8 +14351,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -14816,15 +14856,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -15027,10 +15064,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -15048,6 +15085,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -15924,9 +15964,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -36555,8 +36595,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h index 190417e0c7..91c214464d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h @@ -336,20 +336,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; @@ -859,84 +859,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -944,44 +947,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -990,76 +994,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2277,8 +2281,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2315,17 +2319,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3311,9 +3311,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3344,6 +3344,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3526,13 +3529,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3547,7 +3543,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3561,19 +3556,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3751,180 +3746,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4590,6 +4595,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4647,72 +4653,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4755,9 +4761,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -4840,6 +4846,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -4848,6 +4871,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -10859,8 +10883,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -11021,8 +11047,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -11038,8 +11072,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -11088,8 +11130,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -11457,6 +11507,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -11549,12 +11602,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -13090,9 +13137,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -13101,17 +13145,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -14031,9 +14064,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -14150,8 +14188,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -14653,15 +14693,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -14864,10 +14901,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -14885,6 +14922,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -15761,9 +15801,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -36392,8 +36432,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h index 62d1c57923..fc803ecd84 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h @@ -302,20 +302,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; @@ -825,84 +825,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -910,44 +913,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -956,76 +960,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2243,8 +2247,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2281,17 +2285,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3277,9 +3277,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3310,6 +3310,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3492,13 +3495,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3513,7 +3509,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3527,19 +3522,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3717,180 +3712,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4556,6 +4561,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4613,72 +4619,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4721,9 +4727,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -4806,6 +4812,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -4814,6 +4837,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -10825,8 +10849,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -10987,8 +11013,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -11004,8 +11038,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -11054,8 +11096,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -11423,6 +11473,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -11515,12 +11568,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -13056,9 +13103,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -13067,17 +13111,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -13997,9 +14030,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -14116,8 +14154,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -14619,15 +14659,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -14830,10 +14867,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -14851,6 +14888,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -15727,9 +15767,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -36358,8 +36398,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h index 8fef3b75dc..c99a1bd5a6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h @@ -336,20 +336,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; @@ -859,84 +859,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -944,44 +947,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -990,76 +994,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2277,8 +2281,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2315,17 +2319,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3363,9 +3363,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3396,6 +3396,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3578,13 +3581,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3599,7 +3595,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3613,19 +3608,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3803,180 +3798,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4642,6 +4647,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4699,72 +4705,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4807,9 +4813,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -4892,6 +4898,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -4900,6 +4923,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -11056,8 +11080,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -11218,8 +11244,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -11235,8 +11269,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -11285,8 +11327,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -11654,6 +11704,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -11746,12 +11799,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -13287,9 +13334,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -13298,17 +13342,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -14228,9 +14261,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -14347,8 +14385,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -14850,15 +14890,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -15061,10 +15098,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -15082,6 +15119,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -15958,9 +15998,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -36589,8 +36629,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h index 2f0cd48019..55aa467235 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h @@ -302,20 +302,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; @@ -825,84 +825,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -910,44 +913,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -956,76 +960,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2243,8 +2247,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2281,17 +2285,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3329,9 +3329,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3362,6 +3362,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3544,13 +3547,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3565,7 +3561,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3579,19 +3574,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3769,180 +3764,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4608,6 +4613,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4665,72 +4671,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4773,9 +4779,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -4858,6 +4864,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -4866,6 +4889,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -11022,8 +11046,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -11184,8 +11210,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -11201,8 +11235,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -11251,8 +11293,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -11620,6 +11670,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -11712,12 +11765,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -13253,9 +13300,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -13264,17 +13308,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -14194,9 +14227,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -14313,8 +14351,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -14816,15 +14856,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -15027,10 +15064,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -15048,6 +15085,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -15924,9 +15964,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -36555,8 +36595,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h index b19da6d580..b5db1fee7f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h @@ -336,20 +336,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; /** @@ -960,84 +960,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -1045,44 +1048,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -1091,76 +1095,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2378,8 +2382,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2416,17 +2420,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3421,9 +3421,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3454,6 +3454,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3636,13 +3639,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3657,7 +3653,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3671,19 +3666,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3861,180 +3856,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4700,6 +4705,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4757,72 +4763,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4865,9 +4871,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -4950,6 +4956,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -4958,6 +4981,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -12410,8 +12434,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -12572,8 +12598,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -12589,8 +12623,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -12639,8 +12681,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -13008,6 +13058,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -13100,12 +13153,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -14641,9 +14688,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -14652,17 +14696,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -15582,9 +15615,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -15701,8 +15739,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -16204,15 +16244,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -16415,10 +16452,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16436,6 +16473,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -17312,9 +17352,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -37948,8 +37988,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_cm4.h index db1b9d82dc..a2b6a74dbc 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_cm4.h @@ -302,20 +302,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; /** @@ -926,84 +926,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -1011,44 +1014,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -1057,76 +1061,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2344,8 +2348,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2382,17 +2386,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3387,9 +3387,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3420,6 +3420,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3602,13 +3605,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3623,7 +3619,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3637,19 +3632,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3827,180 +3822,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4666,6 +4671,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4723,72 +4729,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4831,9 +4837,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -4916,6 +4922,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -4924,6 +4947,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -12376,8 +12400,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -12538,8 +12564,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -12555,8 +12589,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -12605,8 +12647,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -12974,6 +13024,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -13066,12 +13119,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -14607,9 +14654,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -14618,17 +14662,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -15548,9 +15581,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -15667,8 +15705,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -16170,15 +16210,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -16381,10 +16418,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16402,6 +16439,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -17278,9 +17318,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -37914,8 +37954,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h index b07db7e23b..2d97a3b070 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h @@ -336,20 +336,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; /** @@ -960,84 +960,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -1045,44 +1048,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -1091,76 +1095,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2378,8 +2382,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2416,17 +2420,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3473,9 +3473,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3506,6 +3506,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3688,13 +3691,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3709,7 +3705,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3723,19 +3718,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3913,180 +3908,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4752,6 +4757,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4809,72 +4815,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4917,9 +4923,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -5002,6 +5008,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -5010,6 +5033,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -12607,8 +12631,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -12769,8 +12795,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -12786,8 +12820,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -12836,8 +12878,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -13205,6 +13255,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -13297,12 +13350,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -14838,9 +14885,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -14849,17 +14893,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -15779,9 +15812,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -15898,8 +15936,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -16401,15 +16441,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -16612,10 +16649,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16633,6 +16670,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -17509,9 +17549,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -38145,8 +38185,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h index 981371e803..7ffbf5616b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h @@ -302,20 +302,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; /** @@ -926,84 +926,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -1011,44 +1014,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -1057,76 +1061,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2344,8 +2348,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2382,17 +2386,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3439,9 +3439,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3472,6 +3472,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3654,13 +3657,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3675,7 +3671,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3689,19 +3684,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3879,180 +3874,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4718,6 +4723,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4775,72 +4781,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4883,9 +4889,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -4968,6 +4974,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -4976,6 +4999,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -12573,8 +12597,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -12735,8 +12761,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -12752,8 +12786,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -12802,8 +12844,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -13171,6 +13221,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -13263,12 +13316,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -14804,9 +14851,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -14815,17 +14859,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -15745,9 +15778,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -15864,8 +15902,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -16367,15 +16407,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -16578,10 +16615,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16599,6 +16636,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -17475,9 +17515,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -38111,8 +38151,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h index 7b02d32155..73f0752ecb 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h @@ -336,20 +336,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; /** @@ -960,84 +960,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -1045,44 +1048,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -1091,76 +1095,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2378,8 +2382,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2416,17 +2420,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3421,9 +3421,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3454,6 +3454,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3636,13 +3639,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3657,7 +3653,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3671,19 +3666,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3861,180 +3856,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4700,6 +4705,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4757,72 +4763,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4865,9 +4871,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -4950,6 +4956,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -4958,6 +4981,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -12410,8 +12434,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -12572,8 +12598,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -12589,8 +12623,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -12639,8 +12681,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -13008,6 +13058,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -13100,12 +13153,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -14641,9 +14688,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -14652,17 +14696,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -15582,9 +15615,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -15701,8 +15739,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -16204,15 +16244,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -16415,10 +16452,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16436,6 +16473,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -17312,9 +17352,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -37948,8 +37988,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h index 5253c4e723..e042be05e4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h @@ -302,20 +302,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; /** @@ -926,84 +926,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -1011,44 +1014,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -1057,76 +1061,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2344,8 +2348,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2382,17 +2386,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3387,9 +3387,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3420,6 +3420,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3602,13 +3605,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3623,7 +3619,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3637,19 +3632,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3827,180 +3822,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4666,6 +4671,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4723,72 +4729,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4831,9 +4837,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -4916,6 +4922,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -4924,6 +4947,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -12376,8 +12400,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -12538,8 +12564,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -12555,8 +12589,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -12605,8 +12647,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -12974,6 +13024,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -13066,12 +13119,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -14607,9 +14654,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -14618,17 +14662,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -15548,9 +15581,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -15667,8 +15705,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -16170,15 +16210,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -16381,10 +16418,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16402,6 +16439,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -17278,9 +17318,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -37914,8 +37954,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h index b8f727415b..cce0f906d4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h @@ -336,20 +336,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; /** @@ -960,84 +960,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -1045,44 +1048,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -1091,76 +1095,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2378,8 +2382,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2416,17 +2420,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3473,9 +3473,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3506,6 +3506,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3688,13 +3691,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3709,7 +3705,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3723,19 +3718,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3913,180 +3908,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4752,6 +4757,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4809,72 +4815,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4917,9 +4923,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -5002,6 +5008,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -5010,6 +5033,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -12607,8 +12631,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -12769,8 +12795,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -12786,8 +12820,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -12836,8 +12878,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -13205,6 +13255,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -13297,12 +13350,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -14838,9 +14885,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -14849,17 +14893,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -15779,9 +15812,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -15898,8 +15936,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -16401,15 +16441,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -16612,10 +16649,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16633,6 +16670,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -17509,9 +17549,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -38145,8 +38185,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h index f2fbefcd3c..8dd51b35ba 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h @@ -302,20 +302,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; /** @@ -926,84 +926,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -1011,44 +1014,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -1057,76 +1061,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2344,8 +2348,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2382,17 +2386,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3439,9 +3439,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3472,6 +3472,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3654,13 +3657,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3675,7 +3671,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3689,19 +3684,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3879,180 +3874,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4718,6 +4723,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4775,72 +4781,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4883,9 +4889,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -4968,6 +4974,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -4976,6 +4999,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -12573,8 +12597,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -12735,8 +12761,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -12752,8 +12786,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -12802,8 +12844,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -13171,6 +13221,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -13263,12 +13316,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -14804,9 +14851,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -14815,17 +14859,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -15745,9 +15778,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -15864,8 +15902,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -16367,15 +16407,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -16578,10 +16615,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16599,6 +16636,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -17475,9 +17515,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -38111,8 +38151,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h index a4799ba120..40b8804965 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h @@ -336,20 +336,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; /** @@ -1047,84 +1047,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -1132,44 +1135,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -1178,76 +1182,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2465,8 +2469,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2503,17 +2507,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3536,9 +3536,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3569,6 +3569,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3751,13 +3754,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3772,7 +3768,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3786,19 +3781,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3976,180 +3971,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4815,6 +4820,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4872,72 +4878,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4980,9 +4986,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -5065,6 +5071,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -5073,6 +5096,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -12525,8 +12549,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -12687,8 +12713,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -12704,8 +12738,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -12754,8 +12796,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -13123,6 +13173,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -13215,12 +13268,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -14756,9 +14803,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -14767,17 +14811,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -15697,9 +15730,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -15816,8 +15854,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -16319,15 +16359,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -16530,10 +16567,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16551,6 +16588,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -17427,9 +17467,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -39171,8 +39211,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h index dff41df86c..12bb087023 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h @@ -302,20 +302,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; /** @@ -1013,84 +1013,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -1098,44 +1101,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -1144,76 +1148,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2431,8 +2435,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2469,17 +2473,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3502,9 +3502,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3535,6 +3535,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3717,13 +3720,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3738,7 +3734,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3752,19 +3747,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3942,180 +3937,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4781,6 +4786,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4838,72 +4844,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4946,9 +4952,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -5031,6 +5037,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -5039,6 +5062,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -12491,8 +12515,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -12653,8 +12679,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -12670,8 +12704,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -12720,8 +12762,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -13089,6 +13139,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -13181,12 +13234,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -14722,9 +14769,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -14733,17 +14777,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -15663,9 +15696,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -15782,8 +15820,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -16285,15 +16325,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -16496,10 +16533,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16517,6 +16554,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -17393,9 +17433,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -39137,8 +39177,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h index 037be04358..fd2409a59d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h @@ -336,20 +336,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; /** @@ -1047,84 +1047,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -1132,44 +1135,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -1178,76 +1182,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2465,8 +2469,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2503,17 +2507,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3588,9 +3588,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3621,6 +3621,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3803,13 +3806,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3824,7 +3820,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3838,19 +3833,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -4028,180 +4023,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4867,6 +4872,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4924,72 +4930,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -5032,9 +5038,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -5117,6 +5123,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -5125,6 +5148,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -12722,8 +12746,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -12884,8 +12910,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -12901,8 +12935,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -12951,8 +12993,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -13320,6 +13370,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -13412,12 +13465,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -14953,9 +15000,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -14964,17 +15008,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -15894,9 +15927,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -16013,8 +16051,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -16516,15 +16556,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -16727,10 +16764,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16748,6 +16785,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -17624,9 +17664,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -39368,8 +39408,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h index cfe0c83387..9b4f1f67b2 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h @@ -302,20 +302,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; /** @@ -1013,84 +1013,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -1098,44 +1101,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -1144,76 +1148,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2431,8 +2435,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2469,17 +2473,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3554,9 +3554,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3587,6 +3587,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3769,13 +3772,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3790,7 +3786,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3804,19 +3799,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3994,180 +3989,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4833,6 +4838,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4890,72 +4896,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4998,9 +5004,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -5083,6 +5089,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -5091,6 +5114,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -12688,8 +12712,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -12850,8 +12876,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -12867,8 +12901,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -12917,8 +12959,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -13286,6 +13336,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -13378,12 +13431,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -14919,9 +14966,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -14930,17 +14974,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -15860,9 +15893,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -15979,8 +16017,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -16482,15 +16522,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -16693,10 +16730,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16714,6 +16751,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -17590,9 +17630,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -39334,8 +39374,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h index 05f51c2a88..338413ee3e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h @@ -336,20 +336,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; /** @@ -1047,84 +1047,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -1132,44 +1135,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -1178,76 +1182,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2465,8 +2469,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2503,17 +2507,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3536,9 +3536,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3569,6 +3569,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3751,13 +3754,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3772,7 +3768,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3786,19 +3781,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3976,180 +3971,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4815,6 +4820,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4872,72 +4878,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4980,9 +4986,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -5065,6 +5071,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -5073,6 +5096,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -12525,8 +12549,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -12687,8 +12713,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -12704,8 +12738,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -12754,8 +12796,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -13123,6 +13173,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -13215,12 +13268,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -14756,9 +14803,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -14767,17 +14811,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -15697,9 +15730,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -15816,8 +15854,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -16319,15 +16359,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -16530,10 +16567,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16551,6 +16588,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -17427,9 +17467,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -39171,8 +39211,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h index 85f876e606..0f879dcd3d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h @@ -302,20 +302,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; /** @@ -1013,84 +1013,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -1098,44 +1101,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -1144,76 +1148,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2431,8 +2435,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2469,17 +2473,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3502,9 +3502,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3535,6 +3535,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3717,13 +3720,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3738,7 +3734,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3752,19 +3747,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3942,180 +3937,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4781,6 +4786,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4838,72 +4844,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4946,9 +4952,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -5031,6 +5037,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -5039,6 +5062,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -12491,8 +12515,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -12653,8 +12679,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -12670,8 +12704,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -12720,8 +12762,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -13089,6 +13139,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -13181,12 +13234,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -14722,9 +14769,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -14733,17 +14777,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -15663,9 +15696,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -15782,8 +15820,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -16285,15 +16325,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -16496,10 +16533,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16517,6 +16554,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -17393,9 +17433,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -39137,8 +39177,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h index ee44fd108f..2245408793 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h @@ -336,20 +336,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; /** @@ -1047,84 +1047,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -1132,44 +1135,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -1178,76 +1182,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2465,8 +2469,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2503,17 +2507,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3588,9 +3588,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3621,6 +3621,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3803,13 +3806,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3824,7 +3820,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3838,19 +3833,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -4028,180 +4023,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4867,6 +4872,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4924,72 +4930,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -5032,9 +5038,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -5117,6 +5123,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -5125,6 +5148,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -12722,8 +12746,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -12884,8 +12910,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -12901,8 +12935,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -12951,8 +12993,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -13320,6 +13370,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -13412,12 +13465,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -14953,9 +15000,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -14964,17 +15008,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -15894,9 +15927,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -16013,8 +16051,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -16516,15 +16556,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -16727,10 +16764,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16748,6 +16785,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -17624,9 +17664,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -39368,8 +39408,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h index 1524be361a..987fcda9a8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h @@ -302,20 +302,20 @@ typedef struct __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ - __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ } ADC_TypeDef; - typedef struct { - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ - __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC12 base address + 0x00 */ + uint32_t RESERVED; /*!< Reserved, ADC12 base address + 0x04 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC12 base address + 0x08 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC12 base address + 0x0C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC12 base address + 0x10 */ + uint32_t RESERVED1[55]; /*!< Reserved, 0x14 - 0xEC */ + __I uint32_t HWCFGR0; /*!< ADC version register, Address offset: 0xF0 */ + __I uint32_t VERR; /*!< ADC version register, Address offset: 0xF4 */ + __I uint32_t IPIDR; /*!< ADC ID register, Address offset: 0xF8 */ + __I uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0xFC */ } ADC_Common_TypeDef; /** @@ -1013,84 +1013,87 @@ typedef struct __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ - __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + uint32_t MACRXQCR; /*!< Rx Queue control register Address offset: 0x0094 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved Address offset: 0x0098-0x009C */ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00BC */ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ - uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + uint32_t RESERVED8[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ - uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + uint32_t RESERVED9[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ - uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + uint32_t RESERVED10[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ - uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x0118 */ + __IO uint32_t MACHWF0R; /*!< HW feature 0 register Address offset: 0x011C */ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ - uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACHWF3R; /*!< HW feature 3 register Address offset: 0x0128 */ + uint32_t RESERVED12[53]; /*!< Reserved Address offset: 0x012C-0x01FC */ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ - uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ - __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ - __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ - __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ - __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ - __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ - __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ - __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ - __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ - uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x0208-0x020C */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0210 */ + uint32_t RESERVED14[7]; /*!< Reserved Address offset: 0x0214-0x022C */ + __IO uint32_t MACCSRSWCR; /*!< CSR software control register Address offset: 0x0230 */ + uint32_t RESERVED15[51]; /*!< Reserved Address offset: 0x0234-0x02FC */ + __IO uint32_t MACA0HR; /*!< MAC Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< MAC Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< MAC Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< MAC Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< MAC Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< MAC Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< MAC Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< MAC Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED16[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ - __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ - uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ - __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ - __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ - uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ - __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ - uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ - __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ - __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ - uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ - __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ - uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ - __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ - __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ - __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ - __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ - uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED17[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED18[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED19[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED20[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED21[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED22[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ - uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + uint32_t RESERVED23[2]; /*!< Reserved Address offset: 0x0908-0x090C */ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ - uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + uint32_t RESERVED24[4]; /*!< Reserved Address offset: 0x0920-0x092C */ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ - uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + uint32_t RESERVED25[2]; /*!< Reserved Address offset: 0x0938-0x093C */ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ - uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ - __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ - uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + uint32_t RESERVED26[108]; /*!< Reserved Address offset: 0x0950-0x0AFC */ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ @@ -1098,44 +1101,45 @@ typedef struct __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ - uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + uint32_t RESERVED27; /*!< Reserved Address offset: 0x0B1C */ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ - uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + uint32_t RESERVED28[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ - uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + uint32_t RESERVED29[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ - uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + uint32_t RESERVED30; /*!< Reserved Address offset: 0x0B44 */ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ - uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + uint32_t RESERVED31[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ - uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + uint32_t RESERVED32[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ - uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + uint32_t RESERVED33[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ - uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + uint32_t RESERVED34[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ - uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + uint32_t RESERVED35[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ - uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + uint32_t RESERVED36[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ - uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ - __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ - uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + uint32_t RESERVED37[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue 0 ETS status Register Address offset: 0x0D14 */ + __IO uint32_t MTLTXQ0QWR; /*!< Tx queue 0 quantum weight Register Address offset: 0x0D18 */ + uint32_t RESERVED38[4]; /*!< Reserved Address offset: 0x0D1C-0x0D28 */ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ @@ -1144,76 +1148,76 @@ typedef struct __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ - uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + uint32_t RESERVED39; /*!< Reserved Address offset: 0x0D4C */ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ - __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + uint32_t MTLTXTXQ1ESR; /*!< Tx queue 1 ETS status Register Address offset: 0x0D54 */ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ - uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x0D68 */ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ - uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + uint32_t RESERVED42[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ - uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + uint32_t RESERVED43[4]; /*!< Reserved Address offset: 0x1010-0x101C */ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ - uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + uint32_t RESERVED44[5]; /*!< Reserved Address offset: 0x102C-0x103C */ + __IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register Address offset: 0x1040 */ + uint32_t RESERVED45[47]; /*!< Reserved Address offset: 0x1044-0x10FC */ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ - uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ - uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + uint32_t RESERVED47; /*!< Reserved Address offset: 0x1118 */ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ - uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + uint32_t RESERVED48; /*!< Reserved Address offset: 0x1124 */ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ - uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + uint32_t RESERVED49; /*!< Reserved Address offset: 0x1140 */ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ - uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + uint32_t RESERVED50; /*!< Reserved Address offset: 0x1148 */ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ - uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x1150 */ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ - uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x1158 */ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ - uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ - __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ - uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x1164 */ + uint32_t RESERVED53[6]; /*!< Reserved Address offset: 0x1168-0x117C */ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ - uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ - uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x1198-0x119C */ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ - uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ - uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + uint32_t RESERVED57; /*!< Reserved Address offset: 0x11B0 */ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ - uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + uint32_t RESERVED58; /*!< Reserved Address offset: 0x11B8 */ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ - uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + uint32_t RESERVED59; /*!< Reserved Address offset: 0x11C0 */ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ - uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + uint32_t RESERVED60[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ - uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + uint32_t RESERVED61[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ - uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ - __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11E4 */ } ETH_TypeDef; /** @@ -2431,8 +2435,8 @@ typedef struct __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */ @@ -2469,17 +2473,13 @@ typedef struct __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */ @@ -3554,9 +3554,9 @@ typedef struct #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ @@ -3587,6 +3587,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -3769,13 +3772,6 @@ typedef struct #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ @@ -3790,7 +3786,6 @@ typedef struct #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - #define ADC_CFGR2_RSHIFT1_Pos (11U) #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ @@ -3804,19 +3799,19 @@ typedef struct #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ -#define ADC_CFGR2_OSR_Pos (16U) -#define ADC_CFGR2_OSR_Msk (0x3FFUL << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OSR_0 (0x001UL << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OSR_1 (0x002UL << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OSR_2 (0x004UL << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OSR_3 (0x008UL << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OSR_4 (0x010UL << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OSR_5 (0x020UL << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OSR_6 (0x040UL << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OSR_7 (0x080UL << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OSR_8 (0x100UL << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OSR_9 (0x200UL << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_OSVR_Pos (16U) +#define ADC_CFGR2_OSVR_Msk (0x3FFUL << ADC_CFGR2_OSVR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OSVR ADC_CFGR2_OSVR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OSVR_0 (0x001UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OSVR_1 (0x002UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OSVR_2 (0x004UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OSVR_3 (0x008UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OSVR_4 (0x010UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OSVR_5 (0x020UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OSVR_6 (0x040UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OSVR_7 (0x080UL << ADC_CFGR2_OSVR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OSVR_8 (0x100UL << ADC_CFGR2_OSVR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OSVR_9 (0x200UL << ADC_CFGR2_OSVR_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_LSHIFT_Pos (28U) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ @@ -3994,180 +3989,190 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_LTR1 register ********************/ -#define ADC_LTR1_LT1_Pos (0U) -#define ADC_LTR1_LT1_Msk (0x3FFFFFFUL << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */ -#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */ -#define ADC_LTR1_LT1_0 (0x0000001UL << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_LTR1_LT1_1 (0x0000002UL << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_LTR1_LT1_2 (0x0000004UL << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_LTR1_LT1_3 (0x0000008UL << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_LTR1_LT1_4 (0x0000010UL << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_LTR1_LT1_5 (0x0000020UL << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_LTR1_LT1_6 (0x0000040UL << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_LTR1_LT1_7 (0x0000080UL << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_LTR1_LT1_8 (0x0000100UL << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_LTR1_LT1_9 (0x0000200UL << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_LTR1_LT1_10 (0x0000400UL << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_LTR1_LT1_11 (0x0000800UL << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_LTR1_LT1_12 (0x0001000UL << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */ -#define ADC_LTR1_LT1_13 (0x0002000UL << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */ -#define ADC_LTR1_LT1_14 (0x0004000UL << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */ -#define ADC_LTR1_LT1_15 (0x0008000UL << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */ -#define ADC_LTR1_LT1_16 (0x0010000UL << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */ -#define ADC_LTR1_LT1_17 (0x0020000UL << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */ -#define ADC_LTR1_LT1_18 (0x0040000UL << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */ -#define ADC_LTR1_LT1_19 (0x0080000UL << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */ -#define ADC_LTR1_LT1_20 (0x0100000UL << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */ -#define ADC_LTR1_LT1_21 (0x0200000UL << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */ -#define ADC_LTR1_LT1_22 (0x0400000UL << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */ -#define ADC_LTR1_LT1_23 (0x0800000UL << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */ -#define ADC_LTR1_LT1_24 (0x1000000UL << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */ -#define ADC_LTR1_LT1_25 (0x2000000UL << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */ +#define ADC_LTR1_LTR1_Pos (0U) +#define ADC_LTR1_LTR1_Msk (0x3FFFFFFUL << ADC_LTR1_LTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR1_LTR1 ADC_LTR1_LTR1_Msk /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_LTR1_LTR1_0 (0x0000001UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000001 */ +#define ADC_LTR1_LTR1_1 (0x0000002UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000002 */ +#define ADC_LTR1_LTR1_2 (0x0000004UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000004 */ +#define ADC_LTR1_LTR1_3 (0x0000008UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000008 */ +#define ADC_LTR1_LTR1_4 (0x0000010UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000010 */ +#define ADC_LTR1_LTR1_5 (0x0000020UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000020 */ +#define ADC_LTR1_LTR1_6 (0x0000040UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000040 */ +#define ADC_LTR1_LTR1_7 (0x0000080UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000080 */ +#define ADC_LTR1_LTR1_8 (0x0000100UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000100 */ +#define ADC_LTR1_LTR1_9 (0x0000200UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000200 */ +#define ADC_LTR1_LTR1_10 (0x0000400UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000400 */ +#define ADC_LTR1_LTR1_11 (0x0000800UL << ADC_LTR1_LTR1_Pos) /*!< 0x00000800 */ +#define ADC_LTR1_LTR1_12 (0x0001000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00001000 */ +#define ADC_LTR1_LTR1_13 (0x0002000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00002000 */ +#define ADC_LTR1_LTR1_14 (0x0004000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00004000 */ +#define ADC_LTR1_LTR1_15 (0x0008000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00008000 */ +#define ADC_LTR1_LTR1_16 (0x0010000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00010000 */ +#define ADC_LTR1_LTR1_17 (0x0020000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00020000 */ +#define ADC_LTR1_LTR1_18 (0x0040000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00040000 */ +#define ADC_LTR1_LTR1_19 (0x0080000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00080000 */ +#define ADC_LTR1_LTR1_20 (0x0100000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00100000 */ +#define ADC_LTR1_LTR1_21 (0x0200000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00200000 */ +#define ADC_LTR1_LTR1_22 (0x0400000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00400000 */ +#define ADC_LTR1_LTR1_23 (0x0800000UL << ADC_LTR1_LTR1_Pos) /*!< 0x00800000 */ +#define ADC_LTR1_LTR1_24 (0x1000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x01000000 */ +#define ADC_LTR1_LTR1_25 (0x2000000UL << ADC_LTR1_LTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR1 register ********************/ -#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */ -#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */ -#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */ -#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */ -#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */ -#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */ -#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */ -#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */ -#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */ -#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */ -#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */ -#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */ -#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */ -#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */ -#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */ -#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */ -#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */ -#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */ -#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */ -#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */ -#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */ -#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */ -#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */ -#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */ -#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */ -#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ -#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ +#define ADC_HTR1_HTR1_Pos (0U) +#define ADC_HTR1_HTR1_Msk (0x3FFFFFFUL << ADC_HTR1_HTR1_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR1_HTR1 ADC_HTR1_HTR1_Msk /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_HTR1_HTR1_0 (0x0000001UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000001 */ +#define ADC_HTR1_HTR1_1 (0x0000002UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000002 */ +#define ADC_HTR1_HTR1_2 (0x0000004UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000004 */ +#define ADC_HTR1_HTR1_3 (0x0000008UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000008 */ +#define ADC_HTR1_HTR1_4 (0x0000010UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000010 */ +#define ADC_HTR1_HTR1_5 (0x0000020UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000020 */ +#define ADC_HTR1_HTR1_6 (0x0000040UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000040 */ +#define ADC_HTR1_HTR1_7 (0x0000080UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000080 */ +#define ADC_HTR1_HTR1_8 (0x0000100UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000100 */ +#define ADC_HTR1_HTR1_9 (0x0000200UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000200 */ +#define ADC_HTR1_HTR1_10 (0x0000400UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000400 */ +#define ADC_HTR1_HTR1_11 (0x0000800UL << ADC_HTR1_HTR1_Pos) /*!< 0x00000800 */ +#define ADC_HTR1_HTR1_12 (0x0001000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00001000 */ +#define ADC_HTR1_HTR1_13 (0x0002000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00002000 */ +#define ADC_HTR1_HTR1_14 (0x0004000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00004000 */ +#define ADC_HTR1_HTR1_15 (0x0008000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00008000 */ +#define ADC_HTR1_HTR1_16 (0x0010000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00010000 */ +#define ADC_HTR1_HTR1_17 (0x0020000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00020000 */ +#define ADC_HTR1_HTR1_18 (0x0040000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00040000 */ +#define ADC_HTR1_HTR1_19 (0x0080000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00080000 */ +#define ADC_HTR1_HTR1_20 (0x0100000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00100000 */ +#define ADC_HTR1_HTR1_21 (0x0200000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00200000 */ +#define ADC_HTR1_HTR1_22 (0x0400000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00400000 */ +#define ADC_HTR1_HTR1_23 (0x0800000UL << ADC_HTR1_HTR1_Pos) /*!< 0x00800000 */ +#define ADC_HTR1_HTR1_24 (0x1000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x01000000 */ +#define ADC_HTR1_HTR1_25 (0x2000000UL << ADC_HTR1_HTR1_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR2 register ********************/ -#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ -#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ -#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ -#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ -#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ -#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ -#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ -#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ -#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ -#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */ -#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */ -#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */ -#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */ -#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */ -#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */ -#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */ -#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */ -#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */ -#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */ -#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */ -#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */ -#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */ -#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */ -#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */ -#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */ -#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */ -#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */ +#define ADC_LTR2_LTR2_Pos (0U) +#define ADC_LTR2_LTR2_Msk (0x3FFFFFFUL << ADC_LTR2_LTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR2_LTR2 ADC_LTR2_LTR2_Msk /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_LTR2_LTR2_0 (0x0000001UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000001 */ +#define ADC_LTR2_LTR2_1 (0x0000002UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000002 */ +#define ADC_LTR2_LTR2_2 (0x0000004UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000004 */ +#define ADC_LTR2_LTR2_3 (0x0000008UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000008 */ +#define ADC_LTR2_LTR2_4 (0x0000010UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000010 */ +#define ADC_LTR2_LTR2_5 (0x0000020UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000020 */ +#define ADC_LTR2_LTR2_6 (0x0000040UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000040 */ +#define ADC_LTR2_LTR2_7 (0x0000080UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000080 */ +#define ADC_LTR2_LTR2_8 (0x0000100UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000100 */ +#define ADC_LTR2_LTR2_9 (0x0000200UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000200 */ +#define ADC_LTR2_LTR2_10 (0x0000400UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000400 */ +#define ADC_LTR2_LTR2_11 (0x0000800UL << ADC_LTR2_LTR2_Pos) /*!< 0x00000800 */ +#define ADC_LTR2_LTR2_12 (0x0001000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00001000 */ +#define ADC_LTR2_LTR2_13 (0x0002000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00002000 */ +#define ADC_LTR2_LTR2_14 (0x0004000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00004000 */ +#define ADC_LTR2_LTR2_15 (0x0008000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00008000 */ +#define ADC_LTR2_LTR2_16 (0x0010000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00010000 */ +#define ADC_LTR2_LTR2_17 (0x0020000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00020000 */ +#define ADC_LTR2_LTR2_18 (0x0040000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00040000 */ +#define ADC_LTR2_LTR2_19 (0x0080000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00080000 */ +#define ADC_LTR2_LTR2_20 (0x0100000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00100000 */ +#define ADC_LTR2_LTR2_21 (0x0200000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00200000 */ +#define ADC_LTR2_LTR2_22 (0x0400000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00400000 */ +#define ADC_LTR2_LTR2_23 (0x0800000UL << ADC_LTR2_LTR2_Pos) /*!< 0x00800000 */ +#define ADC_LTR2_LTR2_24 (0x1000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x01000000 */ +#define ADC_LTR2_LTR2_25 (0x2000000UL << ADC_LTR2_LTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR2 register ********************/ -#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */ -#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */ -#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */ -#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */ -#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */ -#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */ -#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */ -#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */ -#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */ -#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */ -#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */ -#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */ -#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */ -#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */ -#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */ -#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */ -#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */ -#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */ -#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */ -#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */ -#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */ -#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */ -#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */ -#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */ -#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */ -#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */ -#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */ +#define ADC_HTR2_HTR2_Pos (0U) +#define ADC_HTR2_HTR2_Msk (0x3FFFFFFUL << ADC_HTR2_HTR2_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR2_HTR2 ADC_HTR2_HTR2_Msk /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_HTR2_HTR2_0 (0x0000001UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000001 */ +#define ADC_HTR2_HTR2_1 (0x0000002UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000002 */ +#define ADC_HTR2_HTR2_2 (0x0000004UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000004 */ +#define ADC_HTR2_HTR2_3 (0x0000008UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000008 */ +#define ADC_HTR2_HTR2_4 (0x0000010UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000010 */ +#define ADC_HTR2_HTR2_5 (0x0000020UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000020 */ +#define ADC_HTR2_HTR2_6 (0x0000040UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000040 */ +#define ADC_HTR2_HTR2_7 (0x0000080UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000080 */ +#define ADC_HTR2_HTR2_8 (0x0000100UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000100 */ +#define ADC_HTR2_HTR2_9 (0x0000200UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000200 */ +#define ADC_HTR2_HTR2_10 (0x0000400UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000400 */ +#define ADC_HTR2_HTR2_11 (0x0000800UL << ADC_HTR2_HTR2_Pos) /*!< 0x00000800 */ +#define ADC_HTR2_HTR2_12 (0x0001000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00001000 */ +#define ADC_HTR2_HTR2_13 (0x0002000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00002000 */ +#define ADC_HTR2_HTR2_14 (0x0004000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00004000 */ +#define ADC_HTR2_HTR2_15 (0x0008000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00008000 */ +#define ADC_HTR2_HTR2_16 (0x0010000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00010000 */ +#define ADC_HTR2_HTR2_17 (0x0020000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00020000 */ +#define ADC_HTR2_HTR2_18 (0x0040000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00040000 */ +#define ADC_HTR2_HTR2_19 (0x0080000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00080000 */ +#define ADC_HTR2_HTR2_20 (0x0100000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00100000 */ +#define ADC_HTR2_HTR2_21 (0x0200000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00200000 */ +#define ADC_HTR2_HTR2_22 (0x0400000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00400000 */ +#define ADC_HTR2_HTR2_23 (0x0800000UL << ADC_HTR2_HTR2_Pos) /*!< 0x00800000 */ +#define ADC_HTR2_HTR2_24 (0x1000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x01000000 */ +#define ADC_HTR2_HTR2_25 (0x2000000UL << ADC_HTR2_HTR2_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_LTR3 register ********************/ -#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */ -#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ -#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ -#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ -#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ -#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ -#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ -#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ -#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ -#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */ -#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */ -#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */ -#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */ -#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */ -#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */ -#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */ -#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */ -#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */ -#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */ -#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */ -#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */ -#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */ -#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */ -#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */ -#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */ -#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/ -#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */ +#define ADC_LTR3_LTR3_Pos (0U) +#define ADC_LTR3_LTR3_Msk (0x3FFFFFFUL << ADC_LTR3_LTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR3_LTR3 ADC_LTR3_LTR3_Msk /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_LTR3_LTR3_0 (0x0000001UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000001 */ +#define ADC_LTR3_LTR3_1 (0x0000002UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000002 */ +#define ADC_LTR3_LTR3_2 (0x0000004UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000004 */ +#define ADC_LTR3_LTR3_3 (0x0000008UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000008 */ +#define ADC_LTR3_LTR3_4 (0x0000010UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000010 */ +#define ADC_LTR3_LTR3_5 (0x0000020UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000020 */ +#define ADC_LTR3_LTR3_6 (0x0000040UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000040 */ +#define ADC_LTR3_LTR3_7 (0x0000080UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000080 */ +#define ADC_LTR3_LTR3_8 (0x0000100UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000100 */ +#define ADC_LTR3_LTR3_9 (0x0000200UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000200 */ +#define ADC_LTR3_LTR3_10 (0x0000400UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000400 */ +#define ADC_LTR3_LTR3_11 (0x0000800UL << ADC_LTR3_LTR3_Pos) /*!< 0x00000800 */ +#define ADC_LTR3_LTR3_12 (0x0001000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00001000 */ +#define ADC_LTR3_LTR3_13 (0x0002000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00002000 */ +#define ADC_LTR3_LTR3_14 (0x0004000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00004000 */ +#define ADC_LTR3_LTR3_15 (0x0008000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00008000 */ +#define ADC_LTR3_LTR3_16 (0x0010000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00010000 */ +#define ADC_LTR3_LTR3_17 (0x0020000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00020000 */ +#define ADC_LTR3_LTR3_18 (0x0040000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00040000 */ +#define ADC_LTR3_LTR3_19 (0x0080000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00080000 */ +#define ADC_LTR3_LTR3_20 (0x0100000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00100000 */ +#define ADC_LTR3_LTR3_21 (0x0200000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00200000 */ +#define ADC_LTR3_LTR3_22 (0x0400000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00400000 */ +#define ADC_LTR3_LTR3_23 (0x0800000UL << ADC_LTR3_LTR3_Pos) /*!< 0x00800000 */ +#define ADC_LTR3_LTR3_24 (0x1000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x01000000 */ +#define ADC_LTR3_LTR3_25 (0x2000000UL << ADC_LTR3_LTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_HTR3 register ********************/ -#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */ -#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */ -#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */ -#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */ -#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */ -#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */ -#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */ -#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */ -#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */ -#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */ -#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */ -#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */ -#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */ -#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */ -#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */ -#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */ -#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */ -#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */ -#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */ -#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */ -#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */ -#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */ -#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */ -#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */ -#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */ -#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */ -#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */ +#define ADC_HTR3_HTR3_Pos (0U) +#define ADC_HTR3_HTR3_Msk (0x3FFFFFFUL << ADC_HTR3_HTR3_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR3_HTR3 ADC_HTR3_HTR3_Msk /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_HTR3_HTR3_0 (0x0000001UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000001 */ +#define ADC_HTR3_HTR3_1 (0x0000002UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000002 */ +#define ADC_HTR3_HTR3_2 (0x0000004UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000004 */ +#define ADC_HTR3_HTR3_3 (0x0000008UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000008 */ +#define ADC_HTR3_HTR3_4 (0x0000010UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000010 */ +#define ADC_HTR3_HTR3_5 (0x0000020UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000020 */ +#define ADC_HTR3_HTR3_6 (0x0000040UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000040 */ +#define ADC_HTR3_HTR3_7 (0x0000080UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000080 */ +#define ADC_HTR3_HTR3_8 (0x0000100UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000100 */ +#define ADC_HTR3_HTR3_9 (0x0000200UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000200 */ +#define ADC_HTR3_HTR3_10 (0x0000400UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000400 */ +#define ADC_HTR3_HTR3_11 (0x0000800UL << ADC_HTR3_HTR3_Pos) /*!< 0x00000800 */ +#define ADC_HTR3_HTR3_12 (0x0001000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00001000 */ +#define ADC_HTR3_HTR3_13 (0x0002000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00002000 */ +#define ADC_HTR3_HTR3_14 (0x0004000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00004000 */ +#define ADC_HTR3_HTR3_15 (0x0008000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00008000 */ +#define ADC_HTR3_HTR3_16 (0x0010000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00010000 */ +#define ADC_HTR3_HTR3_17 (0x0020000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00020000 */ +#define ADC_HTR3_HTR3_18 (0x0040000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00040000 */ +#define ADC_HTR3_HTR3_19 (0x0080000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00080000 */ +#define ADC_HTR3_HTR3_20 (0x0100000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00100000 */ +#define ADC_HTR3_HTR3_21 (0x0200000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00200000 */ +#define ADC_HTR3_HTR3_22 (0x0400000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00400000 */ +#define ADC_HTR3_HTR3_23 (0x0800000UL << ADC_HTR3_HTR3_Pos) /*!< 0x00800000 */ +#define ADC_HTR3_HTR3_24 (0x1000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x01000000 */ +#define ADC_HTR3_HTR3_25 (0x2000000UL << ADC_HTR3_HTR3_Pos) /*!< 0x02000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) @@ -4833,6 +4838,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ + #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ @@ -4890,72 +4896,72 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) @@ -4998,9 +5004,9 @@ typedef struct #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ @@ -5083,6 +5089,23 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000UL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ +/***************** Bit definition for ADC_HWCFGR0 register ******************/ +#define ADC_HWCFGR0_ADC_NUM_Pos (0U) +#define ADC_HWCFGR0_ADC_NUM_Msk (0xFUL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x0000000F */ +#define ADC_HWCFGR0_ADC_NUM ADC_HWCFGR0_ADC_NUM_Msk /*!< Number of supported ADCs */ +#define ADC_HWCFGR0_ADC_NUM_0 (0x1UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000001 */ +#define ADC_HWCFGR0_ADC_NUM_1 (0x2UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000002 */ +#define ADC_HWCFGR0_ADC_NUM_2 (0x4UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000004 */ +#define ADC_HWCFGR0_ADC_NUM_3 (0x8UL << ADC_HWCFGR0_ADC_NUM_Pos) /*!< 0x00000008 */ + +#define ADC_HWCFGR0_FIFO_SIZE_Pos (4U) +#define ADC_HWCFGR0_FIFO_SIZE_Msk (0xFUL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x000000F0 */ +#define ADC_HWCFGR0_FIFO_SIZE ADC_HWCFGR0_FIFO_SIZE_Msk /*!< FIFO size */ +#define ADC_HWCFGR0_FIFO_SIZE_0 (0x1UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000010 */ +#define ADC_HWCFGR0_FIFO_SIZE_1 (0x2UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000020 */ +#define ADC_HWCFGR0_FIFO_SIZE_2 (0x4UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000040 */ +#define ADC_HWCFGR0_FIFO_SIZE_3 (0x8UL << ADC_HWCFGR0_FIFO_SIZE_Pos) /*!< 0x00000080 */ + /***************** Bit definition for ADC_VERR register ******************/ #define ADC_VERR_MINREV_Pos (0U) #define ADC_VERR_MINREV_Msk (0xFUL << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ @@ -5091,6 +5114,7 @@ typedef struct #define ADC_VERR_MINREV_1 (0x2UL << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ #define ADC_VERR_MINREV_2 (0x4UL << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ #define ADC_VERR_MINREV_3 (0x8UL << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ + #define ADC_VERR_MAJREV_Pos (4U) #define ADC_VERR_MAJREV_Msk (0xFUL << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ #define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ @@ -12688,8 +12712,10 @@ typedef struct #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */ -#define ETH_MACPFR_PCF_0 (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */ -#define ETH_MACPFR_PCF_1 (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */ +#define ETH_MACPFR_PCF_BLOCKALL (0x0UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000000 */ +#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA (0x1UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000010 */ +#define ETH_MACPFR_PCF_FORWARDALL (0x2UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000020 */ +#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x00000030 */ #define ETH_MACPFR_SAIF_Pos (8U) #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */ @@ -12850,8 +12876,16 @@ typedef struct #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_0 (0x1UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */ -#define ETH_MACVTR_EVLS_1 (0x2UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) +#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ +#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U) +#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */ +#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U) +#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */ +#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EVLRXS_Pos (24U) #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */ #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */ @@ -12867,8 +12901,16 @@ typedef struct #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_0 (0x1UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */ -#define ETH_MACVTR_EIVLS_1 (0x2UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) +#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U) +#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */ +#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U) +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */ +#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */ #define ETH_MACVTR_EIVLRXS_Pos (31U) #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */ #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */ @@ -12917,8 +12959,16 @@ typedef struct #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_0 (0x1UL << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */ -#define ETH_MACVIR_VLC_1 (0x2UL << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ +#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ +#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U) +#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */ +#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U) +#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */ +#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */ #define ETH_MACVIR_VLP_Pos (18U) #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */ #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */ @@ -13286,6 +13336,9 @@ typedef struct #define ETH_MACLCSR_LPITE_Pos (20U) #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */ #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */ +#define ETH_MACLCSR_LPITCSE_Pos (21U) +#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */ +#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */ /************** Bit definition for ETH_MACLTCR register **************/ #define ETH_MACLTCR_TWT_Pos (0U) @@ -13378,12 +13431,6 @@ typedef struct #define ETH_MACPHYCSR_LNKSTS_Pos (19U) #define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */ #define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */ -#define ETH_MACPHYCSR_JABTO_Pos (20U) -#define ETH_MACPHYCSR_JABTO_Msk (0x1UL << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */ -#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */ -#define ETH_MACPHYCSR_FALSCARDET_Pos (21U) -#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1UL << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */ -#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */ /*************** Bit definition for ETH_MACVR register ***************/ #define ETH_MACVR_SNPSVER_Pos (0U) @@ -14919,9 +14966,6 @@ typedef struct #define ETH_MACTSCR_TSENMACADDR_Pos (18U) #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */ #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */ -#define ETH_MACTSCR_CSC_Pos (19U) -#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */ -#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */ #define ETH_MACTSCR_TXTSSTSM_Pos (24U) #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */ #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */ @@ -14930,17 +14974,6 @@ typedef struct #define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */ /************** Bit definition for ETH_MACSSIR register **************/ -#define ETH_MACSSIR_SNSINC_Pos (8U) -#define ETH_MACSSIR_SNSINC_Msk (0xFFUL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */ -#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */ -#define ETH_MACSSIR_SNSINC_0 (0x1UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */ -#define ETH_MACSSIR_SNSINC_1 (0x2UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */ -#define ETH_MACSSIR_SNSINC_2 (0x4UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */ -#define ETH_MACSSIR_SNSINC_3 (0x8UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */ -#define ETH_MACSSIR_SNSINC_4 (0x10UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */ -#define ETH_MACSSIR_SNSINC_5 (0x20UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */ -#define ETH_MACSSIR_SNSINC_6 (0x40UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */ -#define ETH_MACSSIR_SNSINC_7 (0x80UL << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */ #define ETH_MACSSIR_SSINC_Pos (16U) #define ETH_MACSSIR_SSINC_Msk (0xFFUL << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */ #define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */ @@ -15860,9 +15893,14 @@ typedef struct #define ETH_MTLTXQ0OMR_TTC_Pos (4U) #define ETH_MTLTXQ0OMR_TTC_Msk (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */ -#define ETH_MTLTXQ0OMR_TTC_0 (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ -#define ETH_MTLTXQ0OMR_TTC_1 (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ -#define ETH_MTLTXQ0OMR_TTC_2 (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_32BITS (0x0UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLTXQ0OMR_TTC_64BITS (0x1UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */ +#define ETH_MTLTXQ0OMR_TTC_96BITS (0x2UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */ +#define ETH_MTLTXQ0OMR_TTC_128BITS (0x3UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000030 */ +#define ETH_MTLTXQ0OMR_TTC_192BITS (0x4UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */ +#define ETH_MTLTXQ0OMR_TTC_256BITS (0x5UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000050 */ +#define ETH_MTLTXQ0OMR_TTC_384BITS (0x6UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000060 */ +#define ETH_MTLTXQ0OMR_TTC_512BITS (0x7UL << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTXQ0OMR_TQS_Pos (16U) #define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFUL << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */ #define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */ @@ -15979,8 +16017,10 @@ typedef struct #define ETH_MTLRXQ0OMR_RTC_Pos (0U) #define ETH_MTLRXQ0OMR_RTC_Msk (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */ -#define ETH_MTLRXQ0OMR_RTC_0 (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ -#define ETH_MTLRXQ0OMR_RTC_1 (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_64BITS (0x0UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000000 */ +#define ETH_MTLRXQ0OMR_RTC_32BITS (0x1UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */ +#define ETH_MTLRXQ0OMR_RTC_96BITS (0x2UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */ +#define ETH_MTLRXQ0OMR_RTC_128BITS (0x3UL << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRXQ0OMR_FUP_Pos (3U) #define ETH_MTLRXQ0OMR_FUP_Msk (0x1UL << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */ #define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */ @@ -16482,15 +16522,12 @@ typedef struct #define ETH_DMAMR_TAA_0 (0x1UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */ #define ETH_DMAMR_TAA_1 (0x2UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */ #define ETH_DMAMR_TAA_2 (0x4UL << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */ +#define ETH_DMAMR_DSPW_Pos (8) +#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */ +#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /*!< Descriptor Posted Write */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */ -#define ETH_DMAMR_PR_Pos (12U) -#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ -#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */ -#define ETH_DMAMR_PR_0 (0x1UL << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */ -#define ETH_DMAMR_PR_1 (0x2UL << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */ -#define ETH_DMAMR_PR_2 (0x4UL << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */ #define ETH_DMAMR_INTM_Pos (16U) #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */ #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */ @@ -16693,10 +16730,10 @@ typedef struct #define ETH_DMAC0CR_DSL_Pos (18U) #define ETH_DMAC0CR_DSL_Msk (0x7UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT (0x0UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ -#define ETH_DMACCR_DSL_32BIT (0x1UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ -#define ETH_DMACCR_DSL_64BIT (0x2UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ -#define ETH_DMACCR_DSL_128BIT (0x4UL << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ +#define ETH_DMACCR_DSL_0BIT (0x0U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00000000 */ +#define ETH_DMACCR_DSL_64BIT (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */ +#define ETH_DMACCR_DSL_128BIT (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */ +#define ETH_DMACCR_DSL_256BIT (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */ /************* Bit definition for ETH_DMAC0TXCR register *************/ #define ETH_DMAC0TXCR_ST_Pos (0U) @@ -16714,6 +16751,9 @@ typedef struct #define ETH_DMAC0TXCR_TSE_Pos (12U) #define ETH_DMAC0TXCR_TSE_Msk (0x1UL << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */ +#define ETH_DMAC0TXCR_IPBL_Pos (15U) +#define ETH_DMAC0TXCR_IPBL_Msk (0x1UL << ETH_DMAC0TXCR_IPBL_Pos) /*!< 0x00008000 */ +#define ETH_DMAC0TXCR_IPBL ETH_DMAC0TXCR_IPBL_Msk /*!< Ignore PBL Requirement */ #define ETH_DMAC0TXCR_TXPBL_Pos (16U) #define ETH_DMAC0TXCR_TXPBL_Msk (0x3FUL << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */ @@ -17590,9 +17630,9 @@ typedef struct #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ -#define DMA_SxCR_ACK_Pos (20U) -#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ -#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk +#define DMA_SxCR_TRBUFF_Pos (20U) +#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk @@ -39334,8 +39374,8 @@ typedef struct /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) -/****************************** USB Instances ********************************/ -#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/****************************** USB PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) /****************************** WWDG Instances ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h index 44fffb9c7b..e66bcf3075 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h @@ -69,7 +69,7 @@ * @brief CMSIS Device version number */ #define __STM32MP1xx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32MP1xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ +#define __STM32MP1xx_CMSIS_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ #define __STM32MP1xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32MP1xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32MP1xx_CMSIS_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/LICENSE.txt b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/LICENSE.txt new file mode 100644 index 0000000000..93f94ed667 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the Apache-2.0 license shall apply. +You may obtain a copy of the Apache-2.0 at: +https://opensource.org/licenses/Apache-2.0 diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html index 972d4eeded..ca206fa50a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html @@ -5,57 +5,85 @@ Release Notes for STM32MP15xx CMSIS - + -
-

Release Notes for  STM32MP15xx CMSIS

+

Release Notes for + STM32MP15xx CMSIS

Copyright © 2021 STMicroelectronics

- +

Purpose

-

This driver provides the CMSIS device for the STM32MP15xx products. This covers

+

This driver provides the CMSIS device for the STM32MP15xx products. +This covers

-

This driver is composed of the descriptions of the registers under “Include” directory.

-

Various template file are provided to easily build an application. They can be adapted to fit applications requirements.

+

This driver is composed of the descriptions of the registers under +“Include” directory.

+

Various template file are provided to easily build an application. +They can be adapted to fit applications requirements.

-
-

Update History

+
+

Update History

- + +

Main Changes

-

This is a Maintenance release for STM32MP15xx CMSIS

+

This is a Maintenance release for STM32MP15xx +CMSIS

Contents

  • Update bit definition in header files:
      -
    • BSEC : Add missing registers
      • -
    • ETH : Update bitfield names
      • +
    • ADC : Add missing registers & Update bitfield names
      • +
    • DMA : Fix missing interrupts used in UART
      • +
    • +
  • Fixes in startup and linker files +
      +
    • Added default clock values in system files
      • +
    • Linker files aligned with GCC12
      • +
    • Fixed declaration of g_pfnVectors size in gcc/startup files
    • -
  • Update License declaration for startup and linker files
    • -
  • Change include in system file ( alignment with other STM32 families)

Known Limitations

None

@@ -64,42 +92,75 @@

Dependencies

- + +

Main Changes

-

This is a Maintenance release for STM32MP15xx CMSIS

+

This is a Maintenance release for STM32MP15xx +CMSIS

Contents

  • Update bit definition in header files:
      +
    • BSEC : Add missing registers
      • +
    • ETH : Update bitfield names
      • +
    • +
  • Update License declaration for startup and linker files
    • +
  • Change include in system file ( alignment with other STM32 +families)
    • +
+

Known Limitations

+

None

+

Dependencies

+

None

+
+
+
+ + +
+

Main Changes

+

This is a Maintenance release for STM32MP15xx +CMSIS

+

Contents

+
    +
  • Update bit definition in header files: +
    • DDR : Update DDR bit registers
    • USBPHYC: Update structure and add bitfields
    • Fix MISRA warnings:
      • Remove duplicate definitions
        • -
      • Use ‘UL’ postfix for _Msk definitions and memory/peripheral base addresses
        • +
      • Use ‘UL’ postfix for _Msk definitions and memory/peripheral base +addresses
      • Unexpected space in “startup_stm32mp151axx_cm4 .s”
    • Linker script :
      • Prevent text section to overide data ( resource table )
        • -
      • Suppress the check and add AT (ADDR (.bss)) to set the LMA to the VMA.
        • +
      • Suppress the check and add AT (ADDR (.bss)) to set the LMA to the +VMA.
    • Update the licenses declaration
-

Known Limitations

+

Known Limitations

None

-

Dependencies

+

Dependencies

None

- + +
-

Main Changes

-

This is a Maintenance release for STM32MP15xx CMSIS

-

Contents

+

Main Changes

+

This is a Maintenance release for STM32MP15xx +CMSIS

+

Contents

  • Header files:
      @@ -107,38 +168,45 @@

      Contents

    • Update RNG register structure
-

Known Limitations

+

Known Limitations

None

-

Dependencies

+

Dependencies

None

- + +
-

Main Changes

-

This is a Maintenance release for STM32MP15xx CMSIS

-

Contents

+

Main Changes

+

This is a Maintenance release for STM32MP15xx +CMSIS

+

Contents

  • Header files:
      -
    • Rename RCC bit definition to be more compliant with the name from RCC spec
      • +
    • Rename RCC bit definition to be more compliant with the name from +RCC spec
    • Update license with BSD 3-Clause template
    • Fix typo in MDMA register definition
-

Known Limitations

+

Known Limitations

None

-

Dependencies

+

Dependencies

None

- + +
-

Main Changes

-

This is a Maintenance release for STM32MP15xx CMSIS

-

Contents

+

Main Changes

+

This is a Maintenance release for STM32MP15xx +CMSIS

+

Contents

  • Header files:
      @@ -149,21 +217,25 @@

      Contents

  • Update Linker Template file for KEIL and IAR:
      -
    • Add OpenAMP region ( region present by default, to comment if needed )
      • +
    • Add OpenAMP region ( region present by default, to comment if needed +)
-

Known Limitations

+

Known Limitations

None

-

Dependencies

+

Dependencies

None

- + +
-

Main Changes

-

This is the First Maintenance release for STM32MP15xx CMSIS

-

Contents

+

Main Changes

+

This is the First Maintenance release for +STM32MP15xx CMSIS

+

Contents

  • Header files:
      @@ -171,7 +243,8 @@

      Contents

    • Update ETH bit definition
    • update EXTI_EXTICR bit definition
    • Update I2C bit definition
      • -
    • Update SPI bit definition (SPI_CR1_CRC33_17, SPI_RXCRC, SPI_IER, SPI_I2SCFGR)
      • +
    • Update SPI bit definition (SPI_CR1_CRC33_17, SPI_RXCRC, SPI_IER, +SPI_I2SCFGR)
    • TMPSENS IP renamed DTS
    • Update FDCAN TXBC bit definition
    • Update DAC_DHR8RD bit definition
      • @@ -184,31 +257,37 @@

      Contents

  • Update startup file for KEIL and IAR
-

Known Limitations

+

Known Limitations

None

-

Dependencies

+

Dependencies

None

- + +
-

Main Changes

-

This is the First Official release for STM32MP15xx CMSIS

-

Contents

+

Main Changes

+

This is the First Official release for STM32MP15xx +CMSIS

+

Contents

    -
  • First official release version of bits and registers definition aligned with STM32MP1 reference manual.
    • +
  • First official release version of bits and registers definition +aligned with STM32MP1 reference manual.
-

Known Limitations

+

Known Limitations

None

-

Dependencies

+

Dependencies

None

-
+
diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/linker/stm32mp15xx_m4.ld b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/linker/stm32mp15xx_m4.ld index f3841e592e..f082f56f5e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/linker/stm32mp15xx_m4.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/linker/stm32mp15xx_m4.ld @@ -87,13 +87,15 @@ SECTIONS . = ALIGN(4); } > m_text - .ARM.extab : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } > m_text - .ARM : { + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) @@ -101,7 +103,7 @@ SECTIONS . = ALIGN(4); } > m_text - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); @@ -110,7 +112,7 @@ SECTIONS . = ALIGN(4); } > m_text - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); @@ -120,7 +122,7 @@ SECTIONS . = ALIGN(4); } > m_text - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp151axx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp151axx_cm4.s index 29fbb40e4e..3f28cc6a96 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp151axx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp151axx_cm4.s @@ -126,7 +126,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -299,6 +298,8 @@ g_pfnVectors: .word RESERVED148_IRQHandler // Reserved .word WAKEUP_PIN_IRQHandler // Interrupt for all 6 wake-up pins + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp151cxx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp151cxx_cm4.s index f2e7f6838d..ef285fab07 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp151cxx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp151cxx_cm4.s @@ -126,7 +126,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -299,6 +298,8 @@ g_pfnVectors: .word RESERVED148_IRQHandler // Reserved .word WAKEUP_PIN_IRQHandler // Interrupt for all 6 wake-up pins + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp153axx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp153axx_cm4.s index 4db19f0a3b..8d425ef81e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp153axx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp153axx_cm4.s @@ -126,7 +126,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -299,6 +298,8 @@ g_pfnVectors: .word RESERVED148_IRQHandler // Reserved .word WAKEUP_PIN_IRQHandler // Interrupt for all 6 wake-up pins + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp153cxx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp153cxx_cm4.s index 767f10d60a..383865dd41 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp153cxx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp153cxx_cm4.s @@ -126,7 +126,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -299,6 +298,8 @@ g_pfnVectors: .word RESERVED148_IRQHandler // Reserved .word WAKEUP_PIN_IRQHandler // Interrupt for all 6 wake-up pins + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp157axx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp157axx_cm4.s index e4180ea243..237c08124a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp157axx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp157axx_cm4.s @@ -126,7 +126,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -299,6 +298,8 @@ g_pfnVectors: .word RESERVED148_IRQHandler // Reserved .word WAKEUP_PIN_IRQHandler // Interrupt for all 6 wake-up pins + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp157cxx_cm4.s b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp157cxx_cm4.s index b2622f7669..f9ca8460cd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp157cxx_cm4.s +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp157cxx_cm4.s @@ -126,7 +126,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -299,6 +298,8 @@ g_pfnVectors: .word RESERVED148_IRQHandler // Reserved .word WAKEUP_PIN_IRQHandler // Interrupt for all 6 wake-up pins + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp15xx.s b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp15xx.s index 96e9ce6548..132167db83 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp15xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp15xx.s @@ -126,7 +126,6 @@ Infinite_Loop: ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -299,6 +298,8 @@ g_pfnVectors: .word RESERVED148_IRQHandler // Reserved .word WAKEUP_PIN_IRQHandler // Interrupt for all 6 wake-up pins + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/system_stm32mp1xx.c b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/system_stm32mp1xx.c index d00a7ae855..82d4f2f589 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/system_stm32mp1xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/system_stm32mp1xx.c @@ -47,6 +47,29 @@ #include "stm32mp1xx.h" +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)24000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)64000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +#if !defined (CSI_VALUE) + #define CSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< Value of the Internal Low Speed oscillator in Hz*/ +#endif /* LSI_VALUE */ + +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz*/ +#endif /* LSE_VALUE */ + /** * @} */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index c2b839afcd..8639b87ff9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -15,7 +15,7 @@ * STM32L1: 2.3.3 * STM32L4: 1.7.4 * STM32L5: 1.0.6 - * STM32MP1: 1.6.0 + * STM32MP1: 1.7.0 * STM32U0: 1.2.0 * STM32U5: 1.4.1 * STM32WB: 1.12.2 diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 5362681f1f..a88ea16b92 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -37,16 +37,12 @@ extern "C" { #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR -#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) +#if defined(STM32H7) || defined(STM32MP1) #define CRYP_DATATYPE_32B CRYP_NO_SWAP #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP #define CRYP_DATATYPE_1B CRYP_BIT_SWAP -#if defined(STM32U5) -#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF -#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF -#endif /* STM32U5 */ -#endif /* STM32U5 || STM32H7 || STM32MP1 */ +#endif /* STM32H7 || STM32MP1 */ /** * @} */ @@ -112,6 +108,10 @@ extern "C" { #define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES #define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 #endif /* STM32U5 */ + +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ /** * @} */ @@ -139,7 +139,8 @@ extern "C" { #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 #if defined(STM32L0) -#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ #endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) @@ -213,6 +214,11 @@ extern "C" { #endif #endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + /** * @} */ @@ -233,9 +239,13 @@ extern "C" { /** @defgroup CRC_Aliases CRC API aliases * @{ */ -#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ -#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ - +#if defined(STM32H5) || defined(STM32C0) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ +#endif /** * @} */ @@ -277,7 +287,13 @@ extern "C" { #define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 #endif -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif @@ -342,7 +358,8 @@ extern "C" { #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING -#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI #endif @@ -455,7 +472,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) #define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -502,7 +521,7 @@ extern "C" { #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 -#if defined(STM32G0) +#if defined(STM32G0) || defined(STM32C0) #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH #else @@ -519,6 +538,10 @@ extern "C" { #define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ #if defined(STM32U5) #define OB_USER_nRST_STOP OB_USER_NRST_STOP #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY @@ -527,7 +550,20 @@ extern "C" { #define OB_USER_nBOOT0 OB_USER_NBOOT0 #define OB_nBOOT0_RESET OB_NBOOT0_RESET #define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE #endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ /** * @} @@ -571,6 +607,115 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ + + /** * @} */ @@ -638,14 +783,16 @@ extern "C" { #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS -#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ #endif /* STM32H7 */ #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH @@ -667,13 +814,28 @@ extern "C" { #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32H5) #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ -#endif /* STM32U5 */ +#endif /* STM32U5 || STM32H5 */ #if defined(STM32U5) #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ /** * @} */ @@ -683,7 +845,25 @@ extern "C" { */ #if defined(STM32U5) #define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB #endif /* STM32U5 */ +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ /** * @} */ @@ -710,6 +890,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -847,8 +1031,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -864,7 +1048,8 @@ extern "C" { #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX @@ -1002,7 +1187,7 @@ extern "C" { #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 -#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif @@ -1098,22 +1283,42 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32F7) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 || STM32H7RS || STM32N6 */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +#if defined(STM32F7) || defined(STM32WB) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK -#endif /* STM32F7 */ +#endif /* STM32F7 || STM32WB */ #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #endif /* STM32H7 */ -#if defined(STM32F7) || defined(STM32H7) +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP -#endif /* STM32F7 || STM32H7 */ +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ /** * @} @@ -1393,30 +1598,40 @@ extern "C" { #define ETH_MMCRFAECR 0x00000198U #define ETH_MMCRGUFCR 0x000001C4U -#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ #if defined(STM32F1) #else #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ #endif -#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ @@ -1424,6 +1639,8 @@ extern "C" { #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ + /** * @} */ @@ -1587,7 +1804,8 @@ extern "C" { #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ - )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) @@ -1596,8 +1814,10 @@ extern "C" { #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ - )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) -#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode @@ -1631,16 +1851,21 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ - )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA @@ -1765,6 +1990,17 @@ extern "C" { #define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP #define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + #define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP #define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP #define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP @@ -1773,6 +2009,8 @@ extern "C" { #define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP #define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP #define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + #define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY #define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY @@ -1783,6 +2021,7 @@ extern "C" { #define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN #define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN #define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK #endif @@ -1791,6 +2030,20 @@ extern "C" { * @} */ +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +/** + * @} + */ + /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ @@ -1816,7 +2069,8 @@ extern "C" { #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback @@ -2073,7 +2327,8 @@ extern "C" { #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK -#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) @@ -2098,8 +2353,8 @@ extern "C" { #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -2132,8 +2387,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ @@ -2190,8 +2445,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ @@ -2208,7 +2463,7 @@ extern "C" { __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif +#endif #else #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) @@ -2245,8 +2500,10 @@ extern "C" { /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose * @{ */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ /** * @} */ @@ -2405,7 +2662,9 @@ extern "C" { #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE @@ -2414,8 +2673,12 @@ extern "C" { #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) -#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 @@ -2451,8 +2714,8 @@ extern "C" { #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ - )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE @@ -2502,6 +2765,12 @@ extern "C" { #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET @@ -2956,6 +3225,11 @@ extern "C" { #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 #endif #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE @@ -3420,7 +3694,16 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + +#if defined(STM32GK) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_DISABLE +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_DISABLE +#elif defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ + defined(STM32WL) || defined(STM32C0) || defined(STM32V7) || defined(STM32N6) || defined(STM32H7RS) || \ + defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3522,8 +3805,10 @@ extern "C" { #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 @@ -3565,6 +3850,92 @@ extern "C" { #define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE #endif /* STM32U5 */ +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ + /** * @} */ @@ -3581,8 +3952,11 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \ - defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32GK) || defined (STM32WB_GEN2) || defined (STM32WBA) || defined (STM32V7) || defined (STM32H5) || \ + defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) || \ + defined (STM32V8) || defined (STM32C1) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3617,6 +3991,13 @@ extern "C" { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + #define IS_ALARM IS_RTC_ALARM #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER @@ -3635,6 +4016,11 @@ extern "C" { #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ + /** * @} */ @@ -3864,6 +4250,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ @@ -3893,6 +4306,9 @@ extern "C" { #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 /** * @} */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal.h index 9d51f75788..04041b38db 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal.h @@ -145,10 +145,10 @@ typedef enum (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1)) -#define SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCSETR_ANA0_SEL_SEL /*!< PA0 analog switch opened */ -#define SYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000) /*!< PA0 analog switch closed */ -#define SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCSETR_ANA1_SEL_SEL /*!< PA1 analog switch opened */ -#define SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000) /*!< PA1 analog switch closed*/ +#define SYSCFG_SWITCH_PA0_OPEN ((uint32_t)0x00000000) /*!< PA0 analog switch opened */ +#define SYSCFG_SWITCH_PA0_CLOSE SYSCFG_PMCSETR_ANA0_SEL_SEL /*!< PA0 analog switch closed */ +#define SYSCFG_SWITCH_PA1_OPEN ((uint32_t)0x00000000) /*!< PA1 analog switch opened */ +#define SYSCFG_SWITCH_PA1_CLOSE SYSCFG_PMCSETR_ANA1_SEL_SEL /*!< PA1 analog switch closed */ #define IS_SYSCFG_SWITCH_STATE(STATE) ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN) || \ (((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE) || \ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h index b0664a66c6..3adf305269 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h @@ -682,7 +682,7 @@ typedef struct #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \ ADC_CCR_PRESC | \ ADC_CCR_VBATEN | \ - ADC_CCR_VSENSEEN | \ + ADC_CCR_TSEN | \ ADC_CCR_VREFEN | \ ADC_CCR_DAMDF | \ ADC_CCR_DELAY | \ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_def.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_def.h index ef51f32906..984579d16a 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_def.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_def.h @@ -30,7 +30,7 @@ #if defined(USE_HAL_LEGACY) #include "Legacy/stm32_hal_legacy.h" #endif -#include +#include /* Exported types ------------------------------------------------------------*/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_i2c.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_i2c.h index 93eb83dd23..f3e922041d 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_i2c.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_i2c.h @@ -223,6 +223,10 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim.h index aaa718dea9..3c2bf168c6 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim.h @@ -1913,6 +1913,8 @@ mode. ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) @@ -2117,10 +2119,16 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, + uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, + uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h index 9f0893b2c2..637133820b 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h @@ -706,7 +706,7 @@ typedef struct /* only by selecting the corresponding ADC internal channel. */ #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */ #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ -#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSEEN) /*!< ADC measurement path to internal channel temperature sensor */ +#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */ #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */ #define LL_ADC_PATH_INTERNAL_VDDCORE (ADC2_OR_VDDCOREEN) /*!< ADC measurement path to internal channel Vddcore */ /** @@ -2390,7 +2390,7 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_CO } else { - MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN, PathInternal); + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); } } @@ -2506,7 +2506,7 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) { - return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN)); + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); } /** @@ -5109,7 +5109,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL) + (AWDThresholdsHighLow)); - MODIFY_REG(*preg, ADC_LTR1_LT1, AWDThresholdValue); + MODIFY_REG(*preg, ADC_LTR1_LTR1, AWDThresholdValue); } /** @@ -5141,7 +5141,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_ + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL) + (AWDThresholdsHighLow)); - return (uint32_t)(READ_BIT(*preg, ADC_LTR1_LT1)); + return (uint32_t)(READ_BIT(*preg, ADC_LTR1_LTR1)); } /** @@ -5284,7 +5284,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift) { - MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OSR_Pos)))); + MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OSVR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OSVR_Pos)))); } /** @@ -5296,7 +5296,7 @@ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) { - return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OSR))+(1UL << ADC_CFGR2_OSR_Pos)) >> ADC_CFGR2_OSR_Pos); + return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OSVR))+(1UL << ADC_CFGR2_OSVR_Pos)) >> ADC_CFGR2_OSVR_Pos); } /** diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/LICENSE.txt b/system/Drivers/STM32MP1xx_HAL_Driver/LICENSE.txt new file mode 100644 index 0000000000..1cbbc544a3 --- /dev/null +++ b/system/Drivers/STM32MP1xx_HAL_Driver/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the BSD-3-Clause license shall apply. +You may obtain a copy of the BSD-3-Clause at: +https://opensource.org/licenses/BSD-3-Clause diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32MP1xx_HAL_Driver/Release_Notes.html index 30af4e68b1..14ff1679c6 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Release_Notes.html @@ -5,50 +5,143 @@ Release Notes for STM32CubeMP1xx HAL and LL drivers - + -
-

Release Notes for STM32CubeMP1xx HAL and LL drivers

+

Release +Notes for STM32CubeMP1xx HAL and LL drivers

Copyright ©  2021 STMicroelectronics

- +

Purpose

-

The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.

-

The portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.

-

The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provides a basic set of optimized and one-shot services. The Low layer drivers, contrary to the HAL ones are not fully portable across the STM32 families; the availability of some functions depends on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:

-
    -
  • New set of inline functions for direct and atomic register access
    • -
  • One-shot operations that can be used by the HAL drivers or from application level
    • -
  • Full independence from HAL and standalone usage (without HAL drivers)
    • +

    The STM32Cube HAL and LL, an STM32 abstraction layer embedded +software, ensure maximized portability across STM32 portfolio.

    +

    The portable APIs layer provides a generic, multi instanced and +simple set of APIs to interact with the upper layer (application, +libraries and stacks). It is composed of native and extended APIs set. +It is directly built around a generic architecture and allows the +build-upon layers, like the middleware layer, to implement its functions +without knowing in-depth the used STM32 device. This improves the +library code reusability and guarantees an easy portability on other +devices and STM32 families.

    +

    The Low Layer (LL) drivers are part of the STM32Cube firmware HAL +that provides a basic set of optimized and one-shot services. The Low +layer drivers, contrary to the HAL ones are not fully portable across +the STM32 families; the availability of some functions depends on the +physical availability of the relative features on the product. The Low +Layer (LL) drivers are designed to offer the following features:

    +
      +
    • New set of inline functions for direct and atomic register +access
      • +
    • One-shot operations that can be used by the HAL drivers or from +application level
      • +
    • Full independence from HAL and standalone usage (without HAL +drivers)
    • Full features coverage of all the supported peripherals
-
-

Update History

+
+

Update History

- + +

Main Changes

    -
  • Maintenance release of HAL and LL drivers for STM32MP15xx devices
    • +
  • Maintenance release of HAL and LL drivers for +STM32MP15xx devices

Contents

    -
  • General updates to fix known defects and enhancements implementation
    • +
  • General updates to fix known defects and enhancements +implementation
    • +
  • Major update of drivers for STM32MP15xx devices: +
      +
    • HAL: +
        +
      • Fixed wrong definition of SYSCFG ANA0/ANA1 PA0/PA1 switches +open/close.
        • +
      • Add interrupt enable line of TIM6_handle
        • +
      • Fixed SysTick has a wrong behaviour when STGEN is switched to +HSE
        • +
      • +
    • ADC (No API change) +
        +
      • Rename ADC register bits. - OSR TO OSVR - LT1,LT2,LT3 TO +LTR1,LTR2,LTR3 - HT1,HT2,HT3 TO HTR1,HTR2,HTR3 - VSENSEEN TO TSEN
        • +
      • +
    • DMA +
        +
      • Added STM32MP1 UART + DMA missing interrupts (No API Change)
        • +
      • +
    • I2C +
        +
      • Fixed I2C_WaitOnTXISFlagUntilTimeout() busy wait (No API +Change)
        • +
      • +
    • TIM +
        +
      • TIM : add new function HAL_TIM_DMABurst_MultiWrite/ReadStart
        • +
      • LL : Fix counter mode tests
        • +
      • +
    • +
+

Known Limitations

+
    +
  • N/A
    • +
+

Supported Devices

+
    +
  • The drivers provided support the following devices : +
      +
    • STM32MP157Cxx, STM32MP157Axx, STM32MP157Dxx, STM32MP157Fxx
      • +
    • STM32MP153Cxx, STM32MP153Axx, STM32MP153Dxx, STM32MP153Fxx
      • +
    • STM32MP151Cxx, STM32MP151Axx, STM32MP151Dxx, STM32MP151Fxx
      • +
    • +
+
+
+
+ + +
+

Main Changes

+
    +
  • Maintenance release of HAL and LL drivers for +STM32MP15xx devices
    • +
+

Contents

+
    +
  • General updates to fix known defects and enhancements +implementation
  • Major update of drivers for STM32MP15xx devices:
    • HAL: @@ -93,15 +186,16 @@

      Contents

    • RCC (No API change)
      • (HAL) : Fix pllxvco calculation
        • -
      • (LL) : Fix compilation issue ( some missing register alignement with CMSIS Device)
        • +
      • (LL) : Fix compilation issue ( some missing register alignement with +CMSIS Device)
-

Known Limitations

+

Known Limitations

  • N/A
-

Supported Devices

+

Supported Devices

  • The drivers provided support the following devices :
      @@ -113,13 +207,17 @@

      Supported Devices

- + +
-

Main Changes

-

Maintenance release of HAL and LL drivers for STM32MP15xx devices

-

Contents

+

Main Changes

+

Maintenance release of HAL and LL drivers for +STM32MP15xx devices

+

Contents

    -
  • General updates to fix known defects and enhancements implementation
    • +
  • General updates to fix known defects and enhancements +implementation
  • Major update of drivers for STM32MP15xx devices:
    • All HAL and LL Drivers @@ -151,11 +249,11 @@

      Contents

-

Known Limitations

+

Known Limitations

  • None
-

Supported Devices

+

Supported Devices

  • The drivers provided support the following devices :
      @@ -167,13 +265,17 @@

      Supported Devices

- + +
-

Main Changes

-

Maintenance release of HAL and LL drivers for STM32MP15xx devices

-

Contents

+

Main Changes

+

Maintenance release of HAL and LL drivers for +STM32MP15xx devices

+

Contents

    -
  • General updates to fix known defects and enhancements implementation
    • +
  • General updates to fix known defects and enhancements +implementation
  • Major update of drivers for STM32MP15xx devices:
    • DTS (TMPSENS) @@ -182,17 +284,20 @@

      Contents

  • EXTI
      -
    • Remove management of C1EMRx registers which does not exist on the silicon
      • +
    • Remove management of C1EMRx registers which does not exist on the +silicon
    • Fix typo issue with EXTI_LINE_20
  • GENERIC
    • Fix issue on the HAL_SYSCFG_DisableIOCompensation function
      • -
    • Replace SET_BIT usage in some condition (set/clear register pairs)
      • +
    • Replace SET_BIT usage in some condition (set/clear register +pairs)
  • RCC
      -
    • LL - Fix compilation issue ( Align CMSIS Device and LL definitions removing LL_APB3_GRP1_PERIPH_PMBCTRL and LL_AHB5_GRP1_PERIPH_AXIMC)
      • +
    • LL - Fix compilation issue ( Align CMSIS Device and LL definitions +removing LL_APB3_GRP1_PERIPH_PMBCTRL and LL_AHB5_GRP1_PERIPH_AXIMC)
  • SMARTCARD:
      @@ -204,7 +309,7 @@

      Contents

-

Known Limitations

+

Known Limitations

  • None
@@ -212,7 +317,7 @@

Dependencies

  • None
-

Supported Devices

+

Supported Devices

  • The drivers provided support the following devices :
      @@ -224,20 +329,26 @@

      Supported Devices

- + +
-

Main Changes

-

Maintenance release of HAL and LL drivers for STM32MP15xx devices

-

Contents

+

Main Changes

+

Maintenance release of HAL and LL drivers for +STM32MP15xx devices

+

Contents

    -
  • General updates to fix known defects and enhancements implementation
    • +
  • General updates to fix known defects and enhancements +implementation
  • Major update of drivers for STM32MP15xx devices:
    • ADC: No API change
      • Typo corrections in HAL & LL drivers
        • -
      • LL - assert_param should check constraint between modes continuous and discontinuous
        • -
      • HAL - Fix IRQ handler in case of injected conversion + IT mode + trigger timer
        • +
      • LL - assert_param should check constraint between modes continuous +and discontinuous
        • +
      • HAL - Fix IRQ handler in case of injected conversion + IT mode + +trigger timer
    • DFSDM: No API change
        @@ -250,12 +361,15 @@

        Contents

    • GENERIC: No API change
        -
      • HAL configuration file : add SMARTCARD and SRAM in template file
        • +
      • HAL configuration file : add SMARTCARD and SRAM in template +file
    • RCC: No API change
        -
      • Important define update to be compliant with Header file update ( CMSIS device)
        • -
      • Fix compilation issue ( to be compliant with Header file update on CMSIS device)
        • +
      • Important define update to be compliant with Header file update ( +CMSIS device)
        • +
      • Fix compilation issue ( to be compliant with Header file update on +CMSIS device)
    • SAI
        @@ -266,16 +380,18 @@

        Contents

    • SDMMC: No API change
        -
      • HAL - Fix loop increment in SD_HighSpeed and SD_UltraHighSpeed function
        • +
      • HAL - Fix loop increment in SD_HighSpeed and SD_UltraHighSpeed +function
    • SMARTCARD
      • HAL: Implement SMARTCARD Driver: New API
        • -
      • HAL - rename UART_FIFOMODE_ENABLE into SMARTCARD_FIFOMODE_ENABLE
        • +
      • HAL - rename UART_FIFOMODE_ENABLE into +SMARTCARD_FIFOMODE_ENABLE
-

Known Limitations

+

Known Limitations

  • None
@@ -283,7 +399,7 @@

Dependencies

  • None
-

Supported Devices

+

Supported Devices

  • The drivers provided support the following devices :
      @@ -295,13 +411,17 @@

      Supported Devices

- + +
-

Main Changes

-

Maintenance release of HAL and LL drivers for STM32MP15xx devices

-

Contents

+

Main Changes

+

Maintenance release of HAL and LL drivers for +STM32MP15xx devices

+

Contents

    -
  • General updates to fix known defects and enhancements implementation
    • +
  • General updates to fix known defects and enhancements +implementation
  • Major update of drivers for STM32MP15xx devices:
    • ADC @@ -309,7 +429,8 @@

      Contents

    • Update HAL_ADC_Start_DMA() API to enable DMA mode
    • LL : new function to add or remove paths.
        -
      • LL_ADC_SetCommonPathInternalChAdd and LL_ADC_SetCommonPathInternalChAdd : New API
        • +
      • LL_ADC_SetCommonPathInternalChAdd and +LL_ADC_SetCommonPathInternalChAdd : New API
  • CORTEX @@ -326,7 +447,8 @@

    Contents

  • RTC
      -
    • HAL&LL : Implement RTC Driver (including TAMP) : New API
      • +
    • HAL&LL : Implement RTC Driver (including TAMP) : New +API
  • TIM
      @@ -339,18 +461,20 @@

      Contents

  • UART
      -
    • HAL: Alignment with STM32F0/F3/H7 (for inter STM32 families portability) +
    • HAL: Alignment with STM32F0/F3/H7 (for inter STM32 families +portability)
      • some API’s change to take in consideration
  • UTILS
      -
    • LL: Add new Part Number defines related to LL_GetDevicePartNumber()consideration
      • +
    • LL: Add new Part Number defines related to +LL_GetDevicePartNumber()consideration
    • -

    Known Limitations

    +

    Known Limitations

    • None
    @@ -358,7 +482,7 @@

    Dependencies

    • None
    -

    Supported Devices

    +

    Supported Devices

    • The drivers provided support the following devices :
        @@ -370,13 +494,17 @@

        Supported Devices

    - + +
    -

    Main Changes

    -

    First Maintenance release of HAL and LL drivers for STM32MP15xx devices

    -

    Contents

    +

    Main Changes

    +

    First Maintenance release of HAL and LL drivers for +STM32MP15xx devices

    +

    Contents

      -
    • General updates to fix known defects and enhancements implementation
      • +
    • General updates to fix known defects and enhancements +implementation
    • Implementation of LL APIs:
      • DMA / EXTI / HSEM / LPTIM / PWR / SPI / TIM / WWDG / I2C
        • @@ -391,17 +519,22 @@

        Contents

        • HAL: Remove ADC_TWOSAMPLINGDELAY_9CYCLES definition
        • HAL: Remove ADC_OVERSAMPLING_RATIO_xxx defnitions
          • -
        • LL : Add ADC Internal Channel VDDCORE management ( LL_ADC_PATH_INTERNAL_VDDCORE)
          • -
        • HAL & LL: Update for linear calibration and Use ‘ADC_LINEAR_CALIB_REG_COUNT’
          • +
        • LL : Add ADC Internal Channel VDDCORE management ( +LL_ADC_PATH_INTERNAL_VDDCORE)
          • +
        • HAL & LL: Update for linear calibration and Use +‘ADC_LINEAR_CALIB_REG_COUNT’
      • DMA
          -
        • HAL: Use DMA_Stream_TypeDef structure for instance (structure change)
          • +
        • HAL: Use DMA_Stream_TypeDef structure for instance +(structure change)
      • Generic
          -
        • HAL: Update the SystemCoreClock global variable ( needed in case of Coprocesseur use case)
          • -
        • HAL: Add enable/disable functions for IO Compensation mechanism (new API)
          • +
        • HAL: Update the SystemCoreClock global variable ( needed in case of +Coprocesseur use case)
          • +
        • HAL: Add enable/disable functions for IO Compensation mechanism +(new API)
        • HAL: Align HAL_CONF template with HAL package
      • GPIO @@ -412,11 +545,14 @@

        Contents

    • IPCC
        -
      • LL: Add service to get the number of supported channels (new API)
        • +
      • LL: Add service to get the number of supported channels (new +API)
    • LPTIM
        -
      • HAL: Alignment with STM32H7/WB (for inter STM32 families portability): some API’s change to take in consideration
        • +
      • HAL: Alignment with STM32H7/WB (for inter STM32 families +portability): some API’s change to take in +consideration
    • RCC
        @@ -425,15 +561,18 @@

        Contents

    • SPI
        -
      • HAL: Add new feature Reload Feature + Duplex Packet DXP (new API)
        • +
      • HAL: Add new feature Reload Feature + Duplex Packet DXP (new +API)
    • TIM
        -
      • HAL: Alignment with STM32F0/F3/H7/WB (for inter STM32 families portability): some API’s change to take in consideration
        • +
      • HAL: Alignment with STM32F0/F3/H7/WB (for inter STM32 families +portability): some API’s change to take in +consideration
    -

    Known Limitations

    +

    Known Limitations

    • None
    @@ -444,11 +583,14 @@

    Dependencies

    - + +
    -

    Main Changes

    -

    First official release of HAL and LL drivers for STM32MP15xx devices

    -

    Known Limitations

    +

    Main Changes

    +

    First official release of HAL and LL drivers for +STM32MP15xx devices

    +

    Known Limitations

    • None
    @@ -458,11 +600,16 @@

    Dependencies

    -
    +
    -

    For complete documentation on STM32 Microcontrollers , visit: www.st.com/stm32

    -This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge. +

    For complete documentation on STM32 Microcontrollers , visit: +www.st.com/stm32

    +This release note uses up to date web standards and, for this reason, +should not be opened with Internet Explorer but preferably with popular +browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft +Edge.
    diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c index 3f08bfdffd..f9be5f6e54 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c @@ -54,7 +54,7 @@ * @brief STM32MP1xx HAL Driver version number */ #define __STM32MP1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32MP1xx_HAL_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ +#define __STM32MP1xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ #define __STM32MP1xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32MP1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32MP1xx_HAL_VERSION ((__STM32MP1xx_HAL_VERSION_MAIN << 24)\ @@ -367,7 +367,14 @@ __weak uint32_t HAL_GetTick(void) return uwTick; #else /* tick value directly got from 64bits CA7 register*/ - return ( PL1_GetCurrentPhysicalValue() / (HSI_VALUE/1000)); + if ((RCC->STGENCKSELR & RCC_STGENCKSELR_STGENSRC) == RCC_STGENCLKSOURCE_HSE) + { + return ((uint32_t)PL1_GetCurrentPhysicalValue() / (HSE_VALUE / 1000UL)); + } + else + { + return ((uint32_t)PL1_GetCurrentPhysicalValue() / (HSI_VALUE / 1000UL)); + } #endif #endif /* CORE_CA7 */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c index 64551cc7b1..9dec6ee1bb 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c @@ -315,7 +315,7 @@ ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */ -#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OSR |\ +#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OSVR |\ ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\ ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion (neither regular nor injected) is on-going */ @@ -626,7 +626,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* - Oversampling mode (continued/resumed) */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS, ADC_CFGR2_ROVSE | - ((hadc->Init.Oversampling.Ratio - 1UL) << ADC_CFGR2_OSR_Pos) | + ((hadc->Init.Oversampling.Ratio - 1UL) << ADC_CFGR2_OSVR_Pos) | hadc->Init.Oversampling.RightBitShift | hadc->Init.Oversampling.TriggeredMode | hadc->Init.Oversampling.OversamplingStopReset); @@ -778,7 +778,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) /* Reset register CFGR2 */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | - ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE); + ADC_CFGR2_OSVR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE); /* Reset register SMPR1 */ CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS); @@ -789,16 +789,16 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10); /* Reset register LTR1 and HTR1 */ - CLEAR_BIT(hadc->Instance->LTR1, ADC_LTR1_LT1); - CLEAR_BIT(hadc->Instance->HTR1, ADC_HTR1_HT1); + CLEAR_BIT(hadc->Instance->LTR1, ADC_LTR1_LTR1); + CLEAR_BIT(hadc->Instance->HTR1, ADC_HTR1_HTR1); /* Reset register LTR2 and HTR2*/ - CLEAR_BIT(hadc->Instance->LTR2, ADC_LTR2_LT2); - CLEAR_BIT(hadc->Instance->HTR2, ADC_HTR2_HT2); + CLEAR_BIT(hadc->Instance->LTR2, ADC_LTR2_LTR2); + CLEAR_BIT(hadc->Instance->HTR2, ADC_HTR2_HTR2); /* Reset register LTR3 and HTR3 */ - CLEAR_BIT(hadc->Instance->LTR3, ADC_LTR2_LT2); - CLEAR_BIT(hadc->Instance->HTR3, ADC_HTR2_HT2); + CLEAR_BIT(hadc->Instance->LTR3, ADC_LTR2_LTR2); + CLEAR_BIT(hadc->Instance->HTR3, ADC_HTR2_HTR2); /* Reset register SQR1 */ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | @@ -3028,8 +3028,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold); /* Set the high and low thresholds */ - MODIFY_REG(hadc->Instance->LTR1, ADC_LTR1_LT1 , tmp_awd_low_threshold_shifted); - MODIFY_REG(hadc->Instance->HTR1, ADC_HTR1_HT1 , tmp_awd_high_threshold_shifted); + MODIFY_REG(hadc->Instance->LTR1, ADC_LTR1_LTR1 , tmp_awd_low_threshold_shifted); + MODIFY_REG(hadc->Instance->HTR1, ADC_HTR1_HTR1 , tmp_awd_high_threshold_shifted); /* Update state, clear previous result related to AWD1 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1); @@ -3098,14 +3098,14 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { /* Set ADC analog watchdog thresholds value of both thresholds high and low */ - MODIFY_REG(hadc->Instance->LTR2, ADC_LTR2_LT2 , tmp_awd_low_threshold_shifted); - MODIFY_REG(hadc->Instance->HTR2, ADC_HTR2_HT2 , tmp_awd_high_threshold_shifted); + MODIFY_REG(hadc->Instance->LTR2, ADC_LTR2_LTR2 , tmp_awd_low_threshold_shifted); + MODIFY_REG(hadc->Instance->HTR2, ADC_HTR2_HTR2 , tmp_awd_high_threshold_shifted); } else { /* Set ADC analog watchdog thresholds value of both thresholds high and low */ - MODIFY_REG(hadc->Instance->LTR3, ADC_LTR3_LT3 , tmp_awd_low_threshold_shifted); - MODIFY_REG(hadc->Instance->HTR3, ADC_HTR3_HT3 , tmp_awd_high_threshold_shifted); + MODIFY_REG(hadc->Instance->LTR3, ADC_LTR3_LTR3 , tmp_awd_low_threshold_shifted); + MODIFY_REG(hadc->Instance->HTR3, ADC_HTR3_HTR3 , tmp_awd_high_threshold_shifted); } if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c index 6067a0fed9..b1ce280f69 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c @@ -2006,10 +2006,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* Enable OverSampling mode */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE | - ADC_CFGR2_OVSR | + ADC_CFGR2_OSVR | ADC_CFGR2_OVSS, ADC_CFGR2_JOVSE | - ((pConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OSR_Pos) | + ((pConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OSVR_Pos) | pConfigInjected->InjecOversampling.RightBitShift ); } diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma.c index 677c3af789..48556b0f65 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma.c @@ -121,7 +121,10 @@ typedef struct */ #define HAL_TIMEOUT_DMA_ABORT (5U) /* 5 ms */ - +#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART2_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \ + (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX ))) /** * @} */ @@ -256,6 +259,12 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; } + /* enable bufferable transfers if the DMA request is for UART/USART */ + if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) + { + registerValue |= DMA_SxCR_TRBUFF; + } + /* Write to DMA Stream CR register */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_i2c.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_i2c.c index d7d7d07a87..c5018707d5 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_i2c.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_i2c.c @@ -455,10 +455,14 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t /* Private functions for I2C transfer IRQ handler */ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); @@ -2732,9 +2736,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; - /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2754,9 +2755,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2765,30 +2763,29 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; - if (hi2c->XferCount > MAX_NBYTE_SIZE) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ else { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) - != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2826,9 +2823,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; - /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2848,9 +2842,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2859,29 +2850,29 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; - if (hi2c->XferCount > MAX_NBYTE_SIZE) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ else { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2894,7 +2885,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT)); return HAL_OK; } @@ -2918,8 +2909,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -2941,9 +2930,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2952,28 +2938,36 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; } - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) - != HAL_OK) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } if (hi2c->hdmatx != NULL) { @@ -3025,12 +3019,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd if (dmaxferstatus == HAL_OK) { - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3038,11 +3028,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } else { @@ -3082,8 +3072,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -3105,9 +3093,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -3116,25 +3101,35 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; } - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); } if (hi2c->hdmarx != NULL) @@ -3187,11 +3182,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr if (dmaxferstatus == HAL_OK) { - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3199,11 +3191,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } else { @@ -3446,6 +3438,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; @@ -5183,6 +5179,143 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin return HAL_OK; } +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + if (hi2c->Memaddress == 0xFFFFFFFFU) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -5464,6 +5597,145 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui return HAL_OK; } +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Enable only Error interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->XferCount != 0U) + { + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -7382,6 +7654,12 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr.c index 57cfb72b93..3654439746 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr.c @@ -621,7 +621,7 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) #endif /*CORE_CA7*/ /* Select Stop mode entry --------------------------------------------------*/ - if ((STOPEntry == PWR_STOPENTRY_WFI)) + if (STOPEntry == PWR_STOPENTRY_WFI) { /* Request Wait For Interrupt */ __WFI(); diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c index 627acc6098..df462bde22 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c @@ -3901,11 +3901,70 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + return status; +} +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); if (htim->State == HAL_TIM_STATE_BUSY) { @@ -3938,8 +3997,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -3955,8 +4015,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -3972,8 +4033,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -3989,8 +4051,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4006,8 +4069,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4023,8 +4087,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4040,25 +4105,31 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; } default: + status = HAL_ERROR; break; } - /* configure the DMA Burst Mode */ + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ htim->Instance->DCR = (BurstBaseAddress | BurstLength); /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); htim->State = HAL_TIM_STATE_READY; + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -4172,11 +4243,72 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); if (htim->State == HAL_TIM_STATE_BUSY) { @@ -4209,8 +4341,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4225,8 +4358,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4241,8 +4375,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4257,8 +4392,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4273,8 +4409,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4289,8 +4426,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4305,26 +4443,31 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; } default: + status = HAL_ERROR; break; } - /* configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - htim->State = HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; + } /* Return function status */ - return HAL_OK; + return status; } /** diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_timebase_tim_template.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_timebase_tim_template.c index 5b8591a2ef..5276c66c31 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_timebase_tim_template.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_timebase_tim_template.c @@ -57,12 +57,7 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) uint32_t uwPrescalerValue = 0U; uint32_t pFLatency; - /*Configure the TIM6 IRQ priority */ - HAL_NVIC_SetPriority(TIM6_IRQn, TickPriority ,0U); - - /* Enable the TIM6 global Interrupt */ - HAL_NVIC_EnableIRQ(TIM6_IRQn); - + /* Enable TIM6 clock */ __HAL_RCC_TIM6_CLK_ENABLE(); @@ -90,6 +85,12 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; if(HAL_TIM_Base_Init(&TimHandle) == HAL_OK) { + /*Configure the TIM6 IRQ priority */ + HAL_NVIC_SetPriority(TIM6_IRQn, TickPriority ,0U); + + /* Enable the TIM6 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM6_IRQn); + /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&TimHandle); } diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_adc.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_adc.c index cdab6d37a5..e81494ee2f 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_adc.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_adc.c @@ -610,7 +610,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Reset register CFGR2 */ CLEAR_BIT(ADCx->CFGR2, - ( ADC_CFGR2_LSHIFT | ADC_CFGR2_OVSR | ADC_CFGR2_RSHIFT1 + ( ADC_CFGR2_LSHIFT | ADC_CFGR2_OSVR | ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT4 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT1 | ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) @@ -632,13 +632,13 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) ); /* Reset register TR1 */ - CLEAR_BIT(ADCx->LTR1, ADC_LTR1_LT1); - SET_BIT(ADCx->HTR1, ADC_HTR1_HT1); + CLEAR_BIT(ADCx->LTR1, ADC_LTR1_LTR1); + SET_BIT(ADCx->HTR1, ADC_HTR1_HTR1); - CLEAR_BIT(ADCx->LTR2, ADC_LTR2_LT2); - SET_BIT(ADCx->HTR2, ADC_HTR2_HT2); - CLEAR_BIT(ADCx->LTR3, ADC_LTR3_LT3); - SET_BIT(ADCx->HTR3, ADC_HTR3_HT3); + CLEAR_BIT(ADCx->LTR2, ADC_LTR2_LTR2); + SET_BIT(ADCx->HTR2, ADC_HTR2_HTR2); + CLEAR_BIT(ADCx->LTR3, ADC_LTR3_LTR3); + SET_BIT(ADCx->HTR3, ADC_HTR3_HTR3); /* Reset register SQR1 */ CLEAR_BIT(ADCx->SQR1, diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 463f68e0c2..fee8a5af5e 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -15,7 +15,7 @@ * STM32L1: 1.4.5 * STM32L4: 1.13.5 * STM32L5: 1.0.6 - * STM32MP1: 1.6.0 + * STM32MP1: 1.7.0 * STM32U0: 1.2.0 * STM32U5: 1.6.1 * STM32WB: 1.14.4 diff --git a/system/Middlewares/OpenAMP/libmetal/lib/atomic.h b/system/Middlewares/OpenAMP/libmetal/lib/atomic.h index 44d6b9aaea..f279af0cb8 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/atomic.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/atomic.h @@ -94,7 +94,7 @@ using std::atomic_fetch_and_explicit; using std::atomic_thread_fence; using std::atomic_signal_fence; -#elif defined(HAVE_STDATOMIC_H) && !defined(__CC_ARM) && \ +#elif defined(HAVE_STDATOMIC_H) && !defined(__ARMCC_VERSION) && \ !defined(__STDC_NO_ATOMICS__) # include # include diff --git a/system/Middlewares/OpenAMP/libmetal/lib/compiler.h b/system/Middlewares/OpenAMP/libmetal/lib/compiler.h index 35dc490f72..cadcd22907 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/compiler.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/compiler.h @@ -16,7 +16,7 @@ # include #elif defined(__ICCARM__) # include -#elif defined(__CC_ARM) +#elif defined(__ARMCC_VERSION) # error "MDK-ARM ARMCC compiler requires the GNU extentions to work correctly" #else # error "Missing compiler support" diff --git a/system/Middlewares/OpenAMP/libmetal/lib/errno.h b/system/Middlewares/OpenAMP/libmetal/lib/errno.h index e84a2bc7d7..fa8270dbf4 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/errno.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/errno.h @@ -14,7 +14,7 @@ #if defined(__ICCARM__) # include -#elif defined(__CC_ARM) +#elif defined(__ARMCC_VERSION) # include #else # include diff --git a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/atomic.h b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/atomic.h index 50951e59de..8e08fbedeb 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/atomic.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/atomic.h @@ -94,7 +94,7 @@ using std::atomic_fetch_and_explicit; using std::atomic_thread_fence; using std::atomic_signal_fence; -#elif defined(HAVE_STDATOMIC_H) && !defined(__CC_ARM) && \ +#elif defined(HAVE_STDATOMIC_H) && !defined(__ARMCC_VERSION) && \ !defined(__STDC_NO_ATOMICS__) # include # include diff --git a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/compiler.h b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/compiler.h index 35dc490f72..cadcd22907 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/compiler.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/compiler.h @@ -16,7 +16,7 @@ # include #elif defined(__ICCARM__) # include -#elif defined(__CC_ARM) +#elif defined(__ARMCC_VERSION) # error "MDK-ARM ARMCC compiler requires the GNU extentions to work correctly" #else # error "Missing compiler support" diff --git a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/errno.h b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/errno.h index e84a2bc7d7..fa8270dbf4 100644 --- a/system/Middlewares/OpenAMP/libmetal/lib/include/metal/errno.h +++ b/system/Middlewares/OpenAMP/libmetal/lib/include/metal/errno.h @@ -14,7 +14,7 @@ #if defined(__ICCARM__) # include -#elif defined(__CC_ARM) +#elif defined(__ARMCC_VERSION) # include #else # include diff --git a/system/Middlewares/OpenAMP/libmetal/st_readme.txt b/system/Middlewares/OpenAMP/libmetal/st_readme.txt index 72532d1cf5..16fae578d3 100644 --- a/system/Middlewares/OpenAMP/libmetal/st_readme.txt +++ b/system/Middlewares/OpenAMP/libmetal/st_readme.txt @@ -18,6 +18,16 @@ ****************************************************************************** @endverbatim +### V1.0.6/13-December-2024 ### +=============================== + + Fix compilation error with ARM Compiler verion 6 MDK-ARM + - lib/atomic.h + - lib/errno.h + - lib/compiler.h + - lib/include/metal/atomic.h + - lib/include/metal/errno.h + - lib/include/metal/compiler.h + ### V1.0.5/18-January-2022 ### =============================== + Integrate official release v2021.10