+
+
+
+
+
+
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xe_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xe_FLASH.ld
new file mode 100644
index 0000000000..930cc8f629
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xe_FLASH.ld
@@ -0,0 +1,189 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32U375xE Device from STM32U3 series
+** 512KBytes FLASH
+** 192KBytes RAM
+** 64KBytes RAM2
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K
+ RAM2 (xrw) : ORIGIN = 0x20030000, LENGTH = 64K
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xe_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xe_FLASH_ns.ld
new file mode 100644
index 0000000000..02a0ad5a87
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xe_FLASH_ns.ld
@@ -0,0 +1,189 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32U375xE Device from STM32U3 series
+** 512KBytes FLASH
+** 192KBytes RAM
+** 64KBytes RAM2
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20018000, LENGTH = 96K
+ RAM2 (xrw) : ORIGIN = 0x20038000, LENGTH = 32K
+ FLASH (rx) : ORIGIN = 0x08040000, LENGTH = 256K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xe_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xe_FLASH_s.ld
new file mode 100644
index 0000000000..2735ff20d8
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xe_FLASH_s.ld
@@ -0,0 +1,197 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32U375xE Device from STM32U3 series
+** 512KBytes FLASH
+** 192KBytes RAM
+** 64KBytes RAM2
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 96K
+ RAM2 (xrw) : ORIGIN = 0x30030000, LENGTH = 32K
+ FLASH (rx) : ORIGIN = 0x0C000000, LENGTH = 248K
+ FLASH_NSC (rx) : ORIGIN = 0x0C03E000, LENGTH = 8K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ .gnu.sgstubs :
+ {
+ . = ALIGN(4);
+ *(.gnu.sgstubs*) /* Secure Gateway stubs */
+ . = ALIGN(4);
+ } >FLASH_NSC
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
\ No newline at end of file
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xg_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xg_FLASH.ld
new file mode 100644
index 0000000000..7b3dab0574
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xg_FLASH.ld
@@ -0,0 +1,189 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32U375xG Device from STM32U3 series
+** 1024KBytes FLASH
+** 192KBytes RAM
+** 64KBytes RAM2
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K
+ RAM2 (xrw) : ORIGIN = 0x20030000, LENGTH = 64K
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xg_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xg_FLASH_ns.ld
new file mode 100644
index 0000000000..769f0fdfbb
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xg_FLASH_ns.ld
@@ -0,0 +1,189 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32U375xG Device from STM32U3 series
+** 1024KBytes FLASH
+** 192KBytes RAM
+** 64KBytes RAM2
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20018000, LENGTH = 96K
+ RAM2 (xrw) : ORIGIN = 0x20038000, LENGTH = 32K
+ FLASH (rx) : ORIGIN = 0x08080000, LENGTH = 512K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xg_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xg_FLASH_s.ld
new file mode 100644
index 0000000000..ab3d77ee46
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xg_FLASH_s.ld
@@ -0,0 +1,197 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32U375xG Device from STM32U3 series
+** 1024KBytes FLASH
+** 192KBytes RAM
+** 64KBytes RAM2
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 96K
+ RAM2 (xrw) : ORIGIN = 0x30030000, LENGTH = 32K
+ FLASH (rx) : ORIGIN = 0x0C000000, LENGTH = 504K
+ FLASH_NSC (rx) : ORIGIN = 0x0C07E000, LENGTH = 8K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ .gnu.sgstubs :
+ {
+ . = ALIGN(4);
+ *(.gnu.sgstubs*) /* Secure Gateway stubs */
+ . = ALIGN(4);
+ } >FLASH_NSC
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
\ No newline at end of file
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xx_FLASH.ld
new file mode 100644
index 0000000000..44955f1f2d
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xx_FLASH.ld
@@ -0,0 +1,189 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32U375xx Device from STM32U3 series
+** 1024KBytes FLASH
+** 192KBytes RAM
+** 64KBytes RAM2
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K
+ RAM2 (xrw) : ORIGIN = 0x20030000, LENGTH = 64K
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xx_FLASH_ns.ld
new file mode 100644
index 0000000000..e1a584ebb1
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xx_FLASH_ns.ld
@@ -0,0 +1,189 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32U375xx Device from STM32U3 series
+** 1024KBytes FLASH
+** 192KBytes RAM
+** 64KBytes RAM2
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20018000, LENGTH = 96K
+ RAM2 (xrw) : ORIGIN = 0x20038000, LENGTH = 32K
+ FLASH (rx) : ORIGIN = 0x08080000, LENGTH = 512K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xx_FLASH_s.ld
new file mode 100644
index 0000000000..8ca7c2549a
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xx_FLASH_s.ld
@@ -0,0 +1,197 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32U375xx Device from STM32U3 series
+** 1024KBytes FLASH
+** 192KBytes RAM
+** 64KBytes RAM2
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 96K
+ RAM2 (xrw) : ORIGIN = 0x30030000, LENGTH = 32K
+ FLASH (rx) : ORIGIN = 0x0C000000, LENGTH = 504K
+ FLASH_NSC (rx) : ORIGIN = 0x0C07E000, LENGTH = 8K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ .gnu.sgstubs :
+ {
+ . = ALIGN(4);
+ *(.gnu.sgstubs*) /* Secure Gateway stubs */
+ . = ALIGN(4);
+ } >FLASH_NSC
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
\ No newline at end of file
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xx_RAM.ld
new file mode 100644
index 0000000000..b2255e3998
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xx_RAM.ld
@@ -0,0 +1,187 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32U375xx Device from STM32U3 series
+** 1024KBytes FLASH
+** 256KBytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20030000, LENGTH = 64K
+ FLASH (rx) : ORIGIN = 0x0A000000, LENGTH = 192K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xx_RAM_ns.ld
new file mode 100644
index 0000000000..c973578b7c
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xx_RAM_ns.ld
@@ -0,0 +1,187 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32U375xx Device from STM32U3 series
+** 1024KBytes FLASH
+** 256KBytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20038000, LENGTH = 32K
+ FLASH (rx) : ORIGIN = 0x0A018000, LENGTH = 96K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xx_RAM_s.ld
new file mode 100644
index 0000000000..2d6794ef2c
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U375xx_RAM_s.ld
@@ -0,0 +1,195 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32U375xx Device from STM32U3 series
+** 1024KBytes FLASH
+** 256KBytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x30030000, LENGTH = 32K
+ FLASH (rx) : ORIGIN = 0x0E000000, LENGTH = 92K
+ FLASH_NSC (rx) : ORIGIN = 0x0E017000, LENGTH = 4K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ .gnu.sgstubs :
+ {
+ . = ALIGN(4);
+ *(.gnu.sgstubs*) /* Secure Gateway stubs */
+ . = ALIGN(4);
+ } >FLASH_NSC
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U385xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U385xx_FLASH.ld
new file mode 100644
index 0000000000..339db83c33
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U385xx_FLASH.ld
@@ -0,0 +1,189 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32U385xx Device from STM32U3 series
+** 1024KBytes FLASH
+** 192KBytes RAM
+** 64KBytes RAM2
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K
+ RAM2 (xrw) : ORIGIN = 0x20030000, LENGTH = 64K
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
\ No newline at end of file
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U385xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U385xx_FLASH_ns.ld
new file mode 100644
index 0000000000..826b24491c
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U385xx_FLASH_ns.ld
@@ -0,0 +1,189 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32U385xx Device from STM32U3 series
+** 1024KBytes FLASH
+** 192KBytes RAM
+** 64KBytes RAM2
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20018000, LENGTH = 96K
+ RAM2 (xrw) : ORIGIN = 0x20038000, LENGTH = 32K
+ FLASH (rx) : ORIGIN = 0x08080000, LENGTH = 512K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
\ No newline at end of file
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U385xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U385xx_FLASH_s.ld
new file mode 100644
index 0000000000..b4330bcdbd
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U385xx_FLASH_s.ld
@@ -0,0 +1,197 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32U385xx Device from STM32U3 series
+** 1024KBytes FLASH
+** 192KBytes RAM
+** 64KBytes RAM2
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 96K
+ RAM2 (xrw) : ORIGIN = 0x30030000, LENGTH = 32K
+ FLASH (rx) : ORIGIN = 0x0C000000, LENGTH = 504K
+ FLASH_NSC (rx) : ORIGIN = 0x0C07E000, LENGTH = 8K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ .gnu.sgstubs :
+ {
+ . = ALIGN(4);
+ *(.gnu.sgstubs*) /* Secure Gateway stubs */
+ . = ALIGN(4);
+ } >FLASH_NSC
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
\ No newline at end of file
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U385xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U385xx_RAM.ld
new file mode 100644
index 0000000000..19a4dd0a9d
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U385xx_RAM.ld
@@ -0,0 +1,187 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32U385xx Device from STM32U3 series
+** 1024KBytes FLASH
+** 256KBytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20030000, LENGTH = 64K
+ FLASH (rx) : ORIGIN = 0x0A000000, LENGTH = 192K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
\ No newline at end of file
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U385xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U385xx_RAM_ns.ld
new file mode 100644
index 0000000000..e3b59eed2f
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U385xx_RAM_ns.ld
@@ -0,0 +1,187 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32U385xx Device from STM32U3 series
+** 1024KBytes FLASH
+** 256KBytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20038000, LENGTH = 32K
+ FLASH (rx) : ORIGIN = 0x0A018000, LENGTH = 96K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
\ No newline at end of file
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U385xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U385xx_RAM_s.ld
new file mode 100644
index 0000000000..15a21c9ff5
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/linker/STM32U385xx_RAM_s.ld
@@ -0,0 +1,195 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32U385xx Device from STM32U3 series
+** 1024KBytes FLASH
+** 256KBytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x30030000, LENGTH = 32K
+ FLASH (rx) : ORIGIN = 0x0E000000, LENGTH = 92K
+ FLASH_NSC (rx) : ORIGIN = 0x0E017000, LENGTH = 4K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ .gnu.sgstubs :
+ {
+ . = ALIGN(4);
+ *(.gnu.sgstubs*) /* Secure Gateway stubs */
+ . = ALIGN(4);
+ } >FLASH_NSC
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/startup_stm32u375xx.s b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/startup_stm32u375xx.s
new file mode 100644
index 0000000000..2b0c4b4beb
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/startup_stm32u375xx.s
@@ -0,0 +1,586 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32u375xx.s
+ * @author Auto-generated by STM32CubeIDE
+ * @brief STM32U375CGTx device vector table for GCC toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m33
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M33. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word SecureFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_PVM_IRQHandler
+ .word RTC_IRQHandler
+ .word RTC_S_IRQHandler
+ .word TAMP_IRQHandler
+ .word RAMCFG_IRQHandler
+ .word FLASH_IRQHandler
+ .word FLASH_S_IRQHandler
+ .word GTZC_IRQHandler
+ .word RCC_IRQHandler
+ .word RCC_S_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word EXTI5_IRQHandler
+ .word EXTI6_IRQHandler
+ .word EXTI7_IRQHandler
+ .word EXTI8_IRQHandler
+ .word EXTI9_IRQHandler
+ .word EXTI10_IRQHandler
+ .word EXTI11_IRQHandler
+ .word EXTI12_IRQHandler
+ .word EXTI13_IRQHandler
+ .word EXTI14_IRQHandler
+ .word EXTI15_IRQHandler
+ .word IWDG_IRQHandler
+ .word 0
+ .word GPDMA1_Channel0_IRQHandler
+ .word GPDMA1_Channel1_IRQHandler
+ .word GPDMA1_Channel2_IRQHandler
+ .word GPDMA1_Channel3_IRQHandler
+ .word GPDMA1_Channel4_IRQHandler
+ .word GPDMA1_Channel5_IRQHandler
+ .word GPDMA1_Channel6_IRQHandler
+ .word GPDMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word DAC1_IRQHandler
+ .word FDCAN1_IT0_IRQHandler
+ .word FDCAN1_IT1_IRQHandler
+ .word TIM1_BRK_TERR_IERR_IRQHandler
+ .word TIM1_UP_IRQHandler
+ .word TIM1_TRG_COM_DIR_IDX_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word 0
+ .word TIM6_IRQHandler
+ .word TIM7_IRQHandler
+ .word 0
+ .word 0
+ .word I3C1_EV_IRQHandler
+ .word I3C1_ER_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word 0
+ .word USART3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word LPUART1_IRQHandler
+ .word LPTIM1_IRQHandler
+ .word LPTIM2_IRQHandler
+ .word TIM15_IRQHandler
+ .word TIM16_IRQHandler
+ .word TIM17_IRQHandler
+ .word COMP_IRQHandler
+ .word USB_FS_IRQHandler
+ .word CRS_IRQHandler
+ .word 0
+ .word OCTOSPI1_IRQHandler
+ .word 0
+ .word SDMMC1_IRQHandler
+ .word 0
+ .word GPDMA1_Channel8_IRQHandler
+ .word GPDMA1_Channel9_IRQHandler
+ .word GPDMA1_Channel10_IRQHandler
+ .word GPDMA1_Channel11_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word I2C3_EV_IRQHandler
+ .word I2C3_ER_IRQHandler
+ .word SAI1_IRQHandler
+ .word 0
+ .word TSC_IRQHandler
+ .word 0
+ .word RNG_IRQHandler
+ .word FPU_IRQHandler
+ .word HASH_IRQHandler
+ .word 0
+ .word LPTIM3_IRQHandler
+ .word SPI3_IRQHandler
+ .word I3C2_EV_IRQHandler
+ .word I3C2_ER_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word ICACHE_IRQHandler
+ .word 0
+ .word 0
+ .word LPTIM4_IRQHandler
+ .word 0
+ .word ADF1_IRQHandler
+ .word ADC2_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word PWR_IRQHandler
+ .word PWR_S_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SecureFault_Handler
+ .thumb_set SecureFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak RTC_S_IRQHandler
+ .thumb_set RTC_S_IRQHandler,Default_Handler
+
+ .weak TAMP_IRQHandler
+ .thumb_set TAMP_IRQHandler,Default_Handler
+
+ .weak RAMCFG_IRQHandler
+ .thumb_set RAMCFG_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak FLASH_S_IRQHandler
+ .thumb_set FLASH_S_IRQHandler,Default_Handler
+
+ .weak GTZC_IRQHandler
+ .thumb_set GTZC_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak RCC_S_IRQHandler
+ .thumb_set RCC_S_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak EXTI5_IRQHandler
+ .thumb_set EXTI5_IRQHandler,Default_Handler
+
+ .weak EXTI6_IRQHandler
+ .thumb_set EXTI6_IRQHandler,Default_Handler
+
+ .weak EXTI7_IRQHandler
+ .thumb_set EXTI7_IRQHandler,Default_Handler
+
+ .weak EXTI8_IRQHandler
+ .thumb_set EXTI8_IRQHandler,Default_Handler
+
+ .weak EXTI9_IRQHandler
+ .thumb_set EXTI9_IRQHandler,Default_Handler
+
+ .weak EXTI10_IRQHandler
+ .thumb_set EXTI10_IRQHandler,Default_Handler
+
+ .weak EXTI11_IRQHandler
+ .thumb_set EXTI11_IRQHandler,Default_Handler
+
+ .weak EXTI12_IRQHandler
+ .thumb_set EXTI12_IRQHandler,Default_Handler
+
+ .weak EXTI13_IRQHandler
+ .thumb_set EXTI13_IRQHandler,Default_Handler
+
+ .weak EXTI14_IRQHandler
+ .thumb_set EXTI14_IRQHandler,Default_Handler
+
+ .weak EXTI15_IRQHandler
+ .thumb_set EXTI15_IRQHandler,Default_Handler
+
+ .weak IWDG_IRQHandler
+ .thumb_set IWDG_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel0_IRQHandler
+ .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel1_IRQHandler
+ .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel2_IRQHandler
+ .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel3_IRQHandler
+ .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel4_IRQHandler
+ .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel5_IRQHandler
+ .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel6_IRQHandler
+ .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel7_IRQHandler
+ .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak DAC1_IRQHandler
+ .thumb_set DAC1_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TERR_IERR_IRQHandler
+ .thumb_set TIM1_BRK_TERR_IERR_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_DIR_IDX_IRQHandler
+ .thumb_set TIM1_TRG_COM_DIR_IDX_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak I3C1_EV_IRQHandler
+ .thumb_set I3C1_EV_IRQHandler,Default_Handler
+
+ .weak I3C1_ER_IRQHandler
+ .thumb_set I3C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak USB_FS_IRQHandler
+ .thumb_set USB_FS_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak OCTOSPI1_IRQHandler
+ .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel8_IRQHandler
+ .thumb_set GPDMA1_Channel8_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel9_IRQHandler
+ .thumb_set GPDMA1_Channel9_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel10_IRQHandler
+ .thumb_set GPDMA1_Channel10_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel11_IRQHandler
+ .thumb_set GPDMA1_Channel11_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak TSC_IRQHandler
+ .thumb_set TSC_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak HASH_IRQHandler
+ .thumb_set HASH_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak I3C2_EV_IRQHandler
+ .thumb_set I3C2_EV_IRQHandler,Default_Handler
+
+ .weak I3C2_ER_IRQHandler
+ .thumb_set I3C2_ER_IRQHandler,Default_Handler
+
+ .weak ICACHE_IRQHandler
+ .thumb_set ICACHE_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak ADF1_IRQHandler
+ .thumb_set ADF1_IRQHandler,Default_Handler
+
+ .weak ADC2_IRQHandler
+ .thumb_set ADC2_IRQHandler,Default_Handler
+
+ .weak PWR_IRQHandler
+ .thumb_set PWR_IRQHandler,Default_Handler
+
+ .weak PWR_S_IRQHandler
+ .thumb_set PWR_S_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
\ No newline at end of file
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/startup_stm32u385xx.s b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/startup_stm32u385xx.s
new file mode 100644
index 0000000000..050b4189cd
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/gcc/startup_stm32u385xx.s
@@ -0,0 +1,595 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32u385xx.s
+ * @author Auto-generated by STM32CubeIDE
+ * @brief STM32U385RGTxQ device vector table for GCC toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m33
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M33. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word SecureFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_PVM_IRQHandler
+ .word RTC_IRQHandler
+ .word RTC_S_IRQHandler
+ .word TAMP_IRQHandler
+ .word RAMCFG_IRQHandler
+ .word FLASH_IRQHandler
+ .word FLASH_S_IRQHandler
+ .word GTZC_IRQHandler
+ .word RCC_IRQHandler
+ .word RCC_S_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word EXTI5_IRQHandler
+ .word EXTI6_IRQHandler
+ .word EXTI7_IRQHandler
+ .word EXTI8_IRQHandler
+ .word EXTI9_IRQHandler
+ .word EXTI10_IRQHandler
+ .word EXTI11_IRQHandler
+ .word EXTI12_IRQHandler
+ .word EXTI13_IRQHandler
+ .word EXTI14_IRQHandler
+ .word EXTI15_IRQHandler
+ .word IWDG_IRQHandler
+ .word SAES_IRQHandler
+ .word GPDMA1_Channel0_IRQHandler
+ .word GPDMA1_Channel1_IRQHandler
+ .word GPDMA1_Channel2_IRQHandler
+ .word GPDMA1_Channel3_IRQHandler
+ .word GPDMA1_Channel4_IRQHandler
+ .word GPDMA1_Channel5_IRQHandler
+ .word GPDMA1_Channel6_IRQHandler
+ .word GPDMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word DAC1_IRQHandler
+ .word FDCAN1_IT0_IRQHandler
+ .word FDCAN1_IT1_IRQHandler
+ .word TIM1_BRK_TERR_IERR_IRQHandler
+ .word TIM1_UP_IRQHandler
+ .word TIM1_TRG_COM_DIR_IDX_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word 0
+ .word TIM6_IRQHandler
+ .word TIM7_IRQHandler
+ .word 0
+ .word 0
+ .word I3C1_EV_IRQHandler
+ .word I3C1_ER_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word 0
+ .word USART3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word LPUART1_IRQHandler
+ .word LPTIM1_IRQHandler
+ .word LPTIM2_IRQHandler
+ .word TIM15_IRQHandler
+ .word TIM16_IRQHandler
+ .word TIM17_IRQHandler
+ .word COMP_IRQHandler
+ .word USB_FS_IRQHandler
+ .word CRS_IRQHandler
+ .word 0
+ .word OCTOSPI1_IRQHandler
+ .word 0
+ .word SDMMC1_IRQHandler
+ .word 0
+ .word GPDMA1_Channel8_IRQHandler
+ .word GPDMA1_Channel9_IRQHandler
+ .word GPDMA1_Channel10_IRQHandler
+ .word GPDMA1_Channel11_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word I2C3_EV_IRQHandler
+ .word I2C3_ER_IRQHandler
+ .word SAI1_IRQHandler
+ .word 0
+ .word TSC_IRQHandler
+ .word AES_IRQHandler
+ .word RNG_IRQHandler
+ .word FPU_IRQHandler
+ .word HASH_IRQHandler
+ .word PKA_IRQHandler
+ .word LPTIM3_IRQHandler
+ .word SPI3_IRQHandler
+ .word I3C2_EV_IRQHandler
+ .word I3C2_ER_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word ICACHE_IRQHandler
+ .word 0
+ .word 0
+ .word LPTIM4_IRQHandler
+ .word 0
+ .word ADF1_IRQHandler
+ .word ADC2_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word PWR_IRQHandler
+ .word PWR_S_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SecureFault_Handler
+ .thumb_set SecureFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak RTC_S_IRQHandler
+ .thumb_set RTC_S_IRQHandler,Default_Handler
+
+ .weak TAMP_IRQHandler
+ .thumb_set TAMP_IRQHandler,Default_Handler
+
+ .weak RAMCFG_IRQHandler
+ .thumb_set RAMCFG_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak FLASH_S_IRQHandler
+ .thumb_set FLASH_S_IRQHandler,Default_Handler
+
+ .weak GTZC_IRQHandler
+ .thumb_set GTZC_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak RCC_S_IRQHandler
+ .thumb_set RCC_S_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak EXTI5_IRQHandler
+ .thumb_set EXTI5_IRQHandler,Default_Handler
+
+ .weak EXTI6_IRQHandler
+ .thumb_set EXTI6_IRQHandler,Default_Handler
+
+ .weak EXTI7_IRQHandler
+ .thumb_set EXTI7_IRQHandler,Default_Handler
+
+ .weak EXTI8_IRQHandler
+ .thumb_set EXTI8_IRQHandler,Default_Handler
+
+ .weak EXTI9_IRQHandler
+ .thumb_set EXTI9_IRQHandler,Default_Handler
+
+ .weak EXTI10_IRQHandler
+ .thumb_set EXTI10_IRQHandler,Default_Handler
+
+ .weak EXTI11_IRQHandler
+ .thumb_set EXTI11_IRQHandler,Default_Handler
+
+ .weak EXTI12_IRQHandler
+ .thumb_set EXTI12_IRQHandler,Default_Handler
+
+ .weak EXTI13_IRQHandler
+ .thumb_set EXTI13_IRQHandler,Default_Handler
+
+ .weak EXTI14_IRQHandler
+ .thumb_set EXTI14_IRQHandler,Default_Handler
+
+ .weak EXTI15_IRQHandler
+ .thumb_set EXTI15_IRQHandler,Default_Handler
+
+ .weak IWDG_IRQHandler
+ .thumb_set IWDG_IRQHandler,Default_Handler
+
+ .weak SAES_IRQHandler
+ .thumb_set SAES_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel0_IRQHandler
+ .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel1_IRQHandler
+ .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel2_IRQHandler
+ .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel3_IRQHandler
+ .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel4_IRQHandler
+ .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel5_IRQHandler
+ .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel6_IRQHandler
+ .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel7_IRQHandler
+ .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak DAC1_IRQHandler
+ .thumb_set DAC1_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TERR_IERR_IRQHandler
+ .thumb_set TIM1_BRK_TERR_IERR_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_DIR_IDX_IRQHandler
+ .thumb_set TIM1_TRG_COM_DIR_IDX_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak I3C1_EV_IRQHandler
+ .thumb_set I3C1_EV_IRQHandler,Default_Handler
+
+ .weak I3C1_ER_IRQHandler
+ .thumb_set I3C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak USB_FS_IRQHandler
+ .thumb_set USB_FS_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak OCTOSPI1_IRQHandler
+ .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel8_IRQHandler
+ .thumb_set GPDMA1_Channel8_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel9_IRQHandler
+ .thumb_set GPDMA1_Channel9_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel10_IRQHandler
+ .thumb_set GPDMA1_Channel10_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel11_IRQHandler
+ .thumb_set GPDMA1_Channel11_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak TSC_IRQHandler
+ .thumb_set TSC_IRQHandler,Default_Handler
+
+ .weak AES_IRQHandler
+ .thumb_set AES_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak HASH_IRQHandler
+ .thumb_set HASH_IRQHandler,Default_Handler
+
+ .weak PKA_IRQHandler
+ .thumb_set PKA_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak I3C2_EV_IRQHandler
+ .thumb_set I3C2_EV_IRQHandler,Default_Handler
+
+ .weak I3C2_ER_IRQHandler
+ .thumb_set I3C2_ER_IRQHandler,Default_Handler
+
+ .weak ICACHE_IRQHandler
+ .thumb_set ICACHE_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak ADF1_IRQHandler
+ .thumb_set ADF1_IRQHandler,Default_Handler
+
+ .weak ADC2_IRQHandler
+ .thumb_set ADC2_IRQHandler,Default_Handler
+
+ .weak PWR_IRQHandler
+ .thumb_set PWR_IRQHandler,Default_Handler
+
+ .weak PWR_S_IRQHandler
+ .thumb_set PWR_S_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
\ No newline at end of file
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/system_stm32u3xx.c b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/system_stm32u3xx.c
new file mode 100644
index 0000000000..51c08e00cf
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/system_stm32u3xx.c
@@ -0,0 +1,298 @@
+/**
+ ******************************************************************************
+ * @file system_stm32u3xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32u3xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * After each device reset the MSI (12 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32u3xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * This file configures the system clock as follows:
+ *=============================================================================
+ *-----------------------------------------------------------------------------
+ * System Clock source | MSI
+ *-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 12000000
+ *-----------------------------------------------------------------------------
+ * HCLK(Hz) | 12000000
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB3 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ *=============================================================================
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup STM32U3xx_system
+ * @{
+ */
+
+/** @addtogroup STM32U3xx_System_Private_Includes
+ * @{
+ */
+#include "stm32u3xx.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U3xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U3xx_System_Private_Defines
+ * @{
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE 32000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined (MSIRC0_VALUE)
+ #define MSIRC0_VALUE 96000000U /*!< Value of the Internal MSI RC0 oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined (MSIRC1_VALUE)
+ #define MSIRC1_VALUE 24000000U /*!< Value of the Internal MSI RC1 oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in Flash or Sram, else the vector table is kept at the automatic
+ remap of boot address selected */
+/*#define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in Sram else user remap will be done in Flash. */
+/*#define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U3xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U3xx_System_Private_Variables
+ * @{
+ */
+ /* The SystemCoreClock variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+uint32_t SystemCoreClock = (MSIRC1_VALUE >> 1u);
+const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U3xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U3xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
+#endif
+
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is MSI, SystemCoreClock will be computed based on
+ * MSIRC0_VALUE(*) or MSIRC1_VALUE(*), depending on MSI source selected.
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ *
+ * (*) MSIRC0_VALUE and MSIRC1_VALUE are constant defined in stm32u3xx_hal_conf.h
+ * file (default values are respectively 96 MHz and 24 MHz) but the real
+ * value may vary depending on the variations in voltage and temperature.
+ *
+ * (**) HSI_VALUE is a constant defined in stm32u3xx_hal.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***) HSE_VALUE is a constant defined in stm32u3xx_hal.h file (default value
+ * 16 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp, msirange;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (RCC->CFGR1 & RCC_CFGR1_SWS)
+ {
+ case 0x00: /* MSIS used as system clock source */
+ /* Read RCC ICSR1 register */
+ tmp = RCC->ICSCR1;
+ /* Check which MSIS Range is selected */
+ if ((tmp & RCC_ICSCR1_MSIRGSEL) != 0x00u)
+ {
+ /* Check which MSIRCx is selected as MSIS source */
+ if ((tmp & RCC_ICSCR1_MSISSEL) != 0x00u)
+ {
+ /* MSI RC1 is selected */
+ SystemCoreClock = MSIRC1_VALUE;
+ }
+ else
+ {
+ /* MSI RC0 is selected */
+ SystemCoreClock = MSIRC0_VALUE;
+ }
+
+ /* Get MSIS range */
+ msirange = (tmp & RCC_ICSCR1_MSISDIV) >> RCC_ICSCR1_MSISDIV_Pos;
+ }
+ else
+ {
+ /* MSI RC1 is selected */
+ SystemCoreClock = MSIRC1_VALUE;
+
+ /* Get MSIS range */
+ msirange = (RCC->CSR & (RCC_CSR_MSISDIVS_1 | RCC_CSR_MSISDIVS_0)) >> RCC_CSR_MSISDIVS_Pos;
+ }
+
+ /*MSIS frequency in HZ*/
+ SystemCoreClock >>= msirange;
+ break;
+
+ case RCC_CFGR1_SWS_0: /* HSI used as system clock source */
+ SystemCoreClock = HSI_VALUE;
+ break;
+
+ case RCC_CFGR1_SWS_1: /* HSE used as system clock source */
+ SystemCoreClock = HSE_VALUE;
+ break;
+
+ default:
+ SystemCoreClock = 0xFFFFFFFFu;
+ break;
+ }
+
+ /* Compute HCLK clock frequency --------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/system_stm32u3xx_ns.c b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/system_stm32u3xx_ns.c
new file mode 100644
index 0000000000..172ec766d4
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/system_stm32u3xx_ns.c
@@ -0,0 +1,219 @@
+/**
+ ******************************************************************************
+ * @file system_stm32u3xx_ns.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
+ * to be used in non-secure application when the system implements
+ * the TrustZone-M security.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32u3xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * After each device reset the MSI (12 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32u3xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup STM32U3xx_system
+ * @{
+ */
+
+/** @addtogroup STM32U3xx_System_Private_Includes
+ * @{
+ */
+#include "stm32u3xx.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U3xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U3xx_System_Private_Defines
+ * @{
+ */
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in Flash or Sram, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in Sram else user remap will be done in Flash. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U3xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U3xx_System_Private_Variables
+ * @{
+ */
+ /* The SystemCoreClock variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+uint32_t SystemCoreClock = (MSIRC1_VALUE >> 1u);
+const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U3xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U3xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ * @param None
+ * @retval None
+ */
+
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
+#endif
+
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note From the non-secure application, the SystemCoreClock value is
+ * retrieved from the secure domain via a Non-Secure Callable function
+ * since the RCC peripheral may be protected with security attributes
+ * that prevent to compute the SystemCoreClock variable from the RCC
+ * peripheral registers.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is MSI, SystemCoreClock will be computed based on
+ * MSIRC0_VALUE(*) or MSIRC1_VALUE(*), depending on MSI source selected.
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ *
+ * (*) MSIRC0_VALUE and MSIRC1_VALUE are constant defined in stm32u3xx_hal_conf.h
+ * file (default values are respectively 96 MHz and 24 MHz) but the real
+ * value may vary depending on the variations in voltage and temperature.
+ *
+ * (**) HSI_VALUE is a constant defined in stm32u3xx_hal.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***) HSE_VALUE is a constant defined in stm32u3xx_hal.h file (default value
+ * 16 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ /* Get the SystemCoreClock value from the secure domain */
+ SystemCoreClock = SECURE_SystemCoreClockUpdate();
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/system_stm32u3xx_s.c b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/system_stm32u3xx_s.c
new file mode 100644
index 0000000000..082179f405
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/Source/Templates/system_stm32u3xx_s.c
@@ -0,0 +1,332 @@
+/**
+ ******************************************************************************
+ * @file system_stm32u3xx_s.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
+ * to be used in secure application when the system implements
+ * the TrustZone-M security.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32u3xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * - SECURE_SystemCoreClockUpdate(): Non-secure callable function to update
+ * the variable SystemCoreClock and return
+ * its value to the non-secure calling
+ * application. It must be called whenever
+ * the core clock is changed during program
+ * execution.
+ *
+ * After each device reset the MSI (12 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32u3xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * This file configures the system clock as follows:
+ *=============================================================================
+ *-----------------------------------------------------------------------------
+ * System Clock source | MSI
+ *-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 12000000
+ *-----------------------------------------------------------------------------
+ * HCLK(Hz) | 12000000
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB3 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ *=============================================================================
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup STM32U3xx_system
+ * @{
+ */
+
+/** @addtogroup STM32U3xx_System_Private_Includes
+ * @{
+ */
+#include "stm32u3xx.h"
+#include "partition_stm32u3xx.h" /* Trustzone-M core secure attributes */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U3xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+#if defined ( __ICCARM__ )
+# define CMSE_NS_ENTRY __cmse_nonsecure_entry
+#else
+# define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry))
+#endif
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U3xx_System_Private_Defines
+ * @{
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE 32000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined (MSIRC0_VALUE)
+ #define MSIRC0_VALUE 96000000U /*!< Value of the Internal MSI RC0 oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined (MSIRC1_VALUE)
+ #define MSIRC1_VALUE 24000000U /*!< Value of the Internal MSI RC1 oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in Flash or Sram, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in Sram else user remap will be done in Flash. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U3xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U3xx_System_Private_Variables
+ * @{
+ */
+ /* The SystemCoreClock variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+uint32_t SystemCoreClock = (MSIRC1_VALUE >> 1u);
+const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U3xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32U3xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ * @param None
+ * @retval None
+ */
+
+void SystemInit(void)
+{
+ /* SAU/IDAU, FPU and Interrupts secure/non-secure allocation settings */
+ TZ_SAU_Setup();
+
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
+#endif
+
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is MSI, SystemCoreClock will be computed based on
+ * MSIRC0_VALUE(*) or MSIRC1_VALUE(*), depending on MSI source selected.
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ *
+ * (*) MSIRC0_VALUE and MSIRC1_VALUE are constant defined in stm32u3xx_hal_conf.h
+ * file (default values are respectively 96 MHz and 24 MHz) but the real
+ * value may vary depending on the variations in voltage and temperature.
+ *
+ * (**) HSI_VALUE is a constant defined in stm32u3xx_hal.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***) HSE_VALUE is a constant defined in stm32u3xx_hal.h file (default value
+ * 16 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp, msirange;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (RCC->CFGR1 & RCC_CFGR1_SWS)
+ {
+ case 0x00: /* MSIS used as system clock source */
+ /* Read RCC ICSR1 register */
+ tmp = RCC->ICSCR1;
+ /* Check which MSIS Range is selected */
+ if ((tmp & RCC_ICSCR1_MSIRGSEL) != 0x00u)
+ {
+ /* Check which MSIRCx is selected as MSIS source */
+ if ((tmp & RCC_ICSCR1_MSISSEL) != 0x00u)
+ {
+ /* MSI RC1 is selected */
+ SystemCoreClock = MSIRC1_VALUE;
+ }
+ else
+ {
+ /* MSI RC0 is selected */
+ SystemCoreClock = MSIRC0_VALUE;
+ }
+
+ /* Get MSIS range */
+ msirange = (tmp & RCC_ICSCR1_MSISDIV) >> RCC_ICSCR1_MSISDIV_Pos;
+ }
+ else
+ {
+ /* MSI RC1 is selected */
+ SystemCoreClock = MSIRC1_VALUE;
+
+ /* Get MSIS range */
+ msirange = (RCC->CSR & (RCC_CSR_MSISDIVS_1 | RCC_CSR_MSISDIVS_0)) >> RCC_CSR_MSISDIVS_Pos;
+ }
+
+ /*MSIS frequency in HZ*/
+ SystemCoreClock >>= msirange;
+ break;
+
+ case RCC_CFGR1_SWS_0: /* HSI used as system clock source */
+ SystemCoreClock = HSI_VALUE;
+ break;
+
+ case RCC_CFGR1_SWS_1: /* HSE used as system clock source */
+ SystemCoreClock = HSE_VALUE;
+ break;
+
+ default:
+ SystemCoreClock = 0xFFFFFFFFu;
+ break;
+ }
+
+ /* Compute HCLK clock frequency --------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Secure Non-Secure-Callable function to return the current
+ * SystemCoreClock value after SystemCoreClock update.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ * @retval SystemCoreClock value (HCLK)
+ */
+CMSE_NS_ENTRY uint32_t SECURE_SystemCoreClockUpdate(void)
+{
+ SystemCoreClockUpdate();
+
+ return SystemCoreClock;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/_htmresc/Add button.svg b/system/Drivers/CMSIS/Device/ST/STM32U3xx/_htmresc/Add button.svg
new file mode 100644
index 0000000000..c211545dad
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/_htmresc/Add button.svg
@@ -0,0 +1,2 @@
+
+
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/_htmresc/Update.svg b/system/Drivers/CMSIS/Device/ST/STM32U3xx/_htmresc/Update.svg
new file mode 100644
index 0000000000..f88381f1e6
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/_htmresc/Update.svg
@@ -0,0 +1,2 @@
+
+
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/_htmresc/favicon.png b/system/Drivers/CMSIS/Device/ST/STM32U3xx/_htmresc/favicon.png
new file mode 100644
index 0000000000..06713eec49
Binary files /dev/null and b/system/Drivers/CMSIS/Device/ST/STM32U3xx/_htmresc/favicon.png differ
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/_htmresc/mini-st_2020.css b/system/Drivers/CMSIS/Device/ST/STM32U3xx/_htmresc/mini-st_2020.css
new file mode 100644
index 0000000000..db8b406aa4
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32U3xx/_htmresc/mini-st_2020.css
@@ -0,0 +1,1711 @@
+@charset "UTF-8";
+/*
+ Flavor name: Custom (mini-custom)
+ Generated online - https://minicss.org/flavors
+ mini.css version: v3.0.1
+*/
+/*
+ Browsers resets and base typography.
+*/
+/* Core module CSS variable definitions */
+:root {
+ --fore-color: #03234b;
+ --secondary-fore-color: #03234b;
+ --back-color: #ffffff;
+ --secondary-back-color: #ffffff;
+ --blockquote-color: #e6007e;
+ --pre-color: #e6007e;
+ --border-color: #3cb4e6;
+ --secondary-border-color: #3cb4e6;
+ --heading-ratio: 1.2;
+ --universal-margin: 0.5rem;
+ --universal-padding: 0.25rem;
+ --universal-border-radius: 0.075rem;
+ --background-margin: 1.5%;
+ --a-link-color: #3cb4e6;
+ --a-visited-color: #8c0078; }
+
+html {
+ font-size: 13.5px; }
+
+a, b, del, em, i, ins, q, span, strong, u {
+ font-size: 1em; }
+
+html, * {
+ font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif;
+ line-height: 1.25;
+ -webkit-text-size-adjust: 100%; }
+
+* {
+ font-size: 1rem; }
+
+body {
+ margin: 0;
+ color: var(--fore-color);
+ @background: var(--back-color);
+ background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top;
+ background-size: var(--background-margin);
+ }
+
+details {
+ display: block; }
+
+summary {
+ display: list-item; }
+
+abbr[title] {
+ border-bottom: none;
+ text-decoration: underline dotted; }
+
+input {
+ overflow: visible; }
+
+img {
+ max-width: 100%;
+ height: auto; }
+
+h1, h2, h3, h4, h5, h6 {
+ line-height: 1.25;
+ margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+ font-weight: 400; }
+ h1 small, h2 small, h3 small, h4 small, h5 small, h6 small {
+ color: var(--secondary-fore-color);
+ display: block;
+ margin-top: -0.25rem; }
+
+h1 {
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); }
+
+h2 {
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) );
+ border-style: none none solid none ;
+ border-width: thin;
+ border-color: var(--border-color); }
+h3 {
+ font-size: calc(1rem * var(--heading-ratio) ); }
+
+h4 {
+ font-size: calc(1rem * var(--heading-ratio)); }
+
+h5 {
+ font-size: 1rem; }
+
+h6 {
+ font-size: calc(1rem / var(--heading-ratio)); }
+
+p {
+ margin: var(--universal-margin); }
+
+ol, ul {
+ margin: var(--universal-margin);
+ padding-left: calc(3 * var(--universal-margin)); }
+
+b, strong {
+ font-weight: 700; }
+
+hr {
+ box-sizing: content-box;
+ border: 0;
+ line-height: 1.25em;
+ margin: var(--universal-margin);
+ height: 0.0714285714rem;
+ background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); }
+
+blockquote {
+ display: block;
+ position: relative;
+ font-style: italic;
+ color: var(--secondary-fore-color);
+ margin: var(--universal-margin);
+ padding: calc(3 * var(--universal-padding));
+ border: 0.0714285714rem solid var(--secondary-border-color);
+ border-left: 0.3rem solid var(--blockquote-color);
+ border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+ blockquote:before {
+ position: absolute;
+ top: calc(0rem - var(--universal-padding));
+ left: 0;
+ font-family: sans-serif;
+ font-size: 2rem;
+ font-weight: 800;
+ content: "\201c";
+ color: var(--blockquote-color); }
+ blockquote[cite]:after {
+ font-style: normal;
+ font-size: 0.75em;
+ font-weight: 700;
+ content: "\a— " attr(cite);
+ white-space: pre; }
+
+code, kbd, pre, samp {
+ font-family: Menlo, Consolas, monospace;
+ font-size: 0.85em; }
+
+code {
+ background: var(--secondary-back-color);
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+kbd {
+ background: var(--fore-color);
+ color: var(--back-color);
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+pre {
+ overflow: auto;
+ background: var(--secondary-back-color);
+ padding: calc(1.5 * var(--universal-padding));
+ margin: var(--universal-margin);
+ border: 0.0714285714rem solid var(--secondary-border-color);
+ border-left: 0.2857142857rem solid var(--pre-color);
+ border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+
+sup, sub, code, kbd {
+ line-height: 0;
+ position: relative;
+ vertical-align: baseline; }
+
+small, sup, sub, figcaption {
+ font-size: 0.75em; }
+
+sup {
+ top: -0.5em; }
+
+sub {
+ bottom: -0.25em; }
+
+figure {
+ margin: var(--universal-margin); }
+
+figcaption {
+ color: var(--secondary-fore-color); }
+
+a {
+ text-decoration: none; }
+ a:link {
+ color: var(--a-link-color); }
+ a:visited {
+ color: var(--a-visited-color); }
+ a:hover, a:focus {
+ text-decoration: underline; }
+
+/*
+ Definitions for the grid system, cards and containers.
+*/
+.container {
+ margin: 0 auto;
+ padding: 0 calc(1.5 * var(--universal-padding)); }
+
+.row {
+ box-sizing: border-box;
+ display: flex;
+ flex: 0 1 auto;
+ flex-flow: row wrap;
+ margin: 0 0 0 var(--background-margin); }
+
+.col-sm,
+[class^='col-sm-'],
+[class^='col-sm-offset-'],
+.row[class*='cols-sm-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+.col-sm,
+.row.cols-sm > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+.col-sm-1,
+.row.cols-sm-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+.col-sm-offset-0 {
+ margin-left: 0; }
+
+.col-sm-2,
+.row.cols-sm-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+.col-sm-offset-1 {
+ margin-left: 8.3333333333%; }
+
+.col-sm-3,
+.row.cols-sm-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+.col-sm-offset-2 {
+ margin-left: 16.6666666667%; }
+
+.col-sm-4,
+.row.cols-sm-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+.col-sm-offset-3 {
+ margin-left: 25%; }
+
+.col-sm-5,
+.row.cols-sm-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+.col-sm-offset-4 {
+ margin-left: 33.3333333333%; }
+
+.col-sm-6,
+.row.cols-sm-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+.col-sm-offset-5 {
+ margin-left: 41.6666666667%; }
+
+.col-sm-7,
+.row.cols-sm-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+.col-sm-offset-6 {
+ margin-left: 50%; }
+
+.col-sm-8,
+.row.cols-sm-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+.col-sm-offset-7 {
+ margin-left: 58.3333333333%; }
+
+.col-sm-9,
+.row.cols-sm-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+.col-sm-offset-8 {
+ margin-left: 66.6666666667%; }
+
+.col-sm-10,
+.row.cols-sm-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+.col-sm-offset-9 {
+ margin-left: 75%; }
+
+.col-sm-11,
+.row.cols-sm-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+.col-sm-offset-10 {
+ margin-left: 83.3333333333%; }
+
+.col-sm-12,
+.row.cols-sm-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+.col-sm-offset-11 {
+ margin-left: 91.6666666667%; }
+
+.col-sm-normal {
+ order: initial; }
+
+.col-sm-first {
+ order: -999; }
+
+.col-sm-last {
+ order: 999; }
+
+@media screen and (min-width: 500px) {
+ .col-md,
+ [class^='col-md-'],
+ [class^='col-md-offset-'],
+ .row[class*='cols-md-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+ .col-md,
+ .row.cols-md > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+ .col-md-1,
+ .row.cols-md-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+ .col-md-offset-0 {
+ margin-left: 0; }
+
+ .col-md-2,
+ .row.cols-md-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+ .col-md-offset-1 {
+ margin-left: 8.3333333333%; }
+
+ .col-md-3,
+ .row.cols-md-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+ .col-md-offset-2 {
+ margin-left: 16.6666666667%; }
+
+ .col-md-4,
+ .row.cols-md-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+ .col-md-offset-3 {
+ margin-left: 25%; }
+
+ .col-md-5,
+ .row.cols-md-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+ .col-md-offset-4 {
+ margin-left: 33.3333333333%; }
+
+ .col-md-6,
+ .row.cols-md-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+ .col-md-offset-5 {
+ margin-left: 41.6666666667%; }
+
+ .col-md-7,
+ .row.cols-md-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+ .col-md-offset-6 {
+ margin-left: 50%; }
+
+ .col-md-8,
+ .row.cols-md-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+ .col-md-offset-7 {
+ margin-left: 58.3333333333%; }
+
+ .col-md-9,
+ .row.cols-md-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+ .col-md-offset-8 {
+ margin-left: 66.6666666667%; }
+
+ .col-md-10,
+ .row.cols-md-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+ .col-md-offset-9 {
+ margin-left: 75%; }
+
+ .col-md-11,
+ .row.cols-md-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+ .col-md-offset-10 {
+ margin-left: 83.3333333333%; }
+
+ .col-md-12,
+ .row.cols-md-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+ .col-md-offset-11 {
+ margin-left: 91.6666666667%; }
+
+ .col-md-normal {
+ order: initial; }
+
+ .col-md-first {
+ order: -999; }
+
+ .col-md-last {
+ order: 999; } }
+@media screen and (min-width: 1280px) {
+ .col-lg,
+ [class^='col-lg-'],
+ [class^='col-lg-offset-'],
+ .row[class*='cols-lg-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+ .col-lg,
+ .row.cols-lg > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+ .col-lg-1,
+ .row.cols-lg-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+ .col-lg-offset-0 {
+ margin-left: 0; }
+
+ .col-lg-2,
+ .row.cols-lg-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+ .col-lg-offset-1 {
+ margin-left: 8.3333333333%; }
+
+ .col-lg-3,
+ .row.cols-lg-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+ .col-lg-offset-2 {
+ margin-left: 16.6666666667%; }
+
+ .col-lg-4,
+ .row.cols-lg-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+ .col-lg-offset-3 {
+ margin-left: 25%; }
+
+ .col-lg-5,
+ .row.cols-lg-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+ .col-lg-offset-4 {
+ margin-left: 33.3333333333%; }
+
+ .col-lg-6,
+ .row.cols-lg-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+ .col-lg-offset-5 {
+ margin-left: 41.6666666667%; }
+
+ .col-lg-7,
+ .row.cols-lg-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+ .col-lg-offset-6 {
+ margin-left: 50%; }
+
+ .col-lg-8,
+ .row.cols-lg-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+ .col-lg-offset-7 {
+ margin-left: 58.3333333333%; }
+
+ .col-lg-9,
+ .row.cols-lg-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+ .col-lg-offset-8 {
+ margin-left: 66.6666666667%; }
+
+ .col-lg-10,
+ .row.cols-lg-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+ .col-lg-offset-9 {
+ margin-left: 75%; }
+
+ .col-lg-11,
+ .row.cols-lg-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+ .col-lg-offset-10 {
+ margin-left: 83.3333333333%; }
+
+ .col-lg-12,
+ .row.cols-lg-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+ .col-lg-offset-11 {
+ margin-left: 91.6666666667%; }
+
+ .col-lg-normal {
+ order: initial; }
+
+ .col-lg-first {
+ order: -999; }
+
+ .col-lg-last {
+ order: 999; } }
+/* Card component CSS variable definitions */
+:root {
+ --card-back-color: #3cb4e6;
+ --card-fore-color: #03234b;
+ --card-border-color: #03234b; }
+
+.card {
+ display: flex;
+ flex-direction: column;
+ justify-content: space-between;
+ align-self: center;
+ position: relative;
+ width: 100%;
+ background: var(--card-back-color);
+ color: var(--card-fore-color);
+ border: 0.0714285714rem solid var(--card-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin);
+ overflow: hidden; }
+ @media screen and (min-width: 320px) {
+ .card {
+ max-width: 320px; } }
+ .card > .sectione {
+ background: var(--card-back-color);
+ color: var(--card-fore-color);
+ box-sizing: border-box;
+ margin: 0;
+ border: 0;
+ border-radius: 0;
+ border-bottom: 0.0714285714rem solid var(--card-border-color);
+ padding: var(--universal-padding);
+ width: 100%; }
+ .card > .sectione.media {
+ height: 200px;
+ padding: 0;
+ -o-object-fit: cover;
+ object-fit: cover; }
+ .card > .sectione:last-child {
+ border-bottom: 0; }
+
+/*
+ Custom elements for card elements.
+*/
+@media screen and (min-width: 240px) {
+ .card.small {
+ max-width: 240px; } }
+@media screen and (min-width: 480px) {
+ .card.large {
+ max-width: 480px; } }
+.card.fluid {
+ max-width: 100%;
+ width: auto; }
+
+.card.warning {
+ --card-back-color: #e5b8b7;
+ --card-fore-color: #3b234b;
+ --card-border-color: #8c0078; }
+
+.card.error {
+ --card-back-color: #464650;
+ --card-fore-color: #ffffff;
+ --card-border-color: #8c0078; }
+
+.card > .sectione.dark {
+ --card-back-color: #3b234b;
+ --card-fore-color: #ffffff; }
+
+.card > .sectione.double-padded {
+ padding: calc(1.5 * var(--universal-padding)); }
+
+/*
+ Definitions for forms and input elements.
+*/
+/* Input_control module CSS variable definitions */
+:root {
+ --form-back-color: #ffe97f;
+ --form-fore-color: #03234b;
+ --form-border-color: #3cb4e6;
+ --input-back-color: #ffffff;
+ --input-fore-color: #03234b;
+ --input-border-color: #3cb4e6;
+ --input-focus-color: #0288d1;
+ --input-invalid-color: #d32f2f;
+ --button-back-color: #e2e2e2;
+ --button-hover-back-color: #dcdcdc;
+ --button-fore-color: #212121;
+ --button-border-color: transparent;
+ --button-hover-border-color: transparent;
+ --button-group-border-color: rgba(124, 124, 124, 0.54); }
+
+form {
+ background: var(--form-back-color);
+ color: var(--form-fore-color);
+ border: 0.0714285714rem solid var(--form-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin);
+ padding: calc(2 * var(--universal-padding)) var(--universal-padding); }
+
+fieldset {
+ border: 0.0714285714rem solid var(--form-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: calc(var(--universal-margin) / 4);
+ padding: var(--universal-padding); }
+
+legend {
+ box-sizing: border-box;
+ display: table;
+ max-width: 100%;
+ white-space: normal;
+ font-weight: 500;
+ padding: calc(var(--universal-padding) / 2); }
+
+label {
+ padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+.input-group {
+ display: inline-block; }
+ .input-group.fluid {
+ display: flex;
+ align-items: center;
+ justify-content: center; }
+ .input-group.fluid > input {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0px; }
+ @media screen and (max-width: 499px) {
+ .input-group.fluid {
+ align-items: stretch;
+ flex-direction: column; } }
+ .input-group.vertical {
+ display: flex;
+ align-items: stretch;
+ flex-direction: column; }
+ .input-group.vertical > input {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0px; }
+
+[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button {
+ height: auto; }
+
+[type="search"] {
+ -webkit-appearance: textfield;
+ outline-offset: -2px; }
+
+[type="search"]::-webkit-search-cancel-button,
+[type="search"]::-webkit-search-decoration {
+ -webkit-appearance: none; }
+
+input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"],
+[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select {
+ box-sizing: border-box;
+ background: var(--input-back-color);
+ color: var(--input-fore-color);
+ border: 0.0714285714rem solid var(--input-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: calc(var(--universal-margin) / 2);
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus {
+ border-color: var(--input-focus-color);
+ box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid {
+ border-color: var(--input-invalid-color);
+ box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] {
+ background: var(--secondary-back-color); }
+
+select {
+ max-width: 100%; }
+
+option {
+ overflow: hidden;
+ text-overflow: ellipsis; }
+
+[type="checkbox"], [type="radio"] {
+ -webkit-appearance: none;
+ -moz-appearance: none;
+ appearance: none;
+ position: relative;
+ height: calc(1rem + var(--universal-padding) / 2);
+ width: calc(1rem + var(--universal-padding) / 2);
+ vertical-align: text-bottom;
+ padding: 0;
+ flex-basis: calc(1rem + var(--universal-padding) / 2) !important;
+ flex-grow: 0 !important; }
+ [type="checkbox"]:checked:before, [type="radio"]:checked:before {
+ position: absolute; }
+
+[type="checkbox"]:checked:before {
+ content: '\2713';
+ font-family: sans-serif;
+ font-size: calc(1rem + var(--universal-padding) / 2);
+ top: calc(0rem - var(--universal-padding));
+ left: calc(var(--universal-padding) / 4); }
+
+[type="radio"] {
+ border-radius: 100%; }
+ [type="radio"]:checked:before {
+ border-radius: 100%;
+ content: '';
+ top: calc(0.0714285714rem + var(--universal-padding) / 2);
+ left: calc(0.0714285714rem + var(--universal-padding) / 2);
+ background: var(--input-fore-color);
+ width: 0.5rem;
+ height: 0.5rem; }
+
+:placeholder-shown {
+ color: var(--input-fore-color); }
+
+::-ms-placeholder {
+ color: var(--input-fore-color);
+ opacity: 0.54; }
+
+button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner {
+ border-style: none;
+ padding: 0; }
+
+button, html [type="button"], [type="reset"], [type="submit"] {
+ -webkit-appearance: button; }
+
+button {
+ overflow: visible;
+ text-transform: none; }
+
+button, [type="button"], [type="submit"], [type="reset"],
+a.button, label.button, .button,
+a[role="button"], label[role="button"], [role="button"] {
+ display: inline-block;
+ background: var(--button-back-color);
+ color: var(--button-fore-color);
+ border: 0.0714285714rem solid var(--button-border-color);
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding));
+ margin: var(--universal-margin);
+ text-decoration: none;
+ cursor: pointer;
+ transition: background 0.3s; }
+ button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus,
+ a.button:hover,
+ a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus,
+ a[role="button"]:hover,
+ a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus {
+ background: var(--button-hover-back-color);
+ border-color: var(--button-hover-border-color); }
+
+input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] {
+ cursor: not-allowed;
+ opacity: 0.75; }
+
+.button-group {
+ display: flex;
+ border: 0.0714285714rem solid var(--button-group-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin); }
+ .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] {
+ margin: 0;
+ max-width: 100%;
+ flex: 1 1 auto;
+ text-align: center;
+ border: 0;
+ border-radius: 0;
+ box-shadow: none; }
+ .button-group > :not(:first-child) {
+ border-left: 0.0714285714rem solid var(--button-group-border-color); }
+ @media screen and (max-width: 499px) {
+ .button-group {
+ flex-direction: column; }
+ .button-group > :not(:first-child) {
+ border: 0;
+ border-top: 0.0714285714rem solid var(--button-group-border-color); } }
+
+/*
+ Custom elements for forms and input elements.
+*/
+button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary {
+ --button-back-color: #1976d2;
+ --button-fore-color: #f8f8f8; }
+ button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus {
+ --button-hover-back-color: #1565c0; }
+
+button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary {
+ --button-back-color: #d32f2f;
+ --button-fore-color: #f8f8f8; }
+ button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus {
+ --button-hover-back-color: #c62828; }
+
+button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary {
+ --button-back-color: #308732;
+ --button-fore-color: #f8f8f8; }
+ button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus {
+ --button-hover-back-color: #277529; }
+
+button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse {
+ --button-back-color: #212121;
+ --button-fore-color: #f8f8f8; }
+ button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus {
+ --button-hover-back-color: #111; }
+
+button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small {
+ padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding));
+ margin: var(--universal-margin); }
+
+button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large {
+ padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding));
+ margin: var(--universal-margin); }
+
+/*
+ Definitions for navigation elements.
+*/
+/* Navigation module CSS variable definitions */
+:root {
+ --header-back-color: #03234b;
+ --header-hover-back-color: #ffd200;
+ --header-fore-color: #ffffff;
+ --header-border-color: #3cb4e6;
+ --nav-back-color: #ffffff;
+ --nav-hover-back-color: #ffe97f;
+ --nav-fore-color: #e6007e;
+ --nav-border-color: #3cb4e6;
+ --nav-link-color: #3cb4e6;
+ --footer-fore-color: #ffffff;
+ --footer-back-color: #03234b;
+ --footer-border-color: #3cb4e6;
+ --footer-link-color: #3cb4e6;
+ --drawer-back-color: #ffffff;
+ --drawer-hover-back-color: #ffe97f;
+ --drawer-border-color: #3cb4e6;
+ --drawer-close-color: #e6007e; }
+
+header {
+ height: 2.75rem;
+ background: var(--header-back-color);
+ color: var(--header-fore-color);
+ border-bottom: 0.0714285714rem solid var(--header-border-color);
+ padding: calc(var(--universal-padding) / 4) 0;
+ white-space: nowrap;
+ overflow-x: auto;
+ overflow-y: hidden; }
+ header.row {
+ box-sizing: content-box; }
+ header .logo {
+ color: var(--header-fore-color);
+ font-size: 1.75rem;
+ padding: var(--universal-padding) calc(2 * var(--universal-padding));
+ text-decoration: none; }
+ header button, header [type="button"], header .button, header [role="button"] {
+ box-sizing: border-box;
+ position: relative;
+ top: calc(0rem - var(--universal-padding) / 4);
+ height: calc(3.1875rem + var(--universal-padding) / 2);
+ background: var(--header-back-color);
+ line-height: calc(3.1875rem - var(--universal-padding) * 1.5);
+ text-align: center;
+ color: var(--header-fore-color);
+ border: 0;
+ border-radius: 0;
+ margin: 0;
+ text-transform: uppercase; }
+ header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus {
+ background: var(--header-hover-back-color); }
+
+nav {
+ background: var(--nav-back-color);
+ color: var(--nav-fore-color);
+ border: 0.0714285714rem solid var(--nav-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin); }
+ nav * {
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+ nav a, nav a:visited {
+ display: block;
+ color: var(--nav-link-color);
+ border-radius: var(--universal-border-radius);
+ transition: background 0.3s; }
+ nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus {
+ text-decoration: none;
+ background: var(--nav-hover-back-color); }
+ nav .sublink-1 {
+ position: relative;
+ margin-left: calc(2 * var(--universal-padding)); }
+ nav .sublink-1:before {
+ position: absolute;
+ left: calc(var(--universal-padding) - 1 * var(--universal-padding));
+ top: -0.0714285714rem;
+ content: '';
+ height: 100%;
+ border: 0.0714285714rem solid var(--nav-border-color);
+ border-left: 0; }
+ nav .sublink-2 {
+ position: relative;
+ margin-left: calc(4 * var(--universal-padding)); }
+ nav .sublink-2:before {
+ position: absolute;
+ left: calc(var(--universal-padding) - 3 * var(--universal-padding));
+ top: -0.0714285714rem;
+ content: '';
+ height: 100%;
+ border: 0.0714285714rem solid var(--nav-border-color);
+ border-left: 0; }
+
+footer {
+ background: var(--footer-back-color);
+ color: var(--footer-fore-color);
+ border-top: 0.0714285714rem solid var(--footer-border-color);
+ padding: calc(2 * var(--universal-padding)) var(--universal-padding);
+ font-size: 0.875rem; }
+ footer a, footer a:visited {
+ color: var(--footer-link-color); }
+
+header.sticky {
+ position: -webkit-sticky;
+ position: sticky;
+ z-index: 1101;
+ top: 0; }
+
+footer.sticky {
+ position: -webkit-sticky;
+ position: sticky;
+ z-index: 1101;
+ bottom: 0; }
+
+.drawer-toggle:before {
+ display: inline-block;
+ position: relative;
+ vertical-align: bottom;
+ content: '\00a0\2261\00a0';
+ font-family: sans-serif;
+ font-size: 1.5em; }
+@media screen and (min-width: 500px) {
+ .drawer-toggle:not(.persistent) {
+ display: none; } }
+
+[type="checkbox"].drawer {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ [type="checkbox"].drawer + * {
+ display: block;
+ box-sizing: border-box;
+ position: fixed;
+ top: 0;
+ width: 320px;
+ height: 100vh;
+ overflow-y: auto;
+ background: var(--drawer-back-color);
+ border: 0.0714285714rem solid var(--drawer-border-color);
+ border-radius: 0;
+ margin: 0;
+ z-index: 1110;
+ right: -320px;
+ transition: right 0.3s; }
+ [type="checkbox"].drawer + * .drawer-close {
+ position: absolute;
+ top: var(--universal-margin);
+ right: var(--universal-margin);
+ z-index: 1111;
+ width: 2rem;
+ height: 2rem;
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ margin: 0;
+ cursor: pointer;
+ transition: background 0.3s; }
+ [type="checkbox"].drawer + * .drawer-close:before {
+ display: block;
+ content: '\00D7';
+ color: var(--drawer-close-color);
+ position: relative;
+ font-family: sans-serif;
+ font-size: 2rem;
+ line-height: 1;
+ text-align: center; }
+ [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus {
+ background: var(--drawer-hover-back-color); }
+ @media screen and (max-width: 320px) {
+ [type="checkbox"].drawer + * {
+ width: 100%; } }
+ [type="checkbox"].drawer:checked + * {
+ right: 0; }
+ @media screen and (min-width: 500px) {
+ [type="checkbox"].drawer:not(.persistent) + * {
+ position: static;
+ height: 100%;
+ z-index: 1100; }
+ [type="checkbox"].drawer:not(.persistent) + * .drawer-close {
+ display: none; } }
+
+/*
+ Definitions for the responsive table component.
+*/
+/* Table module CSS variable definitions. */
+:root {
+ --table-border-color: #03234b;
+ --table-border-separator-color: #03234b;
+ --table-head-back-color: #03234b;
+ --table-head-fore-color: #ffffff;
+ --table-body-back-color: #ffffff;
+ --table-body-fore-color: #03234b;
+ --table-body-alt-back-color: #f4f4f4; }
+
+table {
+ border-collapse: separate;
+ border-spacing: 0;
+ margin: 0;
+ display: flex;
+ flex: 0 1 auto;
+ flex-flow: row wrap;
+ padding: var(--universal-padding);
+ padding-top: 0; }
+ table caption {
+ font-size: 1rem;
+ margin: calc(2 * var(--universal-margin)) 0;
+ max-width: 100%;
+ flex: 0 0 100%; }
+ table thead, table tbody {
+ display: flex;
+ flex-flow: row wrap;
+ border: 0.0714285714rem solid var(--table-border-color); }
+ table thead {
+ z-index: 999;
+ border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0;
+ border-bottom: 0.0714285714rem solid var(--table-border-separator-color); }
+ table tbody {
+ border-top: 0;
+ margin-top: calc(0 - var(--universal-margin));
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+ table tr {
+ display: flex;
+ padding: 0; }
+ table th, table td {
+ padding: calc(0.5 * var(--universal-padding));
+ font-size: 0.9rem; }
+ table th {
+ text-align: left;
+ background: var(--table-head-back-color);
+ color: var(--table-head-fore-color); }
+ table td {
+ background: var(--table-body-back-color);
+ color: var(--table-body-fore-color);
+ border-top: 0.0714285714rem solid var(--table-border-color); }
+
+table:not(.horizontal) {
+ overflow: auto;
+ max-height: 100%; }
+ table:not(.horizontal) thead, table:not(.horizontal) tbody {
+ max-width: 100%;
+ flex: 0 0 100%; }
+ table:not(.horizontal) tr {
+ flex-flow: row wrap;
+ flex: 0 0 100%; }
+ table:not(.horizontal) th, table:not(.horizontal) td {
+ flex: 1 0 0%;
+ overflow: hidden;
+ text-overflow: ellipsis; }
+ table:not(.horizontal) thead {
+ position: sticky;
+ top: 0; }
+ table:not(.horizontal) tbody tr:first-child td {
+ border-top: 0; }
+
+table.horizontal {
+ border: 0; }
+ table.horizontal thead, table.horizontal tbody {
+ border: 0;
+ flex: .2 0 0;
+ flex-flow: row nowrap; }
+ table.horizontal tbody {
+ overflow: auto;
+ justify-content: space-between;
+ flex: .8 0 0;
+ margin-left: 0;
+ padding-bottom: calc(var(--universal-padding) / 4); }
+ table.horizontal tr {
+ flex-direction: column;
+ flex: 1 0 auto; }
+ table.horizontal th, table.horizontal td {
+ width: auto;
+ border: 0;
+ border-bottom: 0.0714285714rem solid var(--table-border-color); }
+ table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) {
+ border-top: 0; }
+ table.horizontal th {
+ text-align: right;
+ border-left: 0.0714285714rem solid var(--table-border-color);
+ border-right: 0.0714285714rem solid var(--table-border-separator-color); }
+ table.horizontal thead tr:first-child {
+ padding-left: 0; }
+ table.horizontal th:first-child, table.horizontal td:first-child {
+ border-top: 0.0714285714rem solid var(--table-border-color); }
+ table.horizontal tbody tr:last-child td {
+ border-right: 0.0714285714rem solid var(--table-border-color); }
+ table.horizontal tbody tr:last-child td:first-child {
+ border-top-right-radius: 0.25rem; }
+ table.horizontal tbody tr:last-child td:last-child {
+ border-bottom-right-radius: 0.25rem; }
+ table.horizontal thead tr:first-child th:first-child {
+ border-top-left-radius: 0.25rem; }
+ table.horizontal thead tr:first-child th:last-child {
+ border-bottom-left-radius: 0.25rem; }
+
+@media screen and (max-width: 499px) {
+ table, table.horizontal {
+ border-collapse: collapse;
+ border: 0;
+ width: 100%;
+ display: table; }
+ table thead, table th, table.horizontal thead, table.horizontal th {
+ border: 0;
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ padding: 0;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ table tbody, table.horizontal tbody {
+ border: 0;
+ display: table-row-group; }
+ table tr, table.horizontal tr {
+ display: block;
+ border: 0.0714285714rem solid var(--table-border-color);
+ border-radius: var(--universal-border-radius);
+ background: #ffffff;
+ padding: var(--universal-padding);
+ margin: var(--universal-margin);
+ margin-bottom: calc(1 * var(--universal-margin)); }
+ table th, table td, table.horizontal th, table.horizontal td {
+ width: auto; }
+ table td, table.horizontal td {
+ display: block;
+ border: 0;
+ text-align: right; }
+ table td:before, table.horizontal td:before {
+ content: attr(data-label);
+ float: left;
+ font-weight: 600; }
+ table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child {
+ border-top: 0; }
+ table tbody tr:last-child td, table.horizontal tbody tr:last-child td {
+ border-right: 0; } }
+table tr:nth-of-type(2n) > td {
+ background: var(--table-body-alt-back-color); }
+
+@media screen and (max-width: 500px) {
+ table tr:nth-of-type(2n) {
+ background: var(--table-body-alt-back-color); } }
+:root {
+ --table-body-hover-back-color: #90caf9; }
+
+table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+ background: var(--table-body-hover-back-color); }
+
+@media screen and (max-width: 500px) {
+ table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+ background: var(--table-body-hover-back-color); } }
+/*
+ Definitions for contextual background elements, toasts and tooltips.
+*/
+/* Contextual module CSS variable definitions */
+:root {
+ --mark-back-color: #3cb4e6;
+ --mark-fore-color: #ffffff; }
+
+mark {
+ background: var(--mark-back-color);
+ color: var(--mark-fore-color);
+ font-size: 0.95em;
+ line-height: 1em;
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) var(--universal-padding); }
+ mark.inline-block {
+ display: inline-block;
+ font-size: 1em;
+ line-height: 1.4;
+ padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+:root {
+ --toast-back-color: #424242;
+ --toast-fore-color: #fafafa; }
+
+.toast {
+ position: fixed;
+ bottom: calc(var(--universal-margin) * 3);
+ left: 50%;
+ transform: translate(-50%, -50%);
+ z-index: 1111;
+ color: var(--toast-fore-color);
+ background: var(--toast-back-color);
+ border-radius: calc(var(--universal-border-radius) * 16);
+ padding: var(--universal-padding) calc(var(--universal-padding) * 3); }
+
+:root {
+ --tooltip-back-color: #212121;
+ --tooltip-fore-color: #fafafa; }
+
+.tooltip {
+ position: relative;
+ display: inline-block; }
+ .tooltip:before, .tooltip:after {
+ position: absolute;
+ opacity: 0;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%);
+ transition: all 0.3s;
+ z-index: 1010;
+ left: 50%; }
+ .tooltip:not(.bottom):before, .tooltip:not(.bottom):after {
+ bottom: 75%; }
+ .tooltip.bottom:before, .tooltip.bottom:after {
+ top: 75%; }
+ .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after {
+ opacity: 1;
+ clip: auto;
+ -webkit-clip-path: inset(0%);
+ clip-path: inset(0%); }
+ .tooltip:before {
+ content: '';
+ background: transparent;
+ border: var(--universal-margin) solid transparent;
+ left: calc(50% - var(--universal-margin)); }
+ .tooltip:not(.bottom):before {
+ border-top-color: #212121; }
+ .tooltip.bottom:before {
+ border-bottom-color: #212121; }
+ .tooltip:after {
+ content: attr(aria-label);
+ color: var(--tooltip-fore-color);
+ background: var(--tooltip-back-color);
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ white-space: nowrap;
+ transform: translateX(-50%); }
+ .tooltip:not(.bottom):after {
+ margin-bottom: calc(2 * var(--universal-margin)); }
+ .tooltip.bottom:after {
+ margin-top: calc(2 * var(--universal-margin)); }
+
+:root {
+ --modal-overlay-color: rgba(0, 0, 0, 0.45);
+ --modal-close-color: #e6007e;
+ --modal-close-hover-color: #ffe97f; }
+
+[type="checkbox"].modal {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ [type="checkbox"].modal + div {
+ position: fixed;
+ top: 0;
+ left: 0;
+ display: none;
+ width: 100vw;
+ height: 100vh;
+ background: var(--modal-overlay-color); }
+ [type="checkbox"].modal + div .card {
+ margin: 0 auto;
+ max-height: 50vh;
+ overflow: auto; }
+ [type="checkbox"].modal + div .card .modal-close {
+ position: absolute;
+ top: 0;
+ right: 0;
+ width: 1.75rem;
+ height: 1.75rem;
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ margin: 0;
+ cursor: pointer;
+ transition: background 0.3s; }
+ [type="checkbox"].modal + div .card .modal-close:before {
+ display: block;
+ content: '\00D7';
+ color: var(--modal-close-color);
+ position: relative;
+ font-family: sans-serif;
+ font-size: 1.75rem;
+ line-height: 1;
+ text-align: center; }
+ [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus {
+ background: var(--modal-close-hover-color); }
+ [type="checkbox"].modal:checked + div {
+ display: flex;
+ flex: 0 1 auto;
+ z-index: 1200; }
+ [type="checkbox"].modal:checked + div .card .modal-close {
+ z-index: 1211; }
+
+:root {
+ --collapse-label-back-color: #03234b;
+ --collapse-label-fore-color: #ffffff;
+ --collapse-label-hover-back-color: #3cb4e6;
+ --collapse-selected-label-back-color: #3cb4e6;
+ --collapse-border-color: var(--collapse-label-back-color);
+ --collapse-selected-border-color: #ceecf8;
+ --collapse-content-back-color: #ffffff;
+ --collapse-selected-label-border-color: #3cb4e6; }
+
+.collapse {
+ width: calc(100% - 2 * var(--universal-margin));
+ opacity: 1;
+ display: flex;
+ flex-direction: column;
+ margin: var(--universal-margin);
+ border-radius: var(--universal-border-radius); }
+ .collapse > [type="radio"], .collapse > [type="checkbox"] {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ .collapse > label {
+ flex-grow: 1;
+ display: inline-block;
+ height: 1.25rem;
+ cursor: pointer;
+ transition: background 0.2s;
+ color: var(--collapse-label-fore-color);
+ background: var(--collapse-label-back-color);
+ border: 0.0714285714rem solid var(--collapse-selected-border-color);
+ padding: calc(1.25 * var(--universal-padding)); }
+ .collapse > label:hover, .collapse > label:focus {
+ background: var(--collapse-label-hover-back-color); }
+ .collapse > label + div {
+ flex-basis: auto;
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%);
+ transition: max-height 0.3s;
+ max-height: 1px; }
+ .collapse > :checked + label {
+ background: var(--collapse-selected-label-back-color);
+ border-color: var(--collapse-selected-label-border-color); }
+ .collapse > :checked + label + div {
+ box-sizing: border-box;
+ position: relative;
+ width: 100%;
+ height: auto;
+ overflow: auto;
+ margin: 0;
+ background: var(--collapse-content-back-color);
+ border: 0.0714285714rem solid var(--collapse-selected-border-color);
+ border-top: 0;
+ padding: var(--universal-padding);
+ clip: auto;
+ -webkit-clip-path: inset(0%);
+ clip-path: inset(0%);
+ max-height: 100%; }
+ .collapse > label:not(:first-of-type) {
+ border-top: 0; }
+ .collapse > label:first-of-type {
+ border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; }
+ .collapse > label:last-of-type:not(:first-of-type) {
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+ .collapse > label:last-of-type:first-of-type {
+ border-radius: var(--universal-border-radius); }
+ .collapse > :checked:last-of-type:not(:first-of-type) + label {
+ border-radius: 0; }
+ .collapse > :checked:last-of-type + label + div {
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+
+/*
+ Custom elements for contextual background elements, toasts and tooltips.
+*/
+mark.tertiary {
+ --mark-back-color: #3cb4e6; }
+
+mark.tag {
+ padding: calc(var(--universal-padding)/2) var(--universal-padding);
+ border-radius: 1em; }
+
+/*
+ Definitions for progress elements and spinners.
+*/
+/* Progress module CSS variable definitions */
+:root {
+ --progress-back-color: #3cb4e6;
+ --progress-fore-color: #555; }
+
+progress {
+ display: block;
+ vertical-align: baseline;
+ -webkit-appearance: none;
+ -moz-appearance: none;
+ appearance: none;
+ height: 0.75rem;
+ width: calc(100% - 2 * var(--universal-margin));
+ margin: var(--universal-margin);
+ border: 0;
+ border-radius: calc(2 * var(--universal-border-radius));
+ background: var(--progress-back-color);
+ color: var(--progress-fore-color); }
+ progress::-webkit-progress-value {
+ background: var(--progress-fore-color);
+ border-top-left-radius: calc(2 * var(--universal-border-radius));
+ border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+ progress::-webkit-progress-bar {
+ background: var(--progress-back-color); }
+ progress::-moz-progress-bar {
+ background: var(--progress-fore-color);
+ border-top-left-radius: calc(2 * var(--universal-border-radius));
+ border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+ progress[value="1000"]::-webkit-progress-value {
+ border-radius: calc(2 * var(--universal-border-radius)); }
+ progress[value="1000"]::-moz-progress-bar {
+ border-radius: calc(2 * var(--universal-border-radius)); }
+ progress.inline {
+ display: inline-block;
+ vertical-align: middle;
+ width: 60%; }
+
+:root {
+ --spinner-back-color: #ddd;
+ --spinner-fore-color: #555; }
+
+@keyframes spinner-donut-anim {
+ 0% {
+ transform: rotate(0deg); }
+ 100% {
+ transform: rotate(360deg); } }
+.spinner {
+ display: inline-block;
+ margin: var(--universal-margin);
+ border: 0.25rem solid var(--spinner-back-color);
+ border-left: 0.25rem solid var(--spinner-fore-color);
+ border-radius: 50%;
+ width: 1.25rem;
+ height: 1.25rem;
+ animation: spinner-donut-anim 1.2s linear infinite; }
+
+/*
+ Custom elements for progress bars and spinners.
+*/
+progress.primary {
+ --progress-fore-color: #1976d2; }
+
+progress.secondary {
+ --progress-fore-color: #d32f2f; }
+
+progress.tertiary {
+ --progress-fore-color: #308732; }
+
+.spinner.primary {
+ --spinner-fore-color: #1976d2; }
+
+.spinner.secondary {
+ --spinner-fore-color: #d32f2f; }
+
+.spinner.tertiary {
+ --spinner-fore-color: #308732; }
+
+/*
+ Definitions for icons - powered by Feather (https://feathericons.com/).
+*/
+span[class^='icon-'] {
+ display: inline-block;
+ height: 1em;
+ width: 1em;
+ vertical-align: -0.125em;
+ background-size: contain;
+ margin: 0 calc(var(--universal-margin) / 4); }
+ span[class^='icon-'].secondary {
+ -webkit-filter: invert(25%);
+ filter: invert(25%); }
+ span[class^='icon-'].inverse {
+ -webkit-filter: invert(100%);
+ filter: invert(100%); }
+
+span.icon-alert {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-bookmark {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-calendar {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-credit {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-edit {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
+span.icon-link {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-help {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-home {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-info {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-lock {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-mail {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-location {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-phone {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-rss {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-search {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-settings {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-share {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-cart {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-upload {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-user {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
+
+/*
+ Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26).
+*/
+span.icon-st-update {
+ background-image: url("Update.svg"); }
+span.icon-st-add {
+ background-image: url("Add button.svg"); }
+
+/*
+ Definitions for utilities and helper classes.
+*/
+/* Utility module CSS variable definitions */
+:root {
+ --generic-border-color: rgba(0, 0, 0, 0.3);
+ --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); }
+
+.hidden {
+ display: none !important; }
+
+.visually-hidden {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; }
+
+.bordered {
+ border: 0.0714285714rem solid var(--generic-border-color) !important; }
+
+.rounded {
+ border-radius: var(--universal-border-radius) !important; }
+
+.circular {
+ border-radius: 50% !important; }
+
+.shadowed {
+ box-shadow: var(--generic-box-shadow) !important; }
+
+.responsive-margin {
+ margin: calc(var(--universal-margin) / 4) !important; }
+ @media screen and (min-width: 500px) {
+ .responsive-margin {
+ margin: calc(var(--universal-margin) / 2) !important; } }
+ @media screen and (min-width: 1280px) {
+ .responsive-margin {
+ margin: var(--universal-margin) !important; } }
+
+.responsive-padding {
+ padding: calc(var(--universal-padding) / 4) !important; }
+ @media screen and (min-width: 500px) {
+ .responsive-padding {
+ padding: calc(var(--universal-padding) / 2) !important; } }
+ @media screen and (min-width: 1280px) {
+ .responsive-padding {
+ padding: var(--universal-padding) !important; } }
+
+@media screen and (max-width: 499px) {
+ .hidden-sm {
+ display: none !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+ .hidden-md {
+ display: none !important; } }
+@media screen and (min-width: 1280px) {
+ .hidden-lg {
+ display: none !important; } }
+@media screen and (max-width: 499px) {
+ .visually-hidden-sm {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+ .visually-hidden-md {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+@media screen and (min-width: 1280px) {
+ .visually-hidden-lg {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+
+/*# sourceMappingURL=mini-custom.css.map */
+
+img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; }
+img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;}
+
+.figure {
+ display: block;
+ margin-left: auto;
+ margin-right: auto;
+ text-align: center;
+}
\ No newline at end of file
diff --git a/system/Drivers/CMSIS/Device/ST/STM32U3xx/_htmresc/st_logo_2020.png b/system/Drivers/CMSIS/Device/ST/STM32U3xx/_htmresc/st_logo_2020.png
new file mode 100644
index 0000000000..d6cebb5ac7
Binary files /dev/null and b/system/Drivers/CMSIS/Device/ST/STM32U3xx/_htmresc/st_logo_2020.png differ
diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
index 79fb3b833e..9c4aa19e70 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
+++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
@@ -17,6 +17,7 @@
* STM32L5: 1.0.6
* STM32MP1: 1.7.0
* STM32U0: 1.2.0
+ * STM32U3: 1.1.0
* STM32U5: 1.4.1
* STM32WB: 1.12.2
* STM32WBA: 1.5.0
diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
new file mode 100644
index 0000000000..502b792e72
--- /dev/null
+++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -0,0 +1,4421 @@
+/**
+ ******************************************************************************
+ * @file stm32_hal_legacy.h
+ * @author MCD Application Team
+ * @brief This file contains aliases definition for the STM32Cube HAL constants
+ * macros and functions maintained for legacy purpose.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_HAL_LEGACY
+#define STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define AES_FLAG_RDERR CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
+#if defined(STM32H7) || defined(STM32MP1)
+#define CRYP_DATATYPE_32B CRYP_NO_SWAP
+#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
+#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
+#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
+#endif /* STM32H7 || STM32MP1 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP ADC_REGULAR_GROUP
+#define INJECTED_GROUP ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT ADC_AWD_EVENT
+#define AWD1_EVENT ADC_AWD1_EVENT
+#define AWD2_EVENT ADC_AWD2_EVENT
+#define AWD3_EVENT ADC_AWD3_EVENT
+#define OVR_EVENT ADC_OVR_EVENT
+#define JQOVF_EVENT ADC_JQOVF_EVENT
+#define ALL_CHANNELS ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
+
+#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
+
+#if defined(STM32H7)
+#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
+#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
+#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
+#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
+#endif /* STM32U5 */
+
+#if defined(STM32H5)
+#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE
+#endif /* STM32H5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
+ input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
+#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
+#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
+#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
+
+#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
+#if defined(STM32L0)
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
+/* to the second dedicated IO (only for COMP2). */
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
+#else
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
+#endif
+#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
+/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
+
+#if defined(STM32U5)
+#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+#if defined(STM32U5)
+#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
+#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
+#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Aliases CRC API aliases
+ * @{
+ */
+#if defined(STM32H5) || defined(STM32C0)
+#else
+#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
+ inter STM32 series compatibility */
+#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
+ inter STM32 series compatibility */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define DAC1_CHANNEL_1 DAC_CHANNEL_1
+#define DAC1_CHANNEL_2 DAC_CHANNEL_2
+#define DAC2_CHANNEL_1 DAC_CHANNEL_1
+#define DAC_WAVE_NONE 0x00000000U
+#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
+#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
+
+#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
+#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
+#endif
+
+#if defined(STM32U5)
+#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
+#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
+#endif
+
+#if defined(STM32H5)
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
+ defined(STM32F4) || defined(STM32G4)
+#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
+#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+#if defined(STM32L4)
+
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
+ defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
+#endif
+
+#endif /* STM32L4 */
+
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
+#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
+#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
+
+#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
+#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
+#endif
+
+#if defined(STM32H7)
+
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+
+#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
+
+#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
+#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5)
+#define PAGESIZE FLASH_PAGE_SIZE
+#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */
+#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW OB_IWDG_SW
+#define OB_WDG_HW OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
+#if defined(STM32G0) || defined(STM32C0)
+#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
+#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
+#else
+#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
+#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
+#endif
+#if defined(STM32H7)
+#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
+#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
+#if defined(STM32H7RS)
+#define FLASH_OPTKEY1 FLASH_OPT_KEY1
+#define FLASH_OPTKEY2 FLASH_OPT_KEY2
+#endif /* STM32H7RS */
+#if defined(STM32U5)
+#define OB_USER_nRST_STOP OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
+#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0
+#define OB_USER_nBOOT0 OB_USER_NBOOT0
+#define OB_nBOOT0_RESET OB_NBOOT0_RESET
+#define OB_nBOOT0_SET OB_NBOOT0_SET
+#define OB_USER_SRAM134_RST OB_USER_SRAM_RST
+#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
+#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
+#endif /* STM32U5 */
+#if defined(STM32U0)
+#define OB_USER_nRST_STOP OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
+#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
+#define OB_USER_nBOOT0 OB_USER_NBOOT0
+#define OB_USER_nBOOT1 OB_USER_NBOOT1
+#define OB_nBOOT0_RESET OB_NBOOT0_RESET
+#define OB_nBOOT0_SET OB_NBOOT0_SET
+#endif /* STM32U0 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32H7)
+#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
+#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
+#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
+#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+#endif /* STM32H7 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
+
+#if defined(STM32U5)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection
+#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection
+
+#endif /* STM32U5 */
+
+#if defined(STM32H5)
+#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
+#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
+#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
+#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
+#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
+#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
+
+#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
+#define SYSCFG_BREAK_PVD SBS_BREAK_PVD
+#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
+#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
+
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
+
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
+
+#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
+#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
+#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
+#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
+
+#define SYSCFG_ETH_MII SBS_ETH_MII
+#define SYSCFG_ETH_RMII SBS_ETH_RMII
+#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
+
+#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
+#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
+#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
+
+#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
+
+#define SYSCFG_MPU_NSEC SBS_MPU_NSEC
+#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SYSCFG_SAU SBS_SAU
+#define SYSCFG_MPU_SEC SBS_MPU_SEC
+#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
+#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
+#else
+#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
+#endif /* __ARM_FEATURE_CMSE */
+
+#define SYSCFG_CLK SBS_CLK
+#define SYSCFG_CLASSB SBS_CLASSB
+#define SYSCFG_FPU SBS_FPU
+#define SYSCFG_ALL SBS_ALL
+
+#define SYSCFG_SEC SBS_SEC
+#define SYSCFG_NSEC SBS_NSEC
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
+
+#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
+#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
+#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
+
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
+
+#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS
+#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
+
+#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
+#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
+#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
+#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
+#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
+#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
+#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
+
+#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
+#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
+#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
+#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
+#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster
+#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
+
+#define HAL_SYSCFG_Lock HAL_SBS_Lock
+#define HAL_SYSCFG_GetLock HAL_SBS_GetLock
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
+#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
+#endif /* __ARM_FEATURE_CMSE */
+
+#endif /* STM32H5 */
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+ * @{
+ */
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
+#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define GET_GPIO_SOURCE GPIO_GET_INDEX
+#define GET_GPIO_INDEX GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32H7)
+#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
+#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
+#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
+#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
+#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
+#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
+
+#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
+ defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
+ STM32H757xx */
+#endif /* STM32H7 */
+
+#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
+ defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
+
+#if defined(STM32L1)
+#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F0 || STM32F3 || STM32F1 */
+
+#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
+
+#if defined(STM32U5) || defined(STM32H5)
+#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
+#endif /* STM32U5 || STM32H5 */
+#if defined(STM32U5)
+#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
+#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
+#endif /* STM32U5 */
+
+#if defined(STM32WBA)
+#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
+#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
+#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO1 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO2 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO3 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO4 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO5 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO6 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO7 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO8 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO9 GPIO_AF11_RF
+#endif /* STM32WBA */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32U5)
+#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
+#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
+#endif /* STM32U5 */
+#if defined(STM32H5)
+#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1
+#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC
+#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB
+#endif /* STM32H5 */
+#if defined(STM32H5) || defined(STM32U5)
+#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX
+#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
+#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED
+#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED
+#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC
+#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC
+#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV
+#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV
+#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF
+#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON
+#endif /* STM32H5 || STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
+
+#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7)
+#define HRTIMInterruptResquests HRTIMInterruptRequests
+#endif /* STM32F3 || STM32G4 || STM32H7 */
+
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
+#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
+#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
+#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
+#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+ */
+#define HRTIM_EVENTSRC_1 (0x00000000U)
+#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+ */
+#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
+#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+#endif /* STM32F3 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
+ defined(STM32L1) || defined(STM32F7)
+#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define KR_KEY_RELOAD IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE IWDG_KEY_ENABLE
+#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
+/**
+ * @}
+ */
+
+#if defined(STM32U5)
+#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
+#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
+#define LPTIM_CHANNEL_ALL 0x00000000U
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
+#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
+#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
+#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
+
+#define NAND_AddressTypedef NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE NOR_WRITE
+#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
+#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
+#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
+#endif
+
+#if defined(STM32L4) || defined(STM32L5)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
+#elif defined(STM32G4)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
+
+#if defined(STM32H7)
+#define I2S_IT_TXE I2S_IT_TXP
+#define I2S_IT_RXNE I2S_IT_RXP
+
+#define I2S_FLAG_TXE I2S_FLAG_TXP
+#define I2S_FLAG_RXNE I2S_FLAG_RXP
+#endif
+
+#if defined(STM32F7)
+#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA ATA_DATA
+#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD ATA_CARD_HEAD
+#define CF_STATUS_CMD ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FORMAT_BIN RTC_FORMAT_BIN
+#define FORMAT_BCD RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+
+#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6)
+#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
+#endif /* STM32H5 || STM32H7RS || STM32N6 */
+
+#if defined(STM32WBA)
+#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2
+#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK
+#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE
+#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
+#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM
+#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
+#endif /* STM32WBA */
+
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
+#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
+#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
+
+#if defined(STM32F7) || defined(STM32WB)
+#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
+#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
+#endif /* STM32F7 || STM32WB */
+
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
+#endif /* STM32H7 */
+
+#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB)
+#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
+#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
+
+#if defined(STM32H7)
+
+#define SPI_FLAG_TXE SPI_FLAG_TXP
+#define SPI_FLAG_RXNE SPI_FLAG_RXP
+
+#define SPI_IT_TXE SPI_IT_TXP
+#define SPI_IT_RXNE SPI_IT_RXP
+
+#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
+#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
+#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
+#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
+
+#endif /* STM32H7 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1 TIM_DMABASE_CR1
+#define TIM_DMABase_CR2 TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER TIM_DMABASE_DIER
+#define TIM_DMABase_SR TIM_DMABASE_SR
+#define TIM_DMABase_EGR TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER TIM_DMABASE_CCER
+#define TIM_DMABase_CNT TIM_DMABASE_CNT
+#define TIM_DMABase_PSC TIM_DMABASE_PSC
+#define TIM_DMABase_ARR TIM_DMABASE_ARR
+#define TIM_DMABase_RCR TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1 TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2 TIM_DMABASE_OR2
+#define TIM_DMABase_OR3 TIM_DMABASE_OR3
+#define TIM_DMABase_OR TIM_DMABASE_OR
+
+#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
+
+#if defined(STM32L0)
+#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
+#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
+#endif
+
+#if defined(STM32F3)
+#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
+#endif
+
+#if defined(STM32H7)
+#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
+#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
+#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
+#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
+#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
+#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
+#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
+#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
+#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
+#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
+#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
+#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
+#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
+#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
+#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
+#endif
+
+#if defined(STM32U5) || defined(STM32MP2)
+#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
+#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
+
+#define __DIV_LPUART UART_DIV_LPUART
+
+#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED USART_NACK_ENABLE
+#define USARTNACK_DISABLED USART_NACK_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CFR_BASE WWDG_CFR_BASE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define VLAN_TAG ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR 0x00000100U
+#define ETH_MMCRIR 0x00000104U
+#define ETH_MMCTIR 0x00000108U
+#define ETH_MMCRIMR 0x0000010CU
+#define ETH_MMCTIMR 0x00000110U
+#define ETH_MMCTGFSCCR 0x0000014CU
+#define ETH_MMCTGFMSCCR 0x00000150U
+#define ETH_MMCTGFCR 0x00000168U
+#define ETH_MMCRFCECR 0x00000194U
+#define ETH_MMCRFAECR 0x00000198U
+#define ETH_MMCRGUFCR 0x000001C4U
+
+#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
+ the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
+ MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus
+ or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
+ of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
+ transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
+ frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
+ de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
+ activate threshold */
+#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
+#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
+ (or time-stamp) */
+#endif
+#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
+ status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
+
+#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
+
+/**
+ * @}
+ */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+ || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+ || defined(STM32H7)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
+#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
+#define CM_RGB888 DMA2D_INPUT_RGB888
+#define CM_RGB565 DMA2D_INPUT_RGB565
+#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
+#define CM_L8 DMA2D_INPUT_L8
+#define CM_AL44 DMA2D_INPUT_AL44
+#define CM_AL88 DMA2D_INPUT_AL88
+#define CM_L4 DMA2D_INPUT_L4
+#define CM_A8 DMA2D_INPUT_A8
+#define CM_A4 DMA2D_INPUT_A4
+/**
+ * @}
+ */
+#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+ || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+ || defined(STM32H7) || defined(STM32U5)
+/** @defgroup DMA2D_Aliases DMA2D API Aliases
+ * @{
+ */
+#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
+ for compatibility with legacy code */
+/**
+ * @}
+ */
+
+#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32U5)
+#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr
+#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT
+#endif /* STM32U5 */
+
+/**
+ * @}
+ */
+
+#if !defined(STM32F2)
+/** @defgroup HASH_alias HASH API alias
+ * @{
+ */
+#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
+/**
+ *
+ * @}
+ */
+#endif /* STM32F2 */
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
+ )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
+ HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
+#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
+ )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \
+ HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
+ defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
+#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
+#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \
+ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
+ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
+ defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
+ defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
+#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
+#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
+#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
+#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
+ STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
+ defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
+#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
+#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
+#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+
+#if defined(STM32F4)
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
+#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
+#endif /* STM32F4 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
+#endif
+#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
+#define PMODE_BIT_NUMBER VOS_BIT_NUMBER
+#define CR_PMODE_BB CR_VOS_BB
+
+#define DBP_BitNumber DBP_BIT_NUMBER
+#define PVDE_BitNumber PVDE_BIT_NUMBER
+#define PMODE_BitNumber PMODE_BIT_NUMBER
+#define EWUP_BitNumber EWUP_BIT_NUMBER
+#define FPDS_BitNumber FPDS_BIT_NUMBER
+#define ODEN_BitNumber ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
+#define BRE_BitNumber BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
+
+#if defined (STM32U5)
+#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
+#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
+#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
+#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
+#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
+#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
+#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
+#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
+#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
+#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
+#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
+#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
+#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
+#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
+#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
+
+#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
+#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
+#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
+#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
+#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
+#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
+#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
+#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
+#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
+#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
+#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
+#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
+#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
+#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
+
+#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
+
+#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
+#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
+#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
+#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
+#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
+#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
+#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
+#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
+#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
+#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
+#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
+#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
+#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
+#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
+
+#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP
+#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP
+#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP
+#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP
+#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP
+#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP
+#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP
+#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP
+#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP
+
+
+#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
+#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
+#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
+#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
+#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
+#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
+#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
+#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
+#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP
+
+
+#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
+#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
+#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
+
+#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
+#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
+#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
+#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
+#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
+#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN
+
+#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
+#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
+#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
+#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
+#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
+#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError TIM_DMAError
+#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
+ defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
+#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
+#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
+#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
+#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
+#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define AES_IT_CC CRYP_IT_CC
+#define AES_IT_ERR CRYP_IT_ERR
+#define AES_FLAG_CCF CRYP_FLAG_CCF
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
+
+#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __ADC_ENABLE __HAL_ADC_ENABLE
+#define __ADC_DISABLE __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
+#define __ADC_IS_ENABLED ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1 ADC_SQR1
+#define __HAL_ADC_SMPR1 ADC_SMPR1
+#define __HAL_ADC_SMPR2 ADC_SMPR2
+#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
+#define __HAL_ADC_JSQR ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#if defined(STM32H7)
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#else
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#endif /* STM32H7 */
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32F3)
+#define COMP_START __HAL_COMP_ENABLE
+#define COMP_STOP __HAL_COMP_DISABLE
+#define COMP_LOCK __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
+ defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+#endif
+#if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+#endif
+#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+#endif
+#if defined(STM32F373xC) ||defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
+
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro */
+/* is COMP_FLAG_LOCK. */
+/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
+/* argument. */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
+/**
+ * @}
+ */
+
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
+ done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
+ done into HAL_COMP_Init() */
+/**
+ * @}
+ */
+#endif
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+ ((WAVE) == DAC_WAVE_NOISE)|| \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_WRPAREA IS_OB_WRPAREA
+#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE IS_FLASH_TYPEERASE
+#define IS_NBSECTORS IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
+#else
+#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
+#endif /* STM32F1 */
+#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
+#define __HAL_I2C_SPEED I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
+
+#if defined(STM32H7)
+#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __IRDA_DISABLE __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
+ HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
+ } while(0)
+#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
+ HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
+ } while(0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+ * @{
+ */
+
+#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
+ HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#if defined(STM32C0)
+#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
+#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
+#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
+#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
+#endif /* STM32C0 */
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+
+#if defined(STM32H7)
+#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
+#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
+
+#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
+
+
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2
+#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2
+#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2
+#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2
+#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2
+#endif
+
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+
+#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
+#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
+#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32L1)
+#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#endif /* STM32L1 */
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
+#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14 RCC_IT_HSI14RDY
+
+#define RCC_IT_CSSLSE RCC_IT_LSECSS
+#define RCC_IT_CSSHSE RCC_IT_CSS
+
+#define RCC_PLLMUL_3 RCC_PLL_MUL3
+#define RCC_PLLMUL_4 RCC_PLL_MUL4
+#define RCC_PLLMUL_6 RCC_PLL_MUL6
+#define RCC_PLLMUL_8 RCC_PLL_MUL8
+#define RCC_PLLMUL_12 RCC_PLL_MUL12
+#define RCC_PLLMUL_16 RCC_PLL_MUL16
+#define RCC_PLLMUL_24 RCC_PLL_MUL24
+#define RCC_PLLMUL_32 RCC_PLL_MUL32
+#define RCC_PLLMUL_48 RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2 RCC_PLL_DIV2
+#define RCC_PLLDIV_3 RCC_PLL_DIV3
+#define RCC_PLLDIV_4 RCC_PLL_DIV4
+
+#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV RCC_MCODIV_1
+#define RCC_MCO_DIV1 RCC_MCODIV_1
+#define RCC_MCO_DIV2 RCC_MCODIV_2
+#define RCC_MCO_DIV4 RCC_MCODIV_4
+#define RCC_MCO_DIV8 RCC_MCODIV_8
+#define RCC_MCO_DIV16 RCC_MCODIV_16
+#define RCC_MCO_DIV32 RCC_MCODIV_32
+#define RCC_MCO_DIV64 RCC_MCODIV_64
+#define RCC_MCO_DIV128 RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#if defined(STM32U0)
+#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
+#endif
+
+
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
+ defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \
+ defined(STM32U0)
+#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
+#else
+#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
+#endif
+
+#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB RCC_CR_HSION_BB
+#define CR_CSSON_BB RCC_CR_CSSON_BB
+#define CR_PLLON_BB RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB RCC_CR_MSION_BB
+#define CSR_LSION_BB RCC_CSR_LSION_BB
+#define CSR_LSEON_BB RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB RCC_CR_HSEON_BB
+#define CSR_RMVF_BB RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
+
+#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
+#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
+#if !defined(STM32U0)
+#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
+#endif
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
+#if defined(STM32U5)
+#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
+#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
+#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
+#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
+#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
+#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE
+#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE
+#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE
+#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE
+#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
+#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
+#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
+#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
+#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
+#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
+#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
+#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
+#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
+#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
+#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
+#endif /* STM32U5 */
+
+#if defined(STM32H5)
+#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
+
+#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE
+#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI
+#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI
+#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE
+#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0
+#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1
+#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2
+#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3
+#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE
+#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM
+
+#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE
+#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE
+#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE
+#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE
+#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE
+#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE
+#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE
+#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE
+#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE
+#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE
+
+#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE
+#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE
+#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE
+#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE
+#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG
+#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG
+#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG
+#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE
+#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE
+#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE
+#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE
+#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE
+#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE
+#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE
+#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE
+#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE
+#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE
+#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE
+#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE
+#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE
+#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
+
+#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0
+#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1
+#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2
+#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3
+
+#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE
+#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM
+
+#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE
+#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI
+#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI
+#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE
+
+#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0
+#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1
+#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2
+#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3
+
+#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE
+#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM
+
+#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE
+#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI
+#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI
+#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE
+
+
+#endif /* STM32H5 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
+ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
+ defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || \
+ defined (STM32U0) || defined (STM32U3)
+#else
+#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
+#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif /* STM32F1 */
+
+#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
+ defined (STM32H7) || \
+ defined (STM32L0) || defined (STM32L1) || \
+ defined (STM32WB)
+#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
+#endif
+
+#define IS_ALARM IS_RTC_ALARM
+#define IS_ALARM_MASK IS_RTC_ALARM_MASK
+#define IS_TAMPER IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+
+#if defined (STM32H5)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
+#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE
+#endif /* STM32H5 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
+
+#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
+#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
+#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
+#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
+
+#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
+#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
+#endif
+
+#if defined(STM32F4) || defined(STM32F2)
+#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
+#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
+#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
+#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
+#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
+#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
+#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
+#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
+#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
+#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
+#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
+#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
+#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
+#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
+#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
+#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
+#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
+#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
+#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define SDMMC1_IRQn SDIO_IRQn
+#define SDMMC1_IRQHandler SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
+#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
+#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
+#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
+#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
+#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
+#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
+#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
+#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
+#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
+#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
+#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
+#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
+#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
+#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
+#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
+#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define SDIO_IRQn SDMMC1_IRQn
+#define SDIO_IRQHandler SDMMC1_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
+#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
+#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
+#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
+#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
+#endif
+
+#if defined(STM32H7) || defined(STM32L5)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
+#define __USART_ENABLE __HAL_USART_ENABLE
+#define __USART_DISABLE __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
+#define USART_OVERSAMPLING_16 0x00000000U
+#define USART_OVERSAMPLING_8 USART_CR1_OVER8
+
+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
+ ((__SAMPLING__) == USART_OVERSAMPLING_8))
+#endif /* STM32F0 || STM32F3 || STM32F7 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
+#if defined(STM32U5)
+#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM
+#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT
+#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0
+#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM
+#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
+
+#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
+
+#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
+#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
+#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
+#endif /* STM32L4 || STM32F4 || STM32F7 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32F7)
+#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
+#endif /* STM32F7 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_HAL_LEGACY */
diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32_assert_template.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32_assert_template.h
new file mode 100644
index 0000000000..21a92a13b3
--- /dev/null
+++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32_assert_template.h
@@ -0,0 +1,53 @@
+/**
+ ******************************************************************************
+ * @file stm32_assert.h
+ * @author MCD Application Team
+ * @brief STM32 assert template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32_assert.h.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal.h
new file mode 100644
index 0000000000..e3281404c3
--- /dev/null
+++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal.h
@@ -0,0 +1,684 @@
+/**
+ ******************************************************************************
+ * @file stm32u3xx_hal.h
+ * @author MCD Application Team
+ * @brief This file contains all the functions prototypes for the HAL
+ * module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32U3xx_HAL_H
+#define __STM32U3xx_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u3xx_hal_conf.h"
+
+/** @addtogroup STM32U3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HAL
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HAL_Exported_Types HAL Exported Types
+ * @{
+ */
+
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+ * @{
+ */
+typedef enum
+{
+ HAL_TICK_FREQ_10HZ = 100U,
+ HAL_TICK_FREQ_100HZ = 10U,
+ HAL_TICK_FREQ_1KHZ = 1U,
+ HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported variables --------------------------------------------------------*/
+/** @defgroup HAL_Exported_Variables HAL Exported Variables
+ * @{
+ */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/**
+ * @brief STM32U3xx HAL Driver version number
+ */
+#define __STM32U3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
+#define __STM32U3xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
+#define __STM32U3xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
+#define __STM32U3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32U3xx_HAL_VERSION ((__STM32U3xx_HAL_VERSION_MAIN << 24U)\
+ |(__STM32U3xx_HAL_VERSION_SUB1 << 16U)\
+ |(__STM32U3xx_HAL_VERSION_SUB2 << 8U )\
+ |(__STM32U3xx_HAL_VERSION_RC))
+
+
+/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
+ * @{
+ */
+
+/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
+ * @{
+ */
+#define SYSCFG_IT_FPU_IOC SYSCFG_FPUIMR_FPU_IOIE /*!< Floating Point Unit Invalid operation Interrupt */
+#define SYSCFG_IT_FPU_DZC SYSCFG_FPUIMR_FPU_DZIE /*!< Floating Point Unit Divide-by-zero Interrupt */
+#define SYSCFG_IT_FPU_UFC SYSCFG_FPUIMR_FPU_UFIE /*!< Floating Point Unit Underflow Interrupt */
+#define SYSCFG_IT_FPU_OFC SYSCFG_FPUIMR_FPU_OFIE /*!< Floating Point Unit Overflow Interrupt */
+#define SYSCFG_IT_FPU_IDC SYSCFG_FPUIMR_FPU_IDIE /*!< Floating Point Unit Input denormal Interrupt */
+#define SYSCFG_IT_FPU_IXC SYSCFG_FPUIMR_FPU_IXIE /*!< Floating Point Unit Inexact Interrupt */
+#define SYSCFG_IT_FPU_ALL (SYSCFG_IT_FPU_IOC| \
+ SYSCFG_IT_FPU_DZC| \
+ SYSCFG_IT_FPU_UFC| \
+ SYSCFG_IT_FPU_OFC| \
+ SYSCFG_IT_FPU_IDC| \
+ SYSCFG_IT_FPU_IXC) /*!< All */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_Compensation_Cell_Selection Compensation Cell Selection
+ * @{
+ */
+#define SYSCFG_IO_VDD_CELL SYSCFG_CCCSR_EN1 /*!< Compensation cell for the I/O supplied by VDD */
+#define SYSCFG_IO_VDDIO2_CELL SYSCFG_CCCSR_EN2 /*!< Compensation cell for the I/O supplied by VDDIO2 */
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_IO_Compensation_Code_Config IO Compensation Code config
+ * @{
+ */
+#define SYSCFG_IO_CELL_CODE 0U /*!< Code from the cell */
+#define SYSCFG_IO_REGISTER_CODE 1U /*!< Code from the values in the cell code register */
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_HAL_EC_IR_MOD SYSCFG IR Modulation
+ * @{
+ */
+#define SYSCFG_IR_MOD_TIM16 0U /*!< TIM16 is selected as IR Modulation envelope source */
+#define SYSCFG_IR_MOD_USART1 SYSCFG_CFGR1_IR_MOD_0 /*!< USART1 is selected as IR Modulation envelope source */
+#define SYSCFG_IR_MOD_UART4 SYSCFG_CFGR1_IR_MOD_1 /*!< UART4 is selected as IR Modulation envelope source */
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_HAL_EC_IR_OUTPOL SYSCFG IR Output Polarity
+ * @{
+ */
+#define SYSCFG_IR_OUTPUTPOL_NONINVERTED 0U /*!< Output of IR (IROut) non-inverted */
+#define SYSCFG_IR_OUTPUTPOL_INVERTED SYSCFG_CFGR1_IR_POL /*!< Output of IR (IROut) inverted */
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
+ * @{
+ */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000)
+ /*!< Voltage reference scale 0 (VREF_OUT1) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0
+ /*!< Voltage reference scale 1 (VREF_OUT2) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1
+ /*!< Voltage reference scale 2 (VREF_OUT3) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1)
+ /*!< Voltage reference scale 3 (VREF_OUT4) */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
+ * @{
+ */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to
+ Voltage reference buffer output */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
+ * @{
+ */
+
+/** @brief Fast-mode Plus driving capability on a specific GPIO
+ */
+#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
+#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
+#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
+#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
+#define SYSCFG_FASTMODEPLUS_ALL (SYSCFG_FASTMODEPLUS_PB6| \
+ SYSCFG_FASTMODEPLUS_PB7| \
+ SYSCFG_FASTMODEPLUS_PB8| \
+ SYSCFG_FASTMODEPLUS_PB9) /*!< All */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_Lock_items SYSCFG Lock items
+ * @brief SYSCFG items to set lock on
+ * @{
+ */
+#define SYSCFG_MPU_NSEC SYSCFG_CNSLCKR_LOCKNSMPU
+ /*!< Non-secure MPU lock (privileged secure or non-secure only) */
+#define SYSCFG_VTOR_NSEC SYSCFG_CNSLCKR_LOCKNSVTOR
+ /*!< Non-secure VTOR lock (privileged secure or non-secure only) */
+#if defined (CPU_IN_SECURE_STATE)
+#define SYSCFG_SAU (SYSCFG_CSLCKR_LOCKSAU << 16U)
+ /*!< SAU lock (privileged secure code only) */
+#define SYSCFG_MPU_SEC (SYSCFG_CSLCKR_LOCKSMPU << 16U)
+ /*!< Secure MPU lock (privileged secure code only) */
+#define SYSCFG_VTOR_AIRCR_SEC (SYSCFG_CSLCKR_LOCKSVTAIRCR << 16U)
+ /*!< VTOR_S and AIRCR lock (privileged secure code only) */
+#define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC|SYSCFG_SAU|SYSCFG_MPU_SEC|SYSCFG_VTOR_AIRCR_SEC)
+ /*!< All */
+#else
+#define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC)
+ /*!< All (privileged secure or non-secure only) */
+#endif /* CPU_IN_SECURE_STATE */
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_Attributes_items SYSCFG Attributes items
+ * @brief SYSCFG items to configure secure or non-secure attributes on
+ * @{
+ */
+#define SYSCFG_CLK SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock control */
+#define SYSCFG_CLASSB SYSCFG_SECCFGR_CLASSBSEC /*!< Class B */
+#define SYSCFG_FPU SYSCFG_SECCFGR_FPUSEC /*!< FPU */
+#define SYSCFG_ALL (SYSCFG_CLK | SYSCFG_CLASSB | SYSCFG_FPU) /*!< All */
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_attributes SYSCFG attributes
+ * @brief SYSCFG secure or non-secure attributes
+ * @{
+ */
+#define SYSCFG_SEC 0x00000001U /*!< Secure attribute */
+#define SYSCFG_NSEC 0x00000000U /*!< Non-secure attribute */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
+ * @{
+ */
+
+/** @brief Freeze/Unfreeze Peripherals in Debug mode
+ */
+#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_I3C1_STOP)
+#define __HAL_DBGMCU_FREEZE_I3C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I3C1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I3C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I3C1_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_I3C1_STOP */
+
+#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
+#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
+#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
+#endif /* DBGMCU_APB1FZR1_DBG_RTC_STOP */
+
+#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
+#endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */
+
+#if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP)
+#endif /* DBGMCU_APB2FZR_DBG_TIM1_STOP */
+
+#if defined(DBGMCU_APB2FZR_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP)
+#endif /* DBGMCU_APB2FZR_DBG_TIM15_STOP */
+
+#if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP)
+#endif /* DBGMCU_APB2FZR_DBG_TIM16_STOP */
+
+#if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP)
+#endif /* DBGMCU_APB2FZR_DBG_TIM17_STOP */
+
+#if defined(DBGMCU_APB2FZR_DBG_I3C2_STOP)
+#define __HAL_DBGMCU_FREEZE_I3C2() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_I3C2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I3C2() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_I3C2_STOP)
+#endif /* DBGMCU_APB2FZR_DBG_I3C2_STOP */
+
+#if defined(DBGMCU_APB3FZR_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP)
+#endif /* DBGMCU_APB3FZR_DBG_I2C3_STOP */
+
+#if defined(DBGMCU_APB3FZR_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP)
+#endif /* DBGMCU_APB3FZR_DBG_LPTIM1_STOP */
+
+#if defined(DBGMCU_APB3FZR_DBG_LPTIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP)
+#endif /* DBGMCU_APB3FZR_DBG_LPTIM3_STOP */
+
+#if defined(DBGMCU_APB3FZR_DBG_LPTIM4_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP)
+#endif /* DBGMCU_APB3FZR_DBG_LPTIM4_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA0_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA0_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA0_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA0_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA3_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA3_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA3_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA4_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA4_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA4_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA5_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA5_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA5_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA6_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA6_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA6_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA7_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA7_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA7_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA8_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA8_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA8_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA8_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA9_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA9_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA9_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA9_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA10_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA10_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA10_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA10_STOP */
+
+#if defined(DBGMCU_AHB1FZR_DBG_GPDMA11_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA11_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA11_STOP)
+#endif /* DBGMCU_AHB1FZR_DBG_GPDMA11_STOP */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
+ * @{
+ */
+
+/** @brief Floating Point Unit interrupt enable/disable macros
+ * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts
+ */
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
+ SET_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\
+ }while(0)
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
+ CLEAR_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\
+ }while(0)
+
+/** @brief SYSCFG Break ECC lock.
+ * Enable and lock the connection of Flash ECC double error connection to TIM1/15/16/17 Break input.
+ * @note The selected configuration is locked and can be unlocked only by system reset.
+ */
+#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
+
+/** @brief SYSCFG Break Cortex-M33 Lockup lock.
+ * Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input.
+ * @note The selected configuration is locked and can be unlocked only by system reset.
+ */
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
+
+/** @brief SYSCFG Break PVD lock.
+ * Enable and lock the PVD connection to Timer1/15/16/17 Break input, as well as the PVDE and PVDLS[2:0] in
+ * the PWR_SVMCR register.
+ * @note The selected configuration is locked and can be unlocked only by system reset.
+ */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
+
+/** @brief SYSCFG Break SRAM2 parity lock.
+ * Enable and lock the SRAM2 parity error signal connection to TIM1/15/16/17 Break input.
+ * @note The selected configuration is locked and can be unlocked by system reset.
+ */
+#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
+
+/** @brief Fast-mode Plus driving capability enable/disable macros
+ * @param __FASTMODEPLUS__: This parameter can be a value of :
+ * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
+ * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
+ * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
+ * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
+ */
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \
+ do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+ SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+ }while(0)
+
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \
+ do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+ CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+ }while(0)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
+ * @{
+ */
+#define IS_SYSCFG_IR_MODULATION(__MODULATION__) (((__MODULATION__) == SYSCFG_IR_MOD_TIM16) || \
+ ((__MODULATION__) == SYSCFG_IR_MOD_USART1) || \
+ ((__MODULATION__) == SYSCFG_IR_MOD_UART4))
+
+#define IS_SYSCFG_IR_OUTPUTPOL(__OUTPUTPOL__) (((__OUTPUTPOL__) == SYSCFG_IR_OUTPUTPOL_NONINVERTED) || \
+ ((__OUTPUTPOL__) == SYSCFG_IR_OUTPUTPOL_INVERTED))
+
+#define IS_SYSCFG_IO_COMPENSATION_CODE(__VALUE__) (((__VALUE__) == SYSCFG_IO_CELL_CODE) || \
+ ((__VALUE__) == SYSCFG_IO_REGISTER_CODE))
+
+#define IS_SYSCFG_IO_COMPENSATION_CELL_PMOS_VALUE(__VALUE__) (((__VALUE__) < 16U))
+#define IS_SYSCFG_IO_COMPENSATION_CELL_NMOS_VALUE(__VALUE__) (((__VALUE__) < 16U))
+
+#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_ALL) != 0x00U) && \
+ (((__INTERRUPT__) & ~SYSCFG_IT_FPU_ALL) == 0x00U))
+
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
+ ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
+ ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \
+ ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3))
+
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
+ ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
+
+#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
+
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_ALL) != 0x00U) && \
+ (((__PIN__) & ~SYSCFG_FASTMODEPLUS_ALL) == 0x00U))
+
+#define IS_SYSCFG_COMPENSATION_CELL(__CELL__) (((__CELL__) == SYSCFG_IO_VDD_CELL) || \
+ ((__CELL__) == SYSCFG_IO_VDDIO2_CELL))
+
+#if defined (CPU_IN_SECURE_STATE)
+
+#define IS_SYSCFG_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SYSCFG_SEC) ||\
+ ((__ATTRIBUTES__) == SYSCFG_NSEC))
+
+#define IS_SYSCFG_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SYSCFG_ALL) != 0x00U) && \
+ (((__ITEM__) & ~SYSCFG_ALL) == 0x00U))
+
+#endif /* CPU_IN_SECURE_STATE */
+
+#define IS_SYSCFG_SINGLE_ITEMS_ATTRIBUTES(__ITEM__) (((__ITEM__) == (SYSCFG_CLK)) || \
+ ((__ITEM__) == (SYSCFG_CLASSB)) || \
+ ((__ITEM__) == (SYSCFG_FPU)))
+
+#define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_LOCK_ALL) != 0x00U) && \
+ (((__ITEM__) & ~SYSCFG_LOCK_ALL) == 0x00U))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Private_Macros HAL Private Macros
+ * @{
+ */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
+ ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+ ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group2
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group3
+ * @{
+ */
+
+/* DBGMCU Peripheral Control functions *****************************************/
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group4
+ * @{
+ */
+
+/* SYSCFG Control functions ****************************************************/
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
+void HAL_SYSCFG_DisableVREFBUF(void);
+void HAL_SYSCFG_EnableIOAnalogBooster(void);
+void HAL_SYSCFG_DisableIOAnalogBooster(void);
+void HAL_SYSCFG_EnableIOAnalogSwitchVdd(void);
+void HAL_SYSCFG_DisableIOAnalogSwitchVdd(void);
+void HAL_SYSCFG_EnableCompensationCell(uint32_t Selection);
+void HAL_SYSCFG_DisableCompensationCell(uint32_t Selection);
+uint32_t HAL_SYSCFG_GetCompensationCellReadyStatus(uint32_t Selection);
+void HAL_SYSCFG_ConfigCompensationCell(uint32_t Selection,
+ uint32_t Code,
+ uint32_t NmosValue,
+ uint32_t PmosValue);
+HAL_StatusTypeDef HAL_SYSCFG_GetCompensationCell(uint32_t Selection,
+ uint32_t *pCode,
+ uint32_t *pNmosValue,
+ uint32_t *pPmosValue);
+void HAL_SYSCFG_ConfigIR(uint32_t Modulation, uint32_t OutputPol);
+HAL_StatusTypeDef HAL_SYSCFG_GetConfigIR(uint32_t *pModulation, uint32_t *pOutputPol);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group5
+ * @{
+ */
+
+/* SYSCFG Lock functions ********************************************/
+void HAL_SYSCFG_Lock(uint32_t Item);
+HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group6
+ * @{
+ */
+
+/* SYSCFG Attributes functions ********************************************/
+#if defined (CPU_IN_SECURE_STATE)
+void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes);
+#endif /* CPU_IN_SECURE_STATE */
+HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32U3xx_HAL_H */
diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_adc.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_adc.h
new file mode 100644
index 0000000000..04674112c2
--- /dev/null
+++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_adc.h
@@ -0,0 +1,2000 @@
+/**
+ ******************************************************************************
+ * @file stm32u3xx_hal_adc.h
+ * @author MCD Application Team
+ * @brief Header file of ADC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U3xx_HAL_ADC_H
+#define STM32U3xx_HAL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u3xx_hal_def.h"
+
+/* Include low level driver */
+#include "stm32u3xx_ll_adc.h"
+
+/** @addtogroup STM32U3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+ * @{
+ */
+
+/**
+ * @brief ADC group regular oversampling structure definition
+ */
+typedef struct
+{
+ uint32_t Ratio; /*!< Configures the oversampling ratio.
+ This parameter can be a value from 1 to 1024 */
+
+ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
+
+ uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
+
+ uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode.
+ The oversampling is either temporary stopped or reset upon an injected
+ sequence interruption.
+ If oversampling is enabled on both regular and injected groups,
+ this parameter is discarded and forced to setting
+ "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed
+ during injection sequence).
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
+
+} ADC_OversamplingTypeDef;
+
+/**
+ * @brief Structure definition of ADC instance and ADC group regular.
+ * @note ADC clock prescaler (init structure "ClockPrescaler" in other ADC IP versions FW drivers)
+ * is moved on RCC side on this STM32 series (rational: for feature "fixed trigger latency").
+ * Refer to RCC FW drivers to configure ADC clock prescaler.
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope entire ADC (affects ADC groups regular and injected): Resolution,
+ * GainCompensation, ScanConvMode, EOCSelection, LowPowerAutoWait.
+ * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode,
+ * NbrOfDiscConversion, ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun,
+ * OversamplingMode, Oversampling, SamplingMode.
+ * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled
+ * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling':
+ * ADC enabled without conversion on going on group regular.
+ * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going
+ * on groups regular and injected.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behavior in case of intended action to update another
+ * parameter (which fulfills the ADC state condition) on the fly).
+ */
+typedef struct
+{
+ uint32_t Resolution; /*!< Configure the ADC resolution.
+ This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
+
+ uint32_t GainCompensation; /*!< Specify the ADC gain compensation coefficient to be applied to ADC raw
+ conversion data, based on following formula:
+ DATA = DATA(raw) * (gain compensation coef) / 4096
+ 12 bit format, unsigned: 2 bits exponents / 12 bits mantissa
+ Gain step is 1/4096 = 0.000244
+ Gain range is 0.0000 to 3.999756
+ This parameter value can be:
+ - value "0": Gain compensation will be disabled and coefficient set to 0
+ - value in range [0x0001; 0x3FFF]: Gain compensation will enabled
+ and coefficient set to specified value */
+
+ uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected.
+ This parameter can be associated to parameter 'DiscontinuousConvMode'
+ to have main sequence subdivided in successive parts.
+ If disabled: Conversion is performed in single mode (one channel converted,
+ the one defined in rank 1).
+ Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion'
+ are discarded (equivalent to set to 1).
+ If enabled: Conversions are performed in sequence mode (multiple ranks defined
+ by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of
+ each channel in sequencer).
+ Scan direction is upward: from rank 1 to rank 'n'.
+ This parameter can be a value of @ref ADC_Scan_mode */
+
+ uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and
+ interruption: end of unitary conversion or end of sequence conversions.
+ This parameter can be a value of @ref ADC_EOCSelection. */
+
+ FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the
+ previous conversion (for ADC group regular) or previous sequence (for ADC group
+ injected) has been retrieved by user software, using function HAL_ADC_GetValue()
+ or HAL_ADCEx_InjectedGetValue().
+ This feature automatically adapts the frequency of ADC conversions triggers to
+ the speed of the system that reads the data. Moreover, this avoids risk of
+ overrun for low frequency applications.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(),
+ HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC
+ flag (by CPU to free the IRQ pending event or by DMA).
+ Auto wait will work but fort a very short time, discarding its intended
+ benefit (except specific case of high load of CPU or DMA transfers which
+ can justify usage of auto wait).
+ Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on,
+ when ADC conversion data is needed:
+ use HAL_ADC_PollForConversion() to ensure that conversion is completed and
+ HAL_ADC_GetValue() to retrieve conversion result and trig another
+ conversion start. (in case of usage of ADC group injected, use the
+ equivalent functions HAL_ADCExInjected_Start(),
+ HAL_ADCEx_InjectedGetValue(), ...). */
+
+ FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion)
+ or continuous mode for ADC group regular, after the first ADC conversion
+ start trigger occurred (software start or external trigger). This parameter
+ can be set to ENABLE or DISABLE. */
+
+ uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group
+ sequencer.
+ To use the regular group sequencer and convert several ranks,
+ parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16.
+ Note: This parameter must be modified when no conversion is on going on
+ regular group (ADC disabled, or ADC enabled without continuous mode
+ or external trigger that could launch a conversion). */
+
+ FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed
+ in Complete-sequence/Discontinuous-sequence (main sequence subdivided in
+ successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter
+ 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled.
+ If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence
+ of ADC group regular (parameter NbrOfConversion) will be subdivided.
+ If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+
+ uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion
+ start.
+ If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger
+ is used instead.
+ This parameter can be a value of @ref ADC_regular_external_trigger_source.
+ Caution: external trigger source is common to all ADC instances. */
+
+ uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular
+ conversion start.
+ If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
+ This parameter can be a value of @ref ADC_regular_external_trigger_edge */
+
+ uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion.
+ This parameter can be a value of @ref ADC_regular_sampling_mode */
+
+ uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA
+ (oneshot or circular), or stored in the DR register or
+ transferred to MDF register.
+ Note: In continuous mode, DMA must be configured in circular mode.
+ Otherwise an overrun will be triggered when DMA buffer maximum pointer
+ is reached.
+ This parameter can be a value of @ref ADC_ConversionDataManagement.
+ Note: This parameter must be modified when no conversion is on going on both
+ regular and injected groups (ADC disabled, or ADC enabled without
+ continuous mode or external trigger that could launch a conversion). */
+
+ uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
+ This parameter applies to ADC group regular only.
+ This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
+ Note: In case of overrun set to data preserved and usage with programming model
+ with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of
+ conversion flags, this induces the release of the preserved data.
+ If needed, this data can be saved in function HAL_ADC_ConvCpltCallback(),
+ placed in user program code (called before end of conversion flags clear).
+ Note: Error reporting with respect to the conversion mode:
+ - Usage with ADC conversion by polling for event or interruption:
+ Error is reported only if overrun is set to data preserved.
+ If overrun is set to data overwritten, user can willingly not read
+ all the converted data, this is not considered as an erroneous case.
+ - Usage with ADC conversion by DMA: Error is reported whatever overrun
+ setting (DMA is expected to process all data from data register). */
+
+ uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without
+ oversampling.
+ This parameter can be a value of @ref ADCEx_Left_Bit_Shift */
+
+ FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: This parameter can be modified only if there is no conversion
+ is ongoing on ADC groups regular and injected */
+
+ ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
+ Caution: this setting overwrites the previous oversampling configuration
+ if oversampling is already enabled. */
+
+} ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of ADC channel for regular group
+ * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
+ * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion
+ * on going on regular group.
+ * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on
+ * regular and injected groups.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behavior in case of intended action to update another
+ * parameter (which fulfills the ADC state condition) on the fly.
+ */
+typedef struct
+{
+ uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
+ Note: Depending on devices and ADC instances, some channels may not be available
+ on device package pins. Refer to device datasheet for channels
+ availability. */
+
+ uint32_t Rank; /*!< Specify the rank in the regular group sequencer.
+ This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS
+ Note: to disable a channel or change order of conversion sequencer, rank
+ containing a previous channel setting can be overwritten by
+ the new channel setting (or parameter number of conversions adjusted) */
+
+ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time
+ (13.5 ADC clock cycles at ADC resolution 12 bits, 11.5 cycles at 10 bits,
+ 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
+ Caution: This parameter applies to a channel that can be used into regular
+ and/or injected group. It overwrites the last setting.
+ Note: In case of usage of internal measurement channels
+ (VrefInt/Vbat/TempSensor), sampling time constraints must be respected
+ (sampling time can be adjusted in function of ADC clock frequency
+ and sampling time setting).
+ Refer to device datasheet for timings values. */
+
+ uint32_t SingleDiff; /*!< Select single-ended or differential input.
+ In differential mode: Differential measurement is carried out between
+ the selected channel (positive input) and
+ another channel (negative input). Refer to
+ reference manual for corresponding channel.
+ Only channel of positive input has to be
+ configured, the other channel is configured
+ automatically.
+ This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING
+ Caution: This parameter applies to a channel that can be used in a regular
+ and/or injected group. It overwrites the last setting.
+ Note: Refer to Reference Manual to ensure the selected channel is available
+ in differential mode.
+ Note: When configuring a channel 'i' in differential mode, the channel 'i+1'
+ is not usable separately.
+ Note: This parameter must be modified when ADC is disabled (before ADC start
+ conversion or after ADC stop conversion).
+ If ADC is enabled, this parameter setting is bypassed without error
+ reporting (as it can be the expected behavior in case of another parameter
+ update on the fly) */
+
+ uint32_t OffsetNumber; /*!< Select the offset number
+ This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB
+ Caution: Only one offset is allowed per channel. This parameter overwrites the
+ last setting. */
+
+ uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data.
+ Offset value must be a positive number.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter
+ must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
+ 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
+ Note: This parameter must be modified when no conversion is on going on both
+ regular and injected groups (ADC disabled, or ADC enabled without
+ continuous mode or external trigger that could launch a conversion). */
+
+ FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not.
+ This parameter is applied only for 16-bit or 8-bit resolution.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow.
+ This parameter value can be ENABLE or DISABLE.
+ Note:
+ - This parameter must be modified when no conversion is on going on
+ both regular and injected groups (ADC disabled, or ADC enabled without
+ continuous mode or external trigger that could launch a conversion).*/
+
+ uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added
+ (positive sign) from or to the raw converted data.
+ This parameter can be a value of @ref ADCEx_OffsetSign.
+ Note:
+ - This parameter must be modified when no conversion is on going on
+ both regular and injected groups (ADC disabled, or ADC enabled without
+ continuous mode or external trigger that could launch a conversion).*/
+
+
+} ADC_ChannelConfTypeDef;
+
+/**
+ * @brief Structure definition of ADC analog watchdog
+ * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular
+ * and injected.
+ */
+typedef struct
+{
+ uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
+ For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels
+ by setting parameter 'WatchdogMode')
+ For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls
+ of 'HAL_ADC_AnalogWDGConfig()' for each channel)
+ This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
+
+ uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
+ For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all
+ channels, ADC groups regular and-or injected.
+ For Analog Watchdog 2 and 3: Several channels can be monitored by applying
+ successively the AWD init structure.
+ Channels on ADC group regular and injected are not differentiated:
+ Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel,
+ value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels,
+ 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel.
+ This parameter can be a value of @ref ADC_analog_watchdog_mode. */
+
+ uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
+ For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode'
+ is configured on single channel (only 1 channel can be
+ monitored).
+ For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature,
+ call successively the function HAL_ADC_AnalogWDGConfig()
+ for each channel to be added (or removed with value
+ 'ADC_ANALOGWATCHDOG_NONE').
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
+
+ FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter
+ must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF
+ or 0x3F respectively. */
+
+ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter
+ must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF
+ or 0x3F respectively. */
+
+ uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider.
+ Before setting flag or raising interrupt, analog watchdog can wait to have several
+ consecutive out-of-window samples. This parameter allows to configure this number.
+ This parameter only applies to Analog watchdog 1. For others, use value
+ ADC_AWD_FILTERING_NONE.
+ This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */
+
+} ADC_AnalogWDGConfTypeDef;
+
+/**
+ * @brief ADC group injected contexts queue configuration
+ * @note Structure intended to be used only through structure "ADC_HandleTypeDef"
+ */
+typedef struct
+{
+ uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each
+ HAL_ADCEx_InjectedConfigChannel() call to finally initialize
+ JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
+
+ uint32_t ChannelCount; /*!< Number of channels in the injected sequence */
+} ADC_InjectionConfigTypeDef;
+
+/** @defgroup ADC_States ADC States
+ * @{
+ */
+
+/**
+ * @brief HAL ADC state machine: ADC states definition (bitfields)
+ * @note ADC state machine is managed by bitfields, state must be compared
+ * with bit by bit.
+ * For example:
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
+ */
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization,
+ calibration, ...) */
+#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur
+ (either by continuous mode, external trigger, low power
+ auto power-on (if feature available), multimode ADC master
+ control (if feature available)) */
+#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag
+ raised */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur
+ (either by auto-injection mode, external trigger, low
+ power auto power-on (if feature available), multimode
+ ADC master control (if feature available)) */
+#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another
+ ADC master (when feature available) */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief ADC handle Structure definition
+ */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+typedef struct __ADC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+{
+ ADC_TypeDef *Instance; /*!< Register base address */
+ ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular
+ conversions setting */
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
+ HAL_LockTypeDef Lock; /*!< ADC locking object */
+ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
+ __IO uint32_t ErrorCode; /*!< ADC Error code */
+ ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up
+ structure */
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
+ void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer
+ callback */
+ void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
+ void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
+ void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete
+ callback */
+ void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue
+ overflow callback */
+ void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */
+ void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */
+ void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */
+ void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
+ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+} ADC_HandleTypeDef;
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL ADC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */
+ HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */
+ HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */
+ HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */
+ HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */
+ HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */
+ HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */
+ HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */
+} HAL_ADC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL ADC Callback pointer definition
+ */
+typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_Error_Code ADC Error Code
+ * @{
+ */
+#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
+#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking,
+ enable/disable, erroneous state, ...) */
+#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
+#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
+#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution
+ * @{
+ */
+#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */
+#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */
+#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */
+#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Scan_mode ADC sequencer scan mode
+ * @{
+ */
+#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */
+#define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */
+#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC)
+/**
+ * @}
+ */
+
+/* Combination of all CHSELR bits: SQ2...SQ8 */
+#define ADC_CHSELR_SQ2_TO_SQ8 (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | ADC_CHSELR_SQ5\
+ | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
+ * @{
+ */
+#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion
+ trigger internal: SW start. */
+#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM1 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM1 channel 2 event (capture compare). */
+#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM1 channel 3 event (capture compare). */
+#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM2 channel 2 event (capture compare). */
+#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM3 TRGO event. */
+#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM4 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion
+ trigger from external peripheral: external interrupt line 11. */
+#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM1 TRGO event. */
+#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM1 TRGO2 event. */
+#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM2 TRGO event. */
+#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM4 TRGO event. */
+#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM6 TRGO event. */
+#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM15 TRGO event. */
+#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM3 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIG_EXT_IT15 (LL_ADC_REG_TRIG_EXT_EXTI_LINE15) /*!< ADC group regular conversion
+ trigger from external peripheral: external interrupt line 15. */
+#define ADC_EXTERNALTRIG_LPTIM1_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) /*!< ADC group regular conversion
+ trigger from external peripheral: LPTIM1 channel 1 event. */
+#define ADC_EXTERNALTRIG_LPTIM2_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) /*!< ADC group regular conversion
+ trigger from external peripheral: LPTIM2 channel 1 event. */
+#define ADC_EXTERNALTRIG_LPTIM3_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM3_CH1) /*!< ADC group regular conversion
+ trigger from external peripheral: LPTIM3 channel 1 event. */
+#define ADC_EXTERNALTRIG_LPTIM4_OUT (LL_ADC_REG_TRIG_EXT_LPTIM4_OUT) /*!< ADC group regular conversion
+ trigger from external peripheral: LPTIM4 OUT event. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
+ * @{
+ */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger
+ disabled (SW start)*/
+#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion
+ trigger polarity set to rising edge */
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion
+ trigger polarity set to falling edge */
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion
+ trigger polarity set to both rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode
+ * @{
+ */
+#define ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is
+ defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */
+#define ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts
+ immediately after end of conversion, and stops upon trigger event.
+ Note: First conversion is using minimal sampling time
+ (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */
+#define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled
+ by trigger events:
+ Trigger rising edge = start sampling
+ Trigger falling edge = stop sampling and start conversion */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
+ * @{
+ */
+#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */
+#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
+ * @{
+ */
+#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case
+ of overrun: data preserved */
+#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case
+ of overrun: data overwritten */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
+ * @{
+ */
+#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
+#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
+#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
+#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */
+#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */
+#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */
+#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */
+#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */
+#define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */
+#define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */
+#define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */
+#define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */
+#define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */
+#define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
+#define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
+#define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
+ * @{
+ */
+#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */
+#define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */
+#define ADC_SAMPLETIME_11CYCLES_5 (LL_ADC_SAMPLINGTIME_11CYCLES_5) /*!< Sampling time 11.5 ADC clock cycles */
+#define ADC_SAMPLETIME_23CYCLES_5 (LL_ADC_SAMPLINGTIME_23CYCLES_5) /*!< Sampling time 23.5 ADC clock cycles */
+#define ADC_SAMPLETIME_46CYCLES_5 (LL_ADC_SAMPLINGTIME_46CYCLES_5) /*!< Sampling time 46.5 ADC clock cycles */
+#define ADC_SAMPLETIME_246CYCLES_5 (LL_ADC_SAMPLINGTIME_246CYCLES_5) /*!< Sampling time 246.5 ADC clock cycles */
+#define ADC_SAMPLETIME_1499CYCLES_5 (LL_ADC_SAMPLINGTIME_1499CYCLES_5) /*!< Sampling time 1499.5 ADC clock cycles*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number
+ * @{
+ */
+/* Note: VrefInt, TempSensor and Vbat internal channels are not available on */
+/* all ADC instances (refer to Reference Manual). */
+#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (connected to GPIO
+ pin) ADCx_IN0 */
+#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (connected to GPIO
+ pin) ADCx_IN1 */
+#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (connected to GPIO
+ pin) ADCx_IN2 */
+#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (connected to GPIO
+ pin) ADCx_IN3 */
+#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (connected to GPIO
+ pin) ADCx_IN4 */
+#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (connected to GPIO
+ pin) ADCx_IN5 */
+#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (connected to GPIO
+ pin) ADCx_IN6 */
+#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (connected to GPIO
+ pin) ADCx_IN7 */
+#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (connected to GPIO
+ pin) ADCx_IN8 */
+#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (connected to GPIO
+ pin) ADCx_IN9 */
+#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (connected to GPIO
+ pin) ADCx_IN10 */
+#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (connected to GPIO
+ pin) ADCx_IN11 */
+#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (connected to GPIO
+ pin) ADCx_IN12 */
+#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (connected to GPIO
+ pin) ADCx_IN13 */
+#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (connected to GPIO
+ pin) ADCx_IN14 */
+#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (connected to GPIO
+ pin) ADCx_IN15 */
+#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (connected to GPIO
+ pin) ADCx_IN16 */
+#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (connected to GPIO
+ pin) ADCx_IN17 */
+#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (connected to GPIO
+ pin) ADCx_IN18 */
+#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to
+ VrefInt: Internal voltage reference.
+ Specific to ADC instance: ADC3. */
+#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to
+ Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat
+ always below Vdda.
+ Specific to ADC instance: ADC3. */
+#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor.
+ Specific to ADC instance: ADC3. */
+#define ADC_CHANNEL_VDDCORE (LL_ADC_CHANNEL_VDDCORE) /*!< Internal channel Vddcore.
+ Specific to ADC instance: ADC2. */
+#define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< Internal channel DAC1 channel 1,
+ channel specific to ADC2 */
+#define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< Internal channel DAC1 channel 2,
+ channel specific to ADC2 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management
+ * @{
+ */
+#define ADC_CONVERSIONDATA_DR (LL_ADC_REG_DR_TRANSFER) /*!< ADC conversions data are available
+ in ADC data register only */
+#define ADC_CONVERSIONDATA_DMA_ONESHOT (LL_ADC_REG_DMA_TRANSFER_LIMITED) /*!< ADC conversion data are transferred
+ by DMA, in limited mode (one shot mode): DMA transfer requests are stopped
+ when number of DMA data transfers (number of ADC conversions) is reached.
+ This ADC mode is intended to be used with DMA mode non-circular. */
+#define ADC_CONVERSIONDATA_DMA_CIRCULAR (LL_ADC_REG_DMA_TRANSFER_UNLIMITED) /*!< ADC conversion data are transferred
+ by DMA, in unlimited mode: DMA transfer requests are unlimited,
+ whatever number of DMA data transferred (number of ADC conversions).
+ This ADC mode is intended to be used with DMA mode circular. */
+#define ADC_CONVERSIONDATA_MDF (LL_ADC_REG_MDF_TRANSFER) /*!< ADC conversion data are transferred
+ to MDF */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
+#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
+#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration
+ * @{
+ */
+#define ADC_AWD_FILTERING_NONE LL_ADC_AWD_FILTERING_NONE /*!< ADC analog watchdog no filtering,
+ one out-of-window sample is needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_2SAMPLES LL_ADC_AWD_FILTERING_2SAMPLES /*!< ADC analog watchdog 2 consecutives
+ out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_3SAMPLES LL_ADC_AWD_FILTERING_3SAMPLES /*!< ADC analog watchdog 3 consecutives
+ out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_4SAMPLES LL_ADC_AWD_FILTERING_4SAMPLES /*!< ADC analog watchdog 4 consecutives
+ out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_5SAMPLES LL_ADC_AWD_FILTERING_5SAMPLES /*!< ADC analog watchdog 5 consecutives
+ out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_6SAMPLES LL_ADC_AWD_FILTERING_6SAMPLES /*!< ADC analog watchdog 6 consecutives
+ out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_7SAMPLES LL_ADC_AWD_FILTERING_7SAMPLES /*!< ADC analog watchdog 7 consecutives
+ out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_8SAMPLES LL_ADC_AWD_FILTERING_8SAMPLES /*!< ADC analog watchdog 8 consecutives
+ out-of-window samples are needed to raise flag or interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */
+
+#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to a
+ regular group single channel */
+
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR1_AWD1SGL | ADC_CFGR1_JAWD1EN) /*!< ADC AWD applied to an
+ injected group single channel */
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN \
+ | ADC_CFGR1_JAWD1EN) /*!< ADC AWD applied to a
+ regular and injected groups single channel */
+#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to regular
+ group all channels */
+#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR1_JAWD1EN) /*!< ADC AWD applied to injected
+ group all channels */
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR1_AWD1EN | ADC_CFGR1_JAWD1EN) /*!< ADC AWD applied to regular
+ and injected groups all channels */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift
+ * @{
+ */
+#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */
+#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */
+#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */
+#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */
+#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */
+#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */
+#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */
+#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */
+#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */
+#define ADC_RIGHTBITSHIFT_9 (LL_ADC_OVS_SHIFT_RIGHT_9) /*!< ADC oversampling right shift of 9 ranks */
+#define ADC_RIGHTBITSHIFT_10 (LL_ADC_OVS_SHIFT_RIGHT_10)/*!< ADC oversampling right shift of 10 ranks */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Left_Bit_Shift ADC Extended Oversampling left Shift
+ * @{
+ */
+#define ADC_LEFTBITSHIFT_NONE (LL_ADC_LEFT_BIT_SHIFT_NONE) /*!< ADC No bit shift */
+#define ADC_LEFTBITSHIFT_1 (LL_ADC_LEFT_BIT_SHIFT_1) /*!< ADC 1 bit shift */
+#define ADC_LEFTBITSHIFT_2 (LL_ADC_LEFT_BIT_SHIFT_2) /*!< ADC 2 bits shift */
+#define ADC_LEFTBITSHIFT_3 (LL_ADC_LEFT_BIT_SHIFT_3) /*!< ADC 3 bits shift */
+#define ADC_LEFTBITSHIFT_4 (LL_ADC_LEFT_BIT_SHIFT_4) /*!< ADC 4 bits shift */
+#define ADC_LEFTBITSHIFT_5 (LL_ADC_LEFT_BIT_SHIFT_5) /*!< ADC 5 bits shift */
+#define ADC_LEFTBITSHIFT_6 (LL_ADC_LEFT_BIT_SHIFT_6) /*!< ADC 6 bits shift */
+#define ADC_LEFTBITSHIFT_7 (LL_ADC_LEFT_BIT_SHIFT_7) /*!< ADC 7 bits shift */
+#define ADC_LEFTBITSHIFT_8 (LL_ADC_LEFT_BIT_SHIFT_8) /*!< ADC 8 bits shift */
+#define ADC_LEFTBITSHIFT_9 (LL_ADC_LEFT_BIT_SHIFT_9) /*!< ADC 9 bits shift */
+#define ADC_LEFTBITSHIFT_10 (LL_ADC_LEFT_BIT_SHIFT_10) /*!< ADC 10 bits shift */
+#define ADC_LEFTBITSHIFT_11 (LL_ADC_LEFT_BIT_SHIFT_11) /*!< ADC 11 bits shift */
+#define ADC_LEFTBITSHIFT_12 (LL_ADC_LEFT_BIT_SHIFT_12) /*!< ADC 12 bits shift */
+#define ADC_LEFTBITSHIFT_13 (LL_ADC_LEFT_BIT_SHIFT_13) /*!< ADC 13 bits shift */
+#define ADC_LEFTBITSHIFT_14 (LL_ADC_LEFT_BIT_SHIFT_14) /*!< ADC 14 bits shift */
+#define ADC_LEFTBITSHIFT_15 (LL_ADC_LEFT_BIT_SHIFT_15) /*!< ADC 15 bits shift */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
+ * @{
+ */
+#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode:
+ continuous mode (all conversions of OVS ratio are done from 1 trigger) */
+#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode:
+ discontinuous mode (each conversion of OVS ratio needs a trigger) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular
+ * @{
+ */
+#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained
+ during injection sequence */
+#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during
+ injection sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Event_type ADC Event type
+ * @{
+ */
+/**
+ * @note Analog watchdog 1 is available on all stm32 series
+ * Analog watchdog 2 and 3 are not available on all series
+ */
+#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
+#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */
+#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */
+#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */
+#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
+#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
+/**
+ * @}
+ */
+#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility
+ with other STM32 devices having only one analog watchdog */
+
+/** @defgroup ADC_interrupts_definition ADC interrupts definition
+ * @{
+ */
+#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */
+#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */
+#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */
+#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */
+#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
+#define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */
+#define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */
+#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
+#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog
+ watchdog) */
+#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog
+ watchdog) */
+#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */
+#define ADC_IT_LDORDY ADC_IER_LDORDYIE /*!< ADC internal voltage regulator ready interrupt source */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition ADC flags definition
+ * @{
+ */
+#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */
+#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
+#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
+#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
+#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */
+#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
+#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
+#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
+#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC internal voltage regulator output ready flag */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Macros ADC Private Macros
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in */
+/* code of final user. */
+
+/**
+ * @brief Verify the ADC data conversion setting.
+ * @param DATA : programmed DATA conversion mode.
+ * @retval SET (DATA is a valid value) or RESET (DATA is invalid)
+ */
+#define IS_ADC_CONVERSIONDATAMGT(DATA) \
+ ((((DATA) == ADC_CONVERSIONDATA_DR)) || \
+ (((DATA) == ADC_CONVERSIONDATA_MDF)) || \
+ (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \
+ (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR)))
+
+/**
+ * @brief Return resolution bits in CFGR register RES[1:0] field.
+ * @param __HANDLE__ ADC handle
+ * @retval Value of bitfield RES in CFGR register.
+ */
+#define ADC_GET_RESOLUTION(__HANDLE__) \
+ (LL_ADC_GetResolution((__HANDLE__)->Instance))
+
+/**
+ * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+/**
+ * @brief Verification of ADC state: enabled or disabled.
+ * @param __HANDLE__ ADC handle
+ * @retval SET (ADC enabled) or RESET (ADC disabled)
+ */
+#define ADC_IS_ENABLE(__HANDLE__) \
+ ((((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
+ ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
+ ) ? SET : RESET)
+
+/**
+ * @brief Check if conversion is on going on regular group.
+ * @param __HANDLE__ ADC handle
+ * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going)
+ */
+#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
+ (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance))
+
+
+/**
+ * @brief Simultaneously clear and set specific bits of the handle State.
+ * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+ * the first parameter is the ADC handle State, the second parameter is the
+ * bit field to clear, the third and last parameter is the bit field to set.
+ * @retval None
+ */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+ * @brief Verify that a given value is aligned with the ADC resolution range.
+ * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
+ * @param __ADC_VALUE__ value checked against the resolution.
+ * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
+ */
+#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
+ ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
+
+/**
+ * @brief Verify the length of the scheduled regular conversions group.
+ * @param __LENGTH__ number of programmed conversions.
+ * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions)
+ * or RESET (__LENGTH__ is null or too large)
+ */
+#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
+
+
+/**
+ * @brief Verify the number of scheduled regular conversions in discontinuous mode.
+ * @param NUMBER number of scheduled regular conversions in discontinuous mode.
+ * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode)
+ * or RESET (NUMBER is null or too large)
+ */
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
+
+/**
+ * @brief Verify the ADC resolution setting.
+ * @param __RESOLUTION__ programmed ADC resolution.
+ * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
+ */
+#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_6B) )
+
+/**
+ * @brief Verify the ADC resolution setting when limited to 6 or 8 bits.
+ * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits.
+ * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
+ */
+#define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_6B) )
+
+/**
+ * @brief Verify the ADC gain compensation.
+ * @param __GAIN_COMPENSATION__ programmed ADC gain compensation coefficient.
+ * @retval SET (__GAIN_COMPENSATION__ is a valid value) or RESET (__GAIN_COMPENSATION__ is invalid)
+ */
+#define IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) ((__GAIN_COMPENSATION__) <= 0x3FFFUL)
+
+/**
+ * @brief Verify the ADC offset.
+ * @param __OFFSET__ programmed ADC offset.
+ * @retval SET (__OFFSET__ is a valid value) or RESET (__OFFSET__ is invalid)
+ */
+#define IS_ADC_OFFSET(__OFFSET__) ((__OFFSET__) <= 0x3FFFFFUL)
+
+/**
+ * @brief Verify the ADC scan mode.
+ * @param __SCAN_MODE__ programmed ADC scan mode.
+ * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)
+ */
+#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
+ ((__SCAN_MODE__) == ADC_SCAN_ENABLE) )
+
+/**
+ * @brief Verify the ADC edge trigger setting for regular group.
+ * @param __EDGE__ programmed ADC edge trigger setting.
+ * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
+ */
+#define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
+
+/**
+ * @brief Verify the ADC regular conversions external trigger.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __REG_TRIG_SOURCE__ programmed ADC regular conversions external trigger.
+ * @retval SET (__REG_TRIG_SOURCE__ is a valid value) or RESET (__REG_TRIG_SOURCE__ is invalid)
+ */
+#define IS_ADC_EXTTRIG(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
+ (((__REG_TRIG_SOURCE__) == ADC_SOFTWARE_START) \
+ || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T1_CC1) \
+ || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T1_CC2) \
+ || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T1_CC3) \
+ || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T2_CC2) \
+ || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T3_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T4_CC4) \
+ || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_EXT_IT11) \
+ || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T2_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T4_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T6_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T15_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T3_CC4) \
+ || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_EXT_IT15) \
+ || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_LPTIM1_CH1) \
+ || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_LPTIM2_CH1) \
+ || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_LPTIM3_CH1) \
+ || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_LPTIM4_OUT) \
+ )
+
+
+/**
+ * @brief Verify the ADC regular conversions external trigger.
+ * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger.
+ * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid)
+ */
+#define IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL) || \
+ ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB) || \
+ ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED) )
+
+/**
+ * @brief Verify the ADC regular conversions check for converted data availability.
+ * @param __EOC_SELECTION__ converted data availability check.
+ * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)
+ */
+#define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \
+ ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) )
+
+/**
+ * @brief Verify the ADC regular conversions overrun handling.
+ * @param __OVR__ ADC regular conversions overrun handling.
+ * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)
+ */
+#define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \
+ ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) )
+
+/**
+ * @brief Verify the ADC conversions sampling time.
+ * @param __SAMPLING_TIME__ ADC conversions sampling time.
+ * @retval SET (__SAMPLING_TIME__ is a valid value) or RESET (__SAMPLING_TIME__ is invalid)
+ */
+#define IS_ADC_SAMPLING_TIME(__SAMPLING_TIME__) (((__SAMPLING_TIME__) == ADC_SAMPLETIME_1CYCLE_5) || \
+ ((__SAMPLING_TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \
+ ((__SAMPLING_TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \
+ ((__SAMPLING_TIME__) == ADC_SAMPLETIME_11CYCLES_5) || \
+ ((__SAMPLING_TIME__) == ADC_SAMPLETIME_23CYCLES_5) || \
+ ((__SAMPLING_TIME__) == ADC_SAMPLETIME_46CYCLES_5) || \
+ ((__SAMPLING_TIME__) == ADC_SAMPLETIME_246CYCLES_5) || \
+ ((__SAMPLING_TIME__) == ADC_SAMPLETIME_1499CYCLES_5) )
+
+/**
+ * @brief Verify the ADC regular channel setting.
+ * @param __CHANNEL__ programmed ADC regular channel.
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+ */
+#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_16) )
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/* Fixed timeout values for ADC conversion (including sampling time) */
+/* Maximum sampling time is 1499.5 ADC clock cycle (SMPx[2:0] = 0b111) */
+/* Maximum conversion time is 12.5 + Maximum samling time */
+/* or 12.5 + 1499.5 = 1512 ADC clock cycles */
+/* Minimum ADC Clock frequency is 0.7 MHz */
+/* (refer to device datasheet, parameter "fADC") */
+/* Maximum conversion time is */
+/* = 1512 / 0.7MHz = 2.16 ms */
+/* Used timeout value includes a margin versus theoretical max value */
+#define ADC_STOP_CONVERSION_TIMEOUT (5UL) /*!< ADC stop time-out value */
+
+/* Delay for temperature sensor stabilization time. */
+/* Maximum delay is 120us (refer device datasheet, parameter tSTART). */
+/* Unit: us */
+#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
+
+/* Delay for ADC voltage regulator startup time */
+/* Maximum delay is 10 microseconds */
+/* (refer device RM, parameter Tadcvreg_stup). */
+#define ADC_STAB_DELAY_US ((uint32_t) 10) /*!< ADC voltage regulator startup time */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+ * @{
+ */
+/* Macro for internal HAL driver usage, and possibly can be used into code of */
+/* final user. */
+
+/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.
+ * @{
+ */
+
+/** @brief Reset ADC handle state.
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->State = HAL_ADC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enable ADC interrupt.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC Interrupt
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_IT_RDY ADC Ready interrupt source
+ * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
+ * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
+ * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_OVR ADC overrun interrupt source
+ * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
+ * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
+ * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+ * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable ADC interrupt.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC Interrupt
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_IT_RDY ADC Ready interrupt source
+ * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
+ * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
+ * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_OVR ADC overrun interrupt source
+ * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
+ * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
+ * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+ * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC interrupt source to check
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_IT_RDY ADC Ready interrupt source
+ * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
+ * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
+ * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_OVR ADC overrun interrupt source
+ * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
+ * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
+ * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+ * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified ADC flag is set or not.
+ * @param __HANDLE__ ADC handle
+ * @param __FLAG__ ADC flag
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_FLAG_RDY ADC Ready flag
+ * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
+ * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
+ * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
+ * @arg @ref ADC_FLAG_OVR ADC overrun flag
+ * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
+ * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
+ * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
+ * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
+ * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
+ * @retval State of flag (TRUE or FALSE).
+ */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the specified ADC flag.
+ * @param __HANDLE__ ADC handle
+ * @param __FLAG__ ADC flag
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_FLAG_RDY ADC Ready flag
+ * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
+ * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
+ * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
+ * @arg @ref ADC_FLAG_OVR ADC overrun flag
+ * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
+ * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
+ * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
+ * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
+ * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
+ * @retval None
+ */
+/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ (((__HANDLE__)->Instance->ISR) = (__FLAG__))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to get ADC channel number in decimal format
+ * from literals ADC_CHANNEL_x.
+ * @note Example:
+ * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
+ * will return decimal number "4".
+ * @note The input can be a value from functions where a channel
+ * number is returned, either defined with number
+ * or with bitfield (only one bit must be set).
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ * @arg @ref ADC_CHANNEL_VREFINT
+ * @arg @ref ADC_CHANNEL_VBAT
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR
+ * @arg @ref ADC_CHANNEL_VDDCORE
+ * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+ * @retval Value between Min_Data=0 and Max_Data=18
+ */
+#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
+
+/**
+ * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x
+ * from number in decimal format.
+ * @note Example:
+ * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+ * will return a data equivalent to "ADC_CHANNEL_4".
+ * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)(3)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(3)
+ * @arg @ref LL_ADC_CHANNEL_VDDCORE (1)(3)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(3)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(3)
+ *
+ * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+ * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+ * (3) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
+
+/**
+ * @brief Helper macro to determine whether the selected channel
+ * corresponds to literal definitions of driver.
+ * @note The different literal definitions of ADC channels are:
+ * - ADC internal channel:
+ * ADC_CHANNEL_VREFINT, ...
+ * - ADC external channel (channel connected to a GPIO pin):
+ * ADC_CHANNEL_1, ADC_CHANNEL_2, ...
+ * @note The channel parameter must be a value defined from literal
+ * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ...),
+ * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
+ * must not be a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ * @arg @ref ADC_CHANNEL_VREFINT
+ * @arg @ref ADC_CHANNEL_VBAT
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR
+ * @arg @ref ADC_CHANNEL_VDDCORE
+ * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+ * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel
+ * (channel connected to a GPIO pin).
+ * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+ */
+#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
+ __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
+
+/**
+ * @brief Helper macro to convert a channel defined from parameter
+ * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ...),
+ * to its equivalent parameter definition of a ADC external channel
+ * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
+ * @note The channel parameter can be, additionally to a value
+ * defined from parameter definition of a ADC internal channel
+ * (ADC_CHANNEL_VREFINT, ...),
+ * a value defined from parameter definition of
+ * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is returned
+ * from ADC registers.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ * @arg @ref ADC_CHANNEL_VREFINT
+ * @arg @ref ADC_CHANNEL_VBAT
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR
+ * @arg @ref ADC_CHANNEL_VDDCORE
+ * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ */
+#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
+ __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
+
+/**
+ * @brief Helper macro to determine whether the internal channel
+ * selected is available on the ADC instance selected.
+ * @note The channel parameter must be a value defined from parameter
+ * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ...),
+ * must not be a value defined from parameter definition of
+ * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_VREFINT
+ * @arg @ref ADC_CHANNEL_VBAT
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR
+ * @arg @ref ADC_CHANNEL_VDDCORE
+ * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On this STM32 series, parameter available only on ADC instance: ADC2.
+ * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+ * Value "1" if the internal channel selected is available on the ADC instance selected.
+ */
+#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Helper macro to get the ADC multimode conversion data of ADC master
+ * or ADC slave from raw value with both ADC conversion data concatenated.
+ * @note This macro is intended to be used when multimode transfer by DMA
+ * is enabled: refer to function @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+ * In this case the transferred data need to processed with this macro
+ * to separate the conversion data of ADC master and ADC slave.
+ * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_MASTER
+ * @arg @ref LL_ADC_MULTI_SLAVE
+ * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
+ __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Helper macro to select the ADC common instance
+ * to which is belonging the selected ADC instance.
+ * @note ADC common register instance can be used for:
+ * - Set parameters common to several ADC instances
+ * - Multimode (for devices with several ADC instances)
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @param __ADCx__ ADC instance
+ * @retval ADC common register instance
+ */
+#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \
+ __LL_ADC_COMMON_INSTANCE((__ADCx__))
+
+/**
+ * @brief Helper macro to check if all ADC instances sharing the same
+ * ADC common instance are disabled.
+ * @note This check is required by functions with setting conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @note On devices with only 1 ADC common instance, parameter of this macro
+ * is useless and can be ignored (parameter kept for compatibility
+ * with devices featuring several ADC common instances).
+ * @param __ADCXY_COMMON__ ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Value "0" if all ADC instances sharing the same ADC common instance
+ * are disabled.
+ * Value "1" if at least one ADC instance sharing the same ADC common instance
+ * is enabled.
+ */
+#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
+
+/**
+ * @brief Helper macro to define the ADC conversion data full-scale digital
+ * value corresponding to the selected ADC resolution.
+ * @note ADC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @retval ADC conversion data full-scale digital value
+ */
+#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to convert the ADC conversion data from
+ * a resolution to another resolution.
+ * @param __DATA__ ADC conversion data to be converted
+ * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @retval ADC conversion data to the requested resolution
+ */
+#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+ __ADC_RESOLUTION_CURRENT__,\
+ __ADC_RESOLUTION_TARGET__) \
+__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
+ (__ADC_RESOLUTION_CURRENT__),\
+ (__ADC_RESOLUTION_TARGET__))
+
+/**
+ * @brief Helper macro to calculate the voltage (unit: mVolt)
+ * corresponding to a ADC conversion data (unit: digital value).
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+ __ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
+ (__ADC_DATA__),\
+ (__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to calculate analog reference voltage (Vref+)
+ * (unit: mVolt) from ADC conversion data of internal voltage
+ * reference VrefInt.
+ * @note Computation is using VrefInt calibration value
+ * stored in system memory for each device during production.
+ * @note This voltage depends on user board environment: voltage level
+ * connected to pin Vref+.
+ * On devices with small package, the pin Vref+ is not present
+ * and internally bonded to pin Vdda.
+ * @note On this STM32 series, calibration data of internal voltage reference
+ * VrefInt corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * internal voltage reference VrefInt.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 12 bits.
+ * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * of internal voltage reference VrefInt (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @retval Analog reference voltage (unit: mV)
+ */
+#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
+ (__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor calibration values
+ * stored in system memory for each device during production.
+ * @note Calculation formula:
+ * Temperature = ((TS_ADC_DATA - TS_CAL1)
+ * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+ * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * Avg_Slope = (TS_CAL2 - TS_CAL1)
+ * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+ * TS_CAL1 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL1 (calibrated in factory)
+ * TS_CAL2 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL2 (calibrated in factory)
+ * Caution: Calculation relevancy under reserve that calibration
+ * parameters are correct (address and data).
+ * To calculate temperature using temperature sensor
+ * datasheet typical values (generic values less, therefore
+ * less accurate than calibrated values),
+ * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note On this STM32 series, calibration data of temperature sensor
+ * corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * temperature sensor.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 12 bits.
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+ * temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
+ * sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
+ (__TEMPSENSOR_ADC_DATA__),\
+ (__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor typical values
+ * (refer to device datasheet).
+ * @note Calculation formula:
+ * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+ * / Avg_Slope + CALx_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * (unit: digital value)
+ * Avg_Slope = temperature sensor slope
+ * (unit: uV/Degree Celsius)
+ * TS_TYP_CALx_VOLT = temperature sensor digital value at
+ * temperature CALx_TEMP (unit: mV)
+ * Caution: Calculation relevancy under reserve the temperature sensor
+ * of the current device has characteristics in line with
+ * datasheet typical values.
+ * If temperature sensor calibration values are available on
+ * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+ * temperature calculation will be more accurate using
+ * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note ADC measurement data must correspond to a resolution of 12bits
+ * (full scale digital value 4095). If not the case, the data must be
+ * preliminarily rescaled to an equivalent resolution of 12 bits.
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
+ (unit: uV/DegCelsius).
+ * On this STM32 series, refer to device datasheet parameter "Avg_Slope".
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value
+ * (at temperature and Vref+ defined in parameters below) (unit: mV).
+ * On this STM32 series, refer to device datasheet parameter "V30"
+ * (corresponding to TS_CAL1).
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see
+ parameter above) is corresponding (unit: mV)
+ * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @arg @ref ADC_RESOLUTION_6B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+ __TEMPSENSOR_TYP_CALX_V__,\
+ __TEMPSENSOR_CALX_TEMP__,\
+ __VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
+ (__TEMPSENSOR_TYP_CALX_V__),\
+ (__TEMPSENSOR_CALX_TEMP__),\
+ (__VREFANALOG_VOLTAGE__),\
+ (__TEMPSENSOR_ADC_DATA__),\
+ (__ADC_RESOLUTION__))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Include ADC HAL Extended module */
+#include "stm32u3xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+ pADC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group2
+ * @brief IO operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
+
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc);
+int32_t HAL_ADC_GetSignedValue(const ADC_HandleTypeDef *hadc);
+
+/* ADC sampling control */
+HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig);
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc,
+ const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig);
+
+/**
+ * @}
+ */
+
+/* Peripheral State functions *************************************************/
+/** @addtogroup ADC_Exported_Functions_Group4
+ * @{
+ */
+uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc);
+uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup ADC_Private_Functions ADC Private Functions
+ * @{
+ */
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup);
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+void ADC_DMAError(DMA_HandleTypeDef *hdma);
+void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U3xx_HAL_ADC_H */
diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_adc_ex.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_adc_ex.h
new file mode 100644
index 0000000000..cd4045c17e
--- /dev/null
+++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_adc_ex.h
@@ -0,0 +1,1255 @@
+/**
+ ******************************************************************************
+ * @file stm32u3xx_hal_adc_ex.h
+ * @author MCD Application Team
+ * @brief Header file of ADC HAL extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U3xx_HAL_ADC_EX_H
+#define STM32U3xx_HAL_ADC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u3xx_hal_def.h"
+
+/** @addtogroup STM32U3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
+ * @{
+ */
+
+/**
+ * @brief ADC Injected Conversion Oversampling structure definition
+ */
+typedef struct
+{
+ uint32_t Ratio; /*!< Configures the oversampling ratio.
+ This parameter can be a value from 1 to 1024 */
+
+ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
+} ADC_InjOversamplingTypeDef;
+
+/**
+ * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff,
+ * InjectedOffsetNumber, InjectedOffset
+ * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion,
+ * InjectedDiscontinuousConvMode, AutoInjectedConv, ExternalTrigInjecConv,
+ * ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
+ * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter
+ * 'InjectedSingleDiff')
+ * - For parameters 'InjectedDiscontinuousConvMode', 'InjecOversampling':
+ * ADC enabled without conversion on going on injected group.
+ * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv':
+ * ADC enabled without conversion on going on regular and injected groups.
+ * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv',
+ * 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going on ADC groups
+ * regular and injected.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behavior in case of intended action to update another
+ * parameter (which fulfills the ADC state condition) on the fly).
+ */
+typedef struct
+{
+ uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected.
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
+ Note: Depending on devices and ADC instances, some channels may not be
+ available on device package pins. Refer to device datasheet for
+ channels availability. */
+
+ uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer.
+ This parameter must be a value of @ref ADC_INJ_SEQ_RANKS.
+ Note: to disable a channel or change order of conversion sequencer,
+ rank containing a previous channel setting can be overwritten by
+ the new channel setting (or parameter number of conversions
+ adjusted) */
+
+ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles.
+ Conversion time is the addition of sampling time and processing time
+ (13.5 ADC clock cycles at ADC resolution 12 bits, 11.5 cycles at 10 bits,
+ 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.
+ Caution: This parameter applies to a channel that can be used in a
+ regular and/or injected group.
+ It overwrites the last setting.
+ Note: In case of usage of internal measurement channels
+ (VrefInt/Vbat/TempSensor), sampling time constraints must be
+ respected (sampling time can be adjusted in function of ADC clock
+ frequency and sampling time setting);
+ Refer to device datasheet for timings values. */
+ uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
+ In differential mode: Differential measurement is carried out between
+ the selected channel (positive input) and
+ another channel (negative input). Refer to
+ reference manual for corresponding channel.
+ Only channel of positive input has to be
+ configured, the other channel is configured
+ automatically.
+ This parameter must be a value of:
+ @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
+ Caution: This parameter applies to a channel that can be used in a
+ regular and/or injected group. It overwrites the last setting.
+ Note: Refer to Reference Manual to ensure the selected channel is
+ available in differential mode.
+ Note: This parameter must be modified when ADC is disabled (before ADC
+ start conversion or after ADC stop conversion).
+ If ADC is enabled, this parameter setting is bypassed without error
+ reporting (as it can be the expected behavior in case of another
+ parameter update on the fly) */
+
+ uint32_t InjectedOffsetNumber; /*!< Selects the offset number.
+ This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.
+ Caution: Only one offset is allowed per channel. This parameter
+ overwrites the last setting. */
+
+ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
+ Offset value must be a positive number.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits), this
+ parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
+ 0x3FF, 0xFF or 0x3F respectively.
+ Note: This parameter must be modified when no conversion is on going on
+ both regular and injected groups (ADC disabled, or ADC enabled
+ without continuous mode or external trigger that could launch a
+ conversion). */
+
+ FunctionalState InjectedOffsetSignedSaturation; /*!< Specifies whether the Signed saturation feature is used or not.
+ This parameter is applied only for 14-bit or 8-bit resolution.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added
+ (positive sign) from or to the raw converted data.
+ This parameter can be a value of @ref ADCEx_OffsetSign.
+ Note:
+ - This parameter must be modified when no conversion is on going on
+ both regular and injected groups (ADC disabled or ADC enabled without
+ continuous mode or external trigger that could launch a conversion).
+ - This parameter is specific to ADC1 only. */
+
+ FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow.
+ This parameter value can be ENABLE or DISABLE.
+ Note: This parameter must be modified when no conversion is on going
+ on both regular and injected groups (ADC disabled, or ADC enabled
+ without continuous mode or external trigger that could launch
+ a conversion). */
+
+ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within
+ the ADC group injected sequencer.
+ To use the injected group sequencer and convert several ranks,
+ parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+ Caution: this setting impacts the entire injected group.
+ Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the
+ configuration of other channels previously set. */
+
+ FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected
+ is performed in Complete-sequence/Discontinuous-sequence
+ (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled
+ (parameter 'ScanConvMode').
+ If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous
+ mode is disabled.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: This parameter must be modified when ADC is disabled
+ (before ADC start conversion or after ADC stop conversion).
+ Note: For injected group, discontinuous mode converts the
+ sequence channel by channel (discontinuous length
+ fixed to 1 rank).
+ Caution: this setting impacts the entire injected group.
+ Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the
+ configuration of other channels previously set. */
+
+ FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion
+ after regular one
+ This parameter can be set to ENABLE or DISABLE.
+ Note: To use Automatic injected conversion, discontinuous mode must be
+ disabled ('DiscontinuousConvMode' and
+ 'InjectedDiscontinuousConvMode' set to DISABLE)
+ Note: To use Automatic injected conversion, injected group external
+ triggers must be disabled ('ExternalTrigInjecConv' set to
+ ADC_INJECTED_SOFTWARE_START)
+ Note: In case of DMA used with regular group: if DMA configured in normal
+ mode (single shot) JAUTO will be stopped upon DMA transfer
+ complete. To maintain JAUTO always enabled,
+ DMA must be configured in circular mode.
+ Caution: this setting impacts the entire injected group.
+ Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the
+ configuration of other channels previously set. */
+ FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
+ This parameter can be set to ENABLE or DISABLE.
+ If context queue is enabled, injected sequencer&channels configurations
+ are queued on up to 2 contexts. If a
+ new injected context is set when queue is full, error is triggered by
+ interruption and through function
+ 'HAL_ADCEx_InjectedQueueOverflowCallback'.
+ Caution: This feature request that the sequence is fully configured
+ before injected conversion start.
+ Therefore, configure channels with as many calls to
+ HAL_ADCEx_InjectedConfigChannel() as the
+ 'InjectedNbrOfConversion' parameter.
+ Caution: this setting impacts the entire injected group. Therefore,
+ call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the
+ configuration of other channels previously set.
+ Note: This parameter must be modified when ADC is disabled (before ADC
+ start conversion or after ADC stop conversion). */
+
+
+ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of
+ injected group.
+ If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled
+ and software trigger is used instead.
+ This parameter can be a value of
+ @ref ADC_injected_external_trigger_source.
+ Caution: this setting impacts the entire injected group. Therefore,
+ call of HAL_ADCEx_InjectedConfigChannel() to configure a channel
+ on injected group can impact the configuration of other channels
+ previously set. */
+
+ uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
+ This parameter can be a value of @ref ADC_injected_external_trigger_edge.
+ If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter
+ is discarded.
+ Caution: this setting impacts the entire injected group. Therefore,
+ call of HAL_ADCEx_InjectedConfigChannel() to configure a
+ channel on injected group can impact the configuration of other
+ channels previously set. */
+
+ FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: This parameter can be modified only if there is no conversion
+ is ongoing (both ADSTART and JADSTART cleared). */
+
+ ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters.
+ Caution: this setting overwrites the previous oversampling
+ configuration if oversampling already enabled.
+ Note: This parameter can be modified only if there is no
+ conversion is ongoing (both ADSTART and
+ JADSTART cleared).*/
+} ADC_InjectionConfTypeDef;
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Structure definition of ADC multimode
+ * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs
+ * state (both Master and Slave ADCs).
+ * Both Master and Slave ADCs must be disabled.
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode.
+ This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */
+
+ uint32_t DualModeData; /*!< Configures the Dual ADC Mode Data Format:
+ This parameter can be a value of @ref ADCEx_Dual_Mode_Data_Format */
+
+ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
+ This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY */
+} ADC_MultiModeTypeDef;
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
+ * @{
+ */
+/* ADC group regular trigger sources for all ADC instances */
+#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< ADC group regular conversion
+ trigger internal: SW start. */
+#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM1 TRGO event. */
+#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion
+ trigger from external peripheral: TIM1 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM2 TRGO event. */
+#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion
+ trigger from external peripheral: TIM2 channel 2 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion
+ trigger from external peripheral: TIM3 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM4 TRGO event. */
+#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion
+ trigger from external peripheral: external interrupt line 15. */
+#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM1 TRGO2 event. */
+#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion
+ trigger from external peripheral: TIM3 channel 3 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM3 TRGO event. */
+#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion
+ trigger from external peripheral: TIM1 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM6 TRGO event. */
+#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion
+ trigger from external peripheral: TIM15 TRGO event. */
+#define ADC_EXTERNALTRIGINJEC_LPTIM1_CH2 (LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2) /*!< ADC group injected conversion
+ trigger from external peripheral: LPTIM1 channel 2 event. */
+#define ADC_EXTERNALTRIGINJEC_LPTIM2_CH2 (LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2) /*!< ADC group injected conversion
+ trigger from external peripheral: LPTIM2 channel 2 event. */
+#define ADC_EXTERNALTRIGINJEC_LPTIM3_CH1 (LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1) /*!< ADC group injected conversion
+ trigger from external peripheral: LPTIM3 channel 2 event. */
+#define ADC_EXTERNALTRIGINJEC_LPTIM4_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM4_OUT) /*!< ADC group regular conversion
+ trigger from external peripheral: LPTIM4 OUT event. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
+ * @{
+ */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions trigger
+ disabled (SW start)*/
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions trigger
+ polarity set to rising edge */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions trigger
+ polarity set to falling edge */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions trigger
+ polarity set to both rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
+ * @{
+ */
+#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number
+ * @{
+ */
+#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected
+ ADC channel */
+#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which
+ the offset programmed will be applied (independently of channel mapped
+ on ADC group regular or group injected) */
+#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which
+ the offset programmed will be applied (independently of channel mapped
+ on ADC group regular or group injected) */
+#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which
+ the offset programmed will be applied (independently of channel mapped
+ on ADC group regular or group injected) */
+#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which
+ the offset programmed will be applied (independently of channel mapped
+ on ADC group regular or group injected) */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign
+ * @{
+ */
+#define ADC_OFFSET_SIGN_NEGATIVE LL_ADC_OFFSET_SIGN_NEGATIVE /*!< Offset sign negative, offset is subtracted */
+#define ADC_OFFSET_SIGN_POSITIVE LL_ADC_OFFSET_SIGN_POSITIVE /*!< Offset sign positive, offset is added */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
+ * @{
+ */
+#define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */
+#define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */
+#define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */
+#define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */
+/**
+ * @}
+ */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode
+ * @{
+ */
+#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled
+ (ADC independent mode) */
+#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular
+ simultaneous */
+#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined
+ group regular interleaved */
+#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group
+ injected simultaneous */
+#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group
+ injected alternate trigger. Works only with external triggers (not internal
+ SW start) */
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined
+ group regular simultaneous + group injected simultaneous */
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined
+ group regular simultaneous + group injected alternate trigger */
+#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined
+ group regular interleaved + group injected simultaneous */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Dual_Mode_Data_Format ADC Extended Dual Mode Data Formatting
+ * @{
+ */
+
+#define ADC_DUALMODEDATAFORMAT_DISABLED (LL_ADC_MULTI_REG_DATA_EACH_ADC) /*!< ADC multimode group regular data
+ format: conversion data in data register of each ADC instance.
+ If ADC data transfer by DMA is used: each ADC uses its own DMA channel,
+ with its individual DMA transfer settings. */
+#define ADC_DUALMODEDATAFORMAT_32_BIT (LL_ADC_MULTI_REG_DATA_COMMON_32B) /*!< ADC multimode group regular data
+ format: conversion data in two ADC common instance data registers (CDR, CDR2)
+ with packing option on 32 bit. In register CDR, data packing on 32 bit:
+ ADC master and slave data are concatenated (data master in [15; 0],
+ data slave in [31; 16]), therefore data width must be lower than 16 bit
+ (even with ADC resolution 12 bit, higher width reachable by post processing:
+ oversampling, offset, ...). In register CDR2, data of master and slave are
+ alternatively set in full register width 32 bit, therefore no constraint on
+ data width. In case of usage with DMA, CDR generate ones transfer request
+ and CDR2 two transfer requests per conversion. */
+#define ADC_DUALMODEDATAFORMAT_8_BIT (LL_ADC_MULTI_REG_DATA_COMMON_16B) /*!< ADC multimode group regular data
+ format: conversion data in two ADC common instance data registers (CDR, CDR2)
+ with packing option on 16 bit. In register CDR, data packing on 16 bit:
+ ADC master and slave data are concatenated (data master in [7; 0],
+ data slave in [15; 8]), therefore data width must be lower than 8 bit
+ (even with ADC resolution 8 bit, higher width reachable by post processing:
+ oversampling, offset, ...). In register CDR2, data of master and slave are
+ alternatively set in full register width 32 bit, therefore no constraint on
+ data width. In case of usage with DMA, CDR generate ones transfer request
+ and CDR2 two transfer requests per conversion. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
+ * @{
+ */
+#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two
+ sampling phases: 1 ADC clock cycle */
+#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two
+ sampling phases: 2 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two
+ sampling phases: 3 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two
+ sampling phases: 4 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two
+ sampling phases: 5 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two
+ sampling phases: 6 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two
+ sampling phases: 7 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two
+ sampling phases: 8 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two
+ sampling phases: 9 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two
+ sampling phases: 10 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two
+ sampling phases: 11 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two
+ sampling phases: 12 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_13CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) /*!< ADC multimode delay between two
+ sampling phases: 13 ADC clock cycles */
+/**
+ * @}
+ */
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
+ * @{
+ */
+#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on
+ all STM32 devices) */
+#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on
+ all STM32 devices) */
+#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_CFGR1_fields ADCx CFGR fields
+ * @{
+ */
+#define ADC_CFGR1_FIELDS (ADC_CFGR1_AWD1CH | ADC_CFGR1_JAUTO | ADC_CFGR1_JAWD1EN |\
+ ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | \
+ ADC_CFGR1_JDISCEN | ADC_CFGR1_DISCNUM | ADC_CFGR1_DISCEN |\
+ ADC_CFGR1_AUTDLY | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |\
+ ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN |\
+ ADC_CFGR1_RES | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN )
+/**
+ * @}
+ */
+
+/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
+ * @{
+ */
+#define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
+ ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
+ ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
+ ADC_SMPR1_SMP0)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_CFGR1_fields_2 ADCx CFGR sub fields
+ * @{
+ */
+/* ADC_CFGR1 fields of parameters that can be updated when no conversion
+ (neither regular nor injected) is on-going */
+#define ADC_CFGR1_FIELDS_2 ((uint32_t)(ADC_CFGR1_DMNGT | ADC_CFGR1_AUTDLY))
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros
+ * @{
+ */
+#if defined(ADC_MULTIMODE_SUPPORT)
+
+/** @brief Force ADC instance in multimode mode independent (multimode disable).
+ * @note This macro must be used only in case of transition from multimode
+ * to mode independent and in case of unknown previous state,
+ * to ensure ADC configuration is in mode independent.
+ * @note Standard way of multimode configuration change is done from
+ * HAL ADC handle of ADC master using function
+ * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )".
+ * Usage of this macro is not the Standard way of multimode
+ * configuration and can lead to have HAL ADC handles status
+ * misaligned. Usage of this macro must be limited to cases
+ * mentioned above.
+ * @param __HANDLE__ ADC handle.
+ * @retval None
+ */
+#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \
+ LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in */
+/* code of final user. */
+
+/**
+ * @brief Test if conversion trigger of injected group is software start
+ * or external trigger.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (software start) or RESET (external trigger).
+ */
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
+ (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
+
+/**
+ * @brief Check if conversion is on going on regular or injected groups.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (conversion is on going) or RESET (no conversion is on going).
+ */
+#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \
+ (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \
+ ) ? RESET : SET)
+
+/**
+ * @brief Check if conversion is on going on injected group.
+ * @param __HANDLE__ ADC handle.
+ * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going)
+ */
+#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \
+ (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance))
+
+/**
+ * @brief Check whether or not ADC is independent.
+ * @param __HANDLE__ ADC handle.
+ * @note When multimode feature is not available, the macro always returns SET.
+ * @retval SET (ADC is independent) or RESET (ADC is not).
+ */
+#define ADC_IS_INDEPENDENT(__HANDLE__) \
+ ( ( ( ((__HANDLE__)->Instance) == ADC3) \
+ )? \
+ SET \
+ : \
+ RESET \
+ )
+
+/**
+ * @brief Set the selected injected Channel rank.
+ * @param __CHANNELNB__ Channel number.
+ * @param __RANKNB__ Rank number.
+ * @retval None
+ */
+#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) (((__CHANNELNB__)& ADC_CHANNEL_NUMBER_MASK) \
+ << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
+
+
+/**
+ * @brief Configure ADC discontinuous conversion mode for injected group
+ * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
+ * @retval None
+ */
+#define ADC_CFGR1_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__)\
+ ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR1_JDISCEN_Pos)
+
+/**
+ * @brief Configure ADC discontinuous conversion mode for regular group
+ * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
+ * @retval None
+ */
+#define ADC_CFGR1_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR1_DISCEN_Pos)
+
+/**
+ * @brief Configure the number of discontinuous conversions for regular group.
+ * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
+ * @retval None
+ */
+#define ADC_CFGR1_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__)\
+ (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR1_DISCNUM_Pos)
+
+/**
+ * @brief Configure the ADC auto delay mode.
+ * @param __AUTDLY__ Auto delay bit enable or disable.
+ * @retval None
+ */
+#define ADC_CFGR1_AUTODELAY(__AUTDLY__) ((__AUTDLY__) << ADC_CFGR1_AUTDLY_Pos)
+
+/**
+ * @brief Configure ADC continuous conversion mode.
+ * @param __CONTINUOUS_MODE__ Continuous mode.
+ * @retval None
+ */
+#define ADC_CFGR1_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR1_CONT_Pos)
+
+/**
+ * @brief Enable the ADC DMA continuous request.
+ * @param __DMACONTREQ_MODE__: DMA continuous request mode.
+ * @retval None
+ */
+#define ADC_CFGR1_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__))
+
+/**
+ * @brief Configure the channel number into offset OFRx register.
+ * @param __CHANNEL__ ADC Channel.
+ * @retval None
+ */
+#define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFCFGR1_OFFSET1_CH_Pos)
+
+/**
+ * @brief Configure calibration factor in differential mode to be set into calibration register.
+ * @param __CALIBRATION_FACTOR__ Calibration factor value.
+ * @retval None
+ */
+#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__)\
+ (((__CALIBRATION_FACTOR__)& (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) )\
+ << ADC_CALFACT_CALFACT_D_Pos)
+
+/**
+ * @brief Calibration factor in differential mode to be retrieved from calibration register.
+ * @param __CALIBRATION_FACTOR__ Calibration factor value.
+ * @retval None
+ */
+#define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos)
+
+/**
+ * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
+ * @param __THRESHOLD__ Threshold value.
+ * @retval None
+ */
+#define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL)
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Configure the ADC DMA continuous request for ADC multimode.
+ * @param __DMACONTREQ_MODE__ DMA continuous request mode.
+ * @retval None
+ */
+#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Shift the offset with respect to the selected ADC resolution.
+ * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
+ * If resolution 12 bits, no shift.
+ * If resolution 10 bits, shift of 2 ranks on the left.
+ * If resolution 8 bits, shift of 4 ranks on the left.
+ * If resolution 6 bits, shift of 6 ranks on the left.
+ * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 2)*2)).
+ * @param __HANDLE__ ADC handle
+ * @param __OFFSET__ Value to be shifted
+ * @retval None
+ */
+#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
+ (((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)>> 2UL)*2UL)))
+
+/**
+ * @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
+ * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
+ * If resolution 12 bits, no shift.
+ * If resolution 10 bits, shift of 2 ranks on the left.
+ * If resolution 8 bits, shift of 4 ranks on the left.
+ * If resolution 6 bits, shift of 6 ranks on the left.
+ * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 2)*2)).
+ * @param __HANDLE__ ADC handle
+ * @param __THRESHOLD__ Value to be shifted
+ * @retval None
+ */
+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
+ ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 2UL) * 2UL))
+
+/**
+ * @brief Clear Common Control Register.
+ * @param __HANDLE__ ADC handle.
+ * @retval None
+ */
+/**
+ * @brief Report common register to ADC1 and ADC2
+ * @param __HANDLE__: ADC handle
+ * @retval Common control register
+ */
+#define ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON)
+/**
+ * @brief Report common register to ADC3
+ * @param __HANDLE__: ADC handle
+ * @retval Common control register
+ */
+#define ADC3_COMMON_REGISTER(__HANDLE__) (ADC3_COMMON)
+
+/**
+ * @brief Report Master Instance
+ * @param __HANDLE__: ADC handle
+ * @note return same instance if ADC of input handle is independent ADC
+ * @retval Master Instance
+ */
+#define ADC_MASTER_REGISTER(__HANDLE__) \
+ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \
+ )? \
+ ((__HANDLE__)->Instance) \
+ : \
+ (ADC1) \
+ )
+
+/**
+ * @brief Check whether or not dual regular conversions are enabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions
+ * are enabled)
+ */
+#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \
+ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
+ )? \
+ ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \
+ : \
+ RESET \
+ )
+
+/**
+ * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle
+ * of ADC master
+ * @param __HANDLE__: ADC handle
+ * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)
+ */
+#define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
+ ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2) \
+ )? \
+ SET \
+ : \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
+ )
+
+/**
+ * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with
+ * dual regular conversions enabled)
+ */
+
+#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \
+ ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
+ )? \
+ SET \
+ : \
+ ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
+
+/**
+ * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with
+ * dual injected conversions enabled)
+ */
+
+#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \
+ ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
+ )? \
+ SET \
+ : \
+ ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
+
+#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) \
+ CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_PRESC | \
+ ADC_CCR_VBATEN | \
+ ADC_CCR_DUAL | \
+ ADC_CCR_DELAY | \
+ ADC_CCR_DAMDF | \
+ ADC_CCR_TSEN | \
+ ADC_CCR_VREFEN )
+
+/**
+ * @brief Set handle instance of the ADC slave associated to the ADC master.
+ * @param __HANDLE_MASTER__ ADC master handle.
+ * @param __HANDLE_SLAVE__ ADC slave handle.
+ * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC,
+ * __HANDLE_SLAVE__ instance is set to NULL.
+ * @retval None
+ */
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
+ ((((__HANDLE_MASTER__)->Instance == ADC1)) \
+ ? ((__HANDLE_SLAVE__)->Instance = ADC2) \
+ : ((__HANDLE_SLAVE__)->Instance = NULL))
+
+
+/**
+ * @brief Verify the ADC instance connected to the temperature sensor.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+ */
+#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || \
+ (((__HANDLE__)->Instance) == ADC2) )
+/**
+ * @brief Verify the ADC instance connected to the battery voltage VBAT.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+ */
+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) ||\
+ (((__HANDLE__)->Instance) == ADC2) )
+
+
+/**
+ * @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+ */
+#define ADC_VREFINT_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) ||\
+ (((__HANDLE__)->Instance) == ADC2) )
+
+/**
+ * @brief Verify the ADC instance connected to the internal VDDCore.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+ */
+#define ADC_VDDCORE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) ||\
+ (((__HANDLE__)->Instance) == ADC2) )
+
+/**
+ * @brief Verify the length of scheduled injected conversions group.
+ * @param __LENGTH__ number of programmed conversions.
+ * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or
+ * RESET (__LENGTH__ is null or too large)
+ */
+#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
+
+/**
+ * @brief Calibration factor value range verification.
+ * @param __CALIBRATION_FACTOR__ Calibration factor value.
+ * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
+ */
+#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
+
+
+/**
+ * @brief Verify the ADC channel setting.
+ * @param __HANDLE__ ADC handle.
+ * @param __CHANNEL__ programmed ADC channel.
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+ */
+#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \
+ ((__CHANNEL__) == ADC_CHANNEL_1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_2) || \
+ ((__CHANNEL__) == ADC_CHANNEL_3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_4) || \
+ ((__CHANNEL__) == ADC_CHANNEL_5) || \
+ ((__CHANNEL__) == ADC_CHANNEL_6) || \
+ ((__CHANNEL__) == ADC_CHANNEL_7) || \
+ ((__CHANNEL__) == ADC_CHANNEL_8) || \
+ ((__CHANNEL__) == ADC_CHANNEL_9) || \
+ ((__CHANNEL__) == ADC_CHANNEL_10) || \
+ ((__CHANNEL__) == ADC_CHANNEL_11) || \
+ ((__CHANNEL__) == ADC_CHANNEL_12) || \
+ ((__CHANNEL__) == ADC_CHANNEL_13) || \
+ ((__CHANNEL__) == ADC_CHANNEL_14) || \
+ ((__CHANNEL__) == ADC_CHANNEL_15) || \
+ ((__CHANNEL__) == ADC_CHANNEL_16) || \
+ ((__CHANNEL__) == ADC_CHANNEL_17) || \
+ ((__CHANNEL__) == ADC_CHANNEL_18) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VDDCORE) || \
+ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \
+ ((((__HANDLE__)->Instance) == ADC2) && \
+ (((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2) || \
+ ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2))))
+
+
+/**
+ * @brief Verify the ADC single-ended input mode setting.
+ * @param __SING_DIFF__ programmed channel setting.
+ * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
+ */
+#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) ((__SING_DIFF__) == ADC_SINGLE_ENDED)
+
+/**
+ * @brief Verify the ADC offset sign setting.
+ * @param __OFFSET_SIGN__ ADC offset sign.
+ * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid)
+ */
+#define IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__) (((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \
+ ((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE) )
+/**
+ * @brief Verify the ADC offset management setting.
+ * @param __OFFSET_NUMBER__ ADC offset management.
+ * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
+ */
+#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
+
+/**
+ * @brief Verify the ADC injected channel setting.
+ * @param __CHANNEL__ programmed ADC injected channel.
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+ */
+#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
+ ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
+ ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
+ ((__CHANNEL__) == ADC_INJECTED_RANK_4) )
+
+/**
+ * @brief Verify the ADC injected conversions external trigger.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __INJ_TRIG_SOURCE__ programmed ADC injected conversions external trigger.
+ * @retval SET (__INJ_TRIG_SOURCE__ is a valid value) or RESET (__INJ_TRIG_SOURCE__ is invalid)
+ */
+#define IS_ADC_EXTTRIGINJEC(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
+ (((__INJ_TRIG_SOURCE__) == ADC_INJECTED_SOFTWARE_START) \
+ || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T1_CC4) \
+ || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T2_CC1) \
+ || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T3_CC4) \
+ || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) \
+ || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T3_CC3) \
+ || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T3_CC1) \
+ || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_LPTIM1_CH2) \
+ || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_LPTIM2_CH2) \
+ || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_LPTIM3_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_LPTIM4_OUT) \
+ )
+
+/**
+ * @brief Verify the ADC edge trigger setting for injected group.
+ * @param __EDGE__ programmed ADC edge trigger setting.
+ * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
+ */
+#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Verify the ADC multimode setting.
+ * @param __MODE__ programmed ADC multimode setting.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
+ ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_INTERL) || \
+ ((__MODE__) == ADC_DUALMODE_ALTERTRIG) )
+
+/**
+ * @brief Verify the ADC dual data mode setting.
+ * @param MODE: programmed ADC dual mode setting.
+ * @retval SET (MODE is valid) or RESET (MODE is invalid)
+ */
+#define IS_ADC_DUAL_DATA_MODE(MODE) (((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED) || \
+ ((MODE) == ADC_DUALMODEDATAFORMAT_32_BIT) || \
+ ((MODE) == ADC_DUALMODEDATAFORMAT_8_BIT) )
+
+/**
+ * @brief Verify the ADC multimode delay setting.
+ * @param __DELAY__ programmed ADC multimode delay setting.
+ * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
+ */
+#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) )
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Verify the ADC analog watchdog setting.
+ * @param __WATCHDOG__ programmed ADC analog watchdog setting.
+ * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
+ */
+#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
+ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
+ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) )
+
+/**
+ * @brief Verify the ADC analog watchdog mode setting.
+ * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
+ * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
+ */
+#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)|| \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
+
+/**
+ * @brief Verify the ADC analog watchdog filtering setting.
+ * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting.
+ * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid)
+ */
+#define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__) \
+ (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES) || \
+ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES) )
+
+
+/**
+ * @brief Verify the ADC conversion (regular or injected or both).
+ * @param __CONVERSION__ ADC conversion group.
+ * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
+ */
+#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \
+ ((__CONVERSION__) == ADC_INJECTED_GROUP) || \
+ ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) )
+
+/**
+ * @brief Verify the ADC event type.
+ * @param __EVENT__ ADC event.
+ * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
+ */
+#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
+ ((__EVENT__) == ADC_AWD_EVENT) || \
+ ((__EVENT__) == ADC_AWD2_EVENT) || \
+ ((__EVENT__) == ADC_AWD3_EVENT) || \
+ ((__EVENT__) == ADC_OVR_EVENT) )
+
+/**
+ * @brief Verify the ADC oversampling ratio.
+ * @param __RATIO__: programmed ADC oversampling ratio.
+ * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
+ */
+#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) >= 1UL) && ((__RATIO__) <= 1024UL))
+
+/**
+ * @brief Verify the ADC oversampling shift.
+ * @param __SHIFT__ programmed ADC oversampling shift.
+ * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
+ */
+#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_9 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_10 ))
+
+/**
+ * @brief Verify the ADC oversampling triggered mode.
+ * @param __MODE__ programmed ADC oversampling triggered mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
+ ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
+
+/**
+ * @brief Verify the ADC oversampling regular conversion resumed or continued mode.
+ * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
+ ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADCEx_Exported_Functions_Group1
+ * @{
+ */
+/* IO operation functions *****************************************************/
+
+/* ADC calibration */
+
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
+uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
+ uint32_t CalibrationFactor);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/* ADC multimode */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
+uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
+void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
+int32_t HAL_ADCEx_InjectedGetSignedValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
+void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
+void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
+void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
+
+/* ADC group regular conversions stop */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
+#if defined(ADC_MULTIMODE_SUPPORT)
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADCEx_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
+ const ADC_InjectionConfTypeDef *pConfigInjected);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc,
+ const ADC_MultiModeTypeDef *pMultimode);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U3xx_HAL_ADC_EX_H */
diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_ccb.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_ccb.h
new file mode 100644
index 0000000000..dd3d417aa3
--- /dev/null
+++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_ccb.h
@@ -0,0 +1,309 @@
+/**
+ ******************************************************************************
+ * @file stm32u3xx_hal_ccb.h
+ * @author MCD Application Team
+ * @brief Header file of CCB HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U3xx_HAL_CCB_H
+#define STM32U3xx_HAL_CCB_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u3xx_hal_def.h"
+
+/** @addtogroup STM32U3xx_HAL_Driver
+ * @{
+ */
+#if defined(CCB) && defined(HAL_CCB_MODULE_ENABLED)
+/** @addtogroup CCB
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CCB_Exported_Types CCB Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL CCB Handle Structure definition
+ */
+typedef struct
+{
+ CCB_TypeDef *Instance; /*!< CCB registers base address */
+ __IO uint32_t State; /*!< Global state of the CCB HAL driver */
+#if !defined(GENERATOR_C7AMBA_CCB_V1_0)
+ __IO uint32_t RNGState; /*!< Internal state of the RNG instance */
+ __IO uint32_t PKAState; /*!< Internal state of the PKA instance */
+ __IO uint32_t SAESState; /*!< Internal state of the SAES instance */
+#endif /* (GENERATOR_C7AMBA_CCB_V1_0) */
+ __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver error */
+} CCB_HandleTypeDef;
+
+/** @brief CCB Wrapping Key definition
+ */
+typedef struct
+{
+ uint32_t WrappingKeyType; /*!< This parameter can be value of @ref CCB_WrappingKeyTypeDef */
+ uint32_t AES_Algorithm; /*!< Used only when wrappingkey type is HAL_CCB_USER_KEY_WRAPPED,
+ AES Algorithm. This parameter can be a value of
+ @ref CCB_AES_Algorithm_Mode */
+ uint32_t *pInitVect; /*!< Used only when wrappingkey type is HAL_CCB_USER_KEY_WRAPPED,
+ Pointer to the initialization vector, counter with CBC Algorithm */
+ uint32_t *pUserWrappedWrappingKey; /*!< Used only when wrappingkey type is HAL_CCB_USER_KEY_WRAPPED,
+ Pointer to the wrapped wrapping Key */
+} CCB_WrappingKeyTypeDef;
+
+/**
+ * @brief CCB ECDSA and ECC scalar Multiplication curve parameters
+ */
+typedef struct
+{
+ uint32_t primeOrderSizeByte; /*!< Number of element in primeOrder array in byte*/
+ uint32_t modulusSizeByte; /*!< Number of element in modulus array in byte */
+ uint32_t coefSignA; /*!< Curve coefficient a sign */
+ const uint8_t *pAbsCoefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
+ const uint8_t *pCoefB; /*!< Pointer to B coefficient (Array of modulusSize elements) */
+ const uint8_t *pModulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
+ const uint8_t *pPrimeOrder; /*!< Pointer to order of the curve n (Array of primeOrderSize elements) */
+ const uint8_t *pPointX; /*!< Pointer to curve base point xG (Array of modulusSize elements) */
+ const uint8_t *pPointY; /*!< Pointer to curve base point yG (Array of modulusSize elements) */
+} CCB_ECDSACurveParamTypeDef, CCB_ECCMulCurveParamTypeDef;
+
+/** @brief CCB ECDSA Key Blob definition
+ */
+typedef struct
+{
+ uint32_t *pIV; /*!< Pointer to the Initial Vector */
+ uint32_t *pTag; /*!< Pointer to the Tag */
+ uint32_t *pWrappedKey; /*!< Pointer to the Wrapped Key */
+} CCB_ECDSAKeyBlobTypeDef, CCB_ECCMulKeyBlobTypeDef;
+
+/**
+ * @brief CCB ECDSA Signature definition
+ */
+typedef struct
+{
+ uint8_t *pRSign; /*!< Pointer to signature part r (Array of modulusSize elements) */
+ uint8_t *pSSign; /*!< Pointer to signature part s (Array of modulusSize elements) */
+} CCB_ECDSASignTypeDef;
+
+/**
+ * @brief CCB ECC scalar multiplication point definition
+ */
+typedef struct
+{
+ uint8_t *pPointX; /*!< Pointer to point P coordinate xP */
+ uint8_t *pPointY; /*!< Pointer to point P coordinate yP */
+} CCB_ECCMulPointTypeDef;
+
+/**
+ * @brief CCB RSA clear key definition
+ */
+typedef struct
+{
+ uint8_t *pExp; /*!< Pointer to Exponent */
+ uint8_t *pPhi; /*!< Pointer to Phi value */
+} CCB_RSAClearKeyTypeDef;
+
+/**
+ * @brief CCB RSA Modular exponatiation parameters
+ */
+typedef struct
+{
+ uint32_t expSizeByte; /*!< Number of element in pExp and pMontgomeryParam arrays */
+ uint32_t modulusSizeByte; /*!< Number of element in modulus array */
+ const uint8_t *pMod; /*!< Pointer to modulus (Array of OpSize elements) */
+} CCB_RSAParamTypeDef;
+
+/**
+ * @brief CCB RSA Modular exponatiation Key Blob definition
+ */
+typedef struct
+{
+ uint32_t *pIV; /*!< Pointer to the Initial Vector */
+ uint32_t *pTag; /*!< Pointer to the Tag */
+ uint32_t *pWrappedExp; /*!< Pointer to the Wrapped Exponent */
+ uint32_t *pWrappedPhi; /*!< Pointer to the Wrapped Phi */
+} CCB_RSAKeyBlobTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CCB_Exported_Constants CCB Exported Constants
+ * @{
+ */
+
+/** @defgroup CCB_State CCB State
+ * @{
+ */
+#define HAL_CCB_STATE_RESET (0x00000000U) /*!< CCB not yet initialized or disabled */
+#define HAL_CCB_STATE_READY (0xDA5DA605U) /*!< CCB is ready for operation */
+#define HAL_CCB_STATE_BUSY (0x00000002U) /*!< CCB BUSY, internal processing is ongoing */
+#define HAL_CCB_STATE_ERROR (0x00000003U) /*!< Blocking error, driver should be re-initialized */
+
+/**
+ * @}
+ */
+
+/** @defgroup CCB_AES_Algorithm_Mode AES Algorithm Mode
+ * @{
+ */
+#define CCB_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */
+#define CCB_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
+
+/**
+ * @}
+ */
+
+/** @defgroup CCB_ErrorCode CCB Error Code
+ * @{
+ */
+#define HAL_CCB_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_CCB_ERROR_INVALID_PARAM (0x00000001U) /*!< Invalid parameters error */
+#define HAL_CCB_ERROR_OPERATION (0x00000002U) /*!< Operation error */
+#define HAL_CCB_ERROR_SAES_TAMP (0x00000010U) /*!< SAES TAMP ERROR */
+#define HAL_CCB_ERROR_RNG_TAMP (0x00000020U) /*!< RNG TAMP ERROR */
+#define HAL_CCB_ERROR_PKAREG_TAMP (0x00000040U) /*!< PKA Register TAMP ERROR */
+#define HAL_CCB_ERROR_PKAOPR_TAMP (0x00000080U) /*!< PKA Operation TAMP ERROR */
+#define HAL_CCB_ERROR_PKARAM_ERASE (0x00000100U) /*!< PKA RAM erase ERROR */
+
+/**
+ * @}
+ */
+
+/** @defgroup CCB_WrappingKeyTypeDef CCB Wrapping Key definition
+ * @{
+ */
+#define HAL_CCB_USER_KEY_WRAPPED (0x00000000U) /*!< the wrapped key is a SW user key */
+#define HAL_CCB_USER_KEY_HW AES_CR_KEYSEL_0 /*!< Hardware key : derived hardware
+ unique key (DHUK 256-bit) */
+#define HAL_CCB_USER_KEY_HSW AES_CR_KEYSEL_2 /*!< DHUK XOR BHK Hardware unique
+ key XOR software key */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CCB_Exported_Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+/** @addtogroup CCB_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_CCB_Init(CCB_HandleTypeDef *hccb);
+void HAL_CCB_MspInit(CCB_HandleTypeDef *hccb);
+HAL_StatusTypeDef HAL_CCB_DeInit(CCB_HandleTypeDef *hccb);
+void HAL_CCB_MspDeInit(CCB_HandleTypeDef *hccb);
+
+/**
+ * @}
+ */
+
+/* Handler functions ********************************/
+/** @addtogroup CCB_Exported_Functions_Group2
+ * @{
+ */
+uint32_t HAL_CCB_GetError(const CCB_HandleTypeDef *hccb);
+uint32_t HAL_CCB_GetState(const CCB_HandleTypeDef *hccb);
+uint32_t HAL_CCB_GetOperationError(const CCB_HandleTypeDef *hccb);
+
+/**
+ * @}
+ */
+
+/* Operation functions *****************************************************/
+/** @addtogroup CCB_Exported_Functions_Group3
+ * @{
+ */
+HAL_StatusTypeDef HAL_CCB_ECDSA_WrapSymmetricKey(CCB_HandleTypeDef *hccb, const uint32_t *pClearAESKey,
+ CCB_WrappingKeyTypeDef *pWrappingKey);
+HAL_StatusTypeDef HAL_CCB_ECC_WrapSymmetricKey(CCB_HandleTypeDef *hccb, const uint32_t *pClearAESKey,
+ CCB_WrappingKeyTypeDef *pWrappingKey);
+HAL_StatusTypeDef HAL_CCB_RSA_WrapSymmetricKey(CCB_HandleTypeDef *hccb, const uint32_t *pClearAESKey,
+ CCB_WrappingKeyTypeDef *pWrappingKey);
+
+HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDSACurveParamTypeDef *pCurveParam,
+ const uint8_t *pClearPrivateKey,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ const CCB_ECDSAKeyBlobTypeDef *pWrappedPrivateKeyBlob);
+
+HAL_StatusTypeDef HAL_CCB_ECDSA_GenerateWrapPrivateKey(CCB_HandleTypeDef *hccb,
+ CCB_ECDSACurveParamTypeDef *pCurveParam,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ CCB_ECDSAKeyBlobTypeDef *pWrappedPrivateKeyBlob);
+
+HAL_StatusTypeDef HAL_CCB_ECDSA_Sign(CCB_HandleTypeDef *hccb, CCB_ECDSACurveParamTypeDef *pCurveParam,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ CCB_ECDSAKeyBlobTypeDef *pWrappedPrivateKeyBlob, const uint8_t *pHash,
+ CCB_ECDSASignTypeDef *pSignature);
+HAL_StatusTypeDef HAL_CCB_ECDSA_ComputePublicKey(CCB_HandleTypeDef *hccb, CCB_ECDSACurveParamTypeDef *pCurveParam,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ CCB_ECDSAKeyBlobTypeDef *pWrappedPrivateKeyBlob,
+ CCB_ECCMulPointTypeDef *pPublicKey);
+
+HAL_StatusTypeDef HAL_CCB_ECC_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECCMulCurveParamTypeDef *pCurveParam,
+ const uint8_t *pClearPrivateKey,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ CCB_ECCMulKeyBlobTypeDef *pWrappedPrivateKeyBlob);
+
+HAL_StatusTypeDef HAL_CCB_ECC_GenerateWrapPrivateKey(CCB_HandleTypeDef *hccb,
+ CCB_ECCMulCurveParamTypeDef *pCurveParam,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ CCB_ECCMulKeyBlobTypeDef *pWrappedPrivateKeyBlob);
+
+HAL_StatusTypeDef HAL_CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_ECCMulCurveParamTypeDef *pCurveParam,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ CCB_ECCMulKeyBlobTypeDef *pWrappedPrivateKeyBlob,
+ CCB_ECCMulPointTypeDef *pInputPoint,
+ CCB_ECCMulPointTypeDef *pOutputPoint);
+
+HAL_StatusTypeDef HAL_CCB_RSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_RSAParamTypeDef *pParam,
+ const CCB_RSAClearKeyTypeDef *pRSAClearPrivateKey,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ CCB_RSAKeyBlobTypeDef *pWrappedPrivateKeyBlob);
+HAL_StatusTypeDef HAL_CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_RSAParamTypeDef *pParam,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ CCB_RSAKeyBlobTypeDef *pWrappedPrivateKeyBlob,
+ const uint8_t *pOperand, uint8_t *pModularExp);
+
+/* Callback functions in non-blocking modes ***********************************/
+void HAL_CCB_IntrusionCallback(CCB_HandleTypeDef *hccb);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(CCB) && defined(HAL_CCB_MODULE_ENABLED) */
+/**
+ * @}
+ */
+#endif /* STM32U3xx_HAL_CCB_H */
diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_comp.h b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_comp.h
new file mode 100644
index 0000000000..69d41ba02d
--- /dev/null
+++ b/system/Drivers/STM32U3xx_HAL_Driver/Inc/stm32u3xx_hal_comp.h
@@ -0,0 +1,810 @@
+/**
+ ******************************************************************************
+ * @file stm32u3xx_hal_comp.h
+ * @author MCD Application Team
+ * @brief Header file of COMP HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U3xx_HAL_COMP_H
+#define STM32U3xx_HAL_COMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u3xx_hal_def.h"
+#include "stm32u3xx_ll_exti.h"
+
+/** @addtogroup STM32U3xx_HAL_Driver
+ * @{
+ */
+#if defined (COMP1) || defined (COMP2)
+
+/** @addtogroup COMP
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup COMP_Exported_Types COMP Exported Types
+ * @{
+ */
+
+/**
+ * @brief COMP Init structure definition
+ */
+typedef struct
+{
+
+ uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances
+ (2 consecutive instances odd and even COMP
+
+![ST logo]()
+
+
+Release Notes for +STM32U3xx CMSIS
+Copyright © 2024 STMicroelectronics
+
Purpose
+This driver provides the CMSIS device for the STM32U3xx product. This +covers
+-
+
- STM32U375xx devices +
- STM32U385xx devices +
This driver is composed of the description of the registers under +“Include” directory.
+Various template files are provided to easily build an application. +They can be adapted to fit applications requirements.
+-
+
- Templates/system_stm32u3xx.c contains the initialization code +referred as SystemInit. +
- Startup files are provided as example for EWARM©, MDK-ARM©, +STM32CubeIDE©. +
- Linker files are provided as example for EWARM©, MDK-ARM©, +STM32CubeIDE©. +
Update history
+
+
+
+
+
+
+Maintenance Release
+-
+
- Maintenance release of CMSIS for STM32U3xx firmware +package supporting STM32U385xx/STM32U375xx devices +
Contents
+-
+
- Fix PWR_I3CPUCR2_PG14_I3CPU_Pos value +
- Suppress unused bit +
- Minor fix on comments +
Known Limitations
+-
+
- None +
+
+
+
+
+
+First Release
+-
+
- First official release of CMSIS for STM32U3xx +firmware package supporting STM32U385xx/STM32U375xx +devices +
Contents
+-
+
- First official release of CMSIS devices drivers
+
-
+
- Support of STM32U385xx/STM32U375xx devices +
+
Known Limitations
+-
+
- None +
+
+
+
+
+
+
diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal.c
new file mode 100644
index 0000000000..b9c35490f5
--- /dev/null
+++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal.c
@@ -0,0 +1,1067 @@
+/**
+ ******************************************************************************
+ * @file stm32u3xx_hal.c
+ * @author MCD Application Team
+ * @brief HAL module driver.
+ * This is the common part of the HAL initialization
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The common HAL driver contains a set of generic and common APIs that can be
+ used by the PPP peripheral drivers and the user to start using the HAL.
+ [..]
+ The HAL contains two APIs' categories:
+ (+) Common HAL APIs
+ (+) Services HAL APIs
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u3xx_hal.h"
+
+/** @addtogroup STM32U3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL HAL
+ * @brief HAL module driver
+ * @{
+ */
+
+#ifdef HAL_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+
+/* Private define ------------------------------------------------------------*/
+/** @defgroup HAL_Private_Defines HAL Private Defines
+ * @{
+ */
+#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms (to be confirmed) */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Exported variables --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Variables HAL Exported Variables
+ * @{
+ */
+__IO uint32_t uwTick;
+uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+ * @{
+ */
+
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initializes the Flash interface the NVIC allocation and initial clock
+ configuration. It initializes the systick also when timeout is needed
+ and the backup domain when enabled.
+ (+) De-Initializes common part of the HAL.
+ (+) Configure The time base source to have 1ms time base with a dedicated
+ Tick interrupt priority.
+ (++) SysTick timer is used by default as source of time base, but user
+ can eventually implement his proper time base source (a general purpose
+ timer for example or other time source), keeping in mind that Time base
+ duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+ handled in milliseconds basis.
+ (++) Time base configuration function (HAL_InitTick ()) is called automatically
+ at the beginning of the program after reset by HAL_Init() or at any time
+ when clock is configured, by HAL_RCC_ClockConfig().
+ (++) Source of time base is configured to generate interrupts at regular
+ time intervals. Care must be taken if HAL_Delay() is called from a
+ peripheral ISR process, the Tick interrupt line must have higher priority
+ (numerically lower) than the peripheral interrupt. Otherwise the caller
+ ISR process will be blocked.
+ (++) functions affecting time base configurations are declared as __weak
+ to make override possible in case of other implementations in user file.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the Flash prefetch, the time base source, NVIC and any required global low
+ * level hardware by calling the HAL_MspInit() callback function to be optionally defined
+ * in user file stm32u3xx_hal_msp.c.
+ *
+ * @note HAL_Init() function is called at the beginning of program after reset and before
+ * the clock configuration.
+ *
+ * @note In the default implementation the System Timer (SysTick) is used as source of time base.
+ * The SysTick configuration is based on MSI clock, as MSI is the clock
+ * used after a system Reset and the NVIC configuration is set to Priority group 4.
+ * Once done, time base tick starts incrementing: the tick variable counter is incremented
+ * each 1ms in the SysTick_Handler() interrupt handler.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_Init(void)
+{
+ /* Configure Flash prefetch */
+#if (PREFETCH_ENABLE != 0U)
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+ /* Set Interrupt Group Priority */
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+ /* Ensure time base clock coherency */
+ SystemCoreClockUpdate();
+
+ /* Select HCLK as SysTick clock source */
+ HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
+
+ /* Initialize 1ms tick time base (default SysTick based on MSI clock after Reset) */
+ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Init the low level hardware */
+ HAL_MspInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief This function de-Initializes common part of the HAL and stops the systick.
+ * This function is optional.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+ /* Reset of all peripherals */
+ __HAL_RCC_AHB1_FORCE_RESET();
+ __HAL_RCC_AHB1_RELEASE_RESET();
+
+ __HAL_RCC_AHB2_FORCE_RESET();
+ __HAL_RCC_AHB2_RELEASE_RESET();
+
+ __HAL_RCC_APB1_FORCE_RESET();
+ __HAL_RCC_APB1_RELEASE_RESET();
+
+ __HAL_RCC_APB2_FORCE_RESET();
+ __HAL_RCC_APB2_RELEASE_RESET();
+
+ __HAL_RCC_APB3_FORCE_RESET();
+ __HAL_RCC_APB3_RELEASE_RESET();
+
+ /* De-Init the low level hardware */
+ HAL_MspDeInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the MSP.
+ * @retval None
+ */
+__weak void HAL_MspInit(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the MSP.
+ * @retval None
+ */
+__weak void HAL_MspDeInit(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function configures the source of the time base.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
+ * @note In the default implementation, SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals.
+ * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+ * The SysTick interrupt must have higher priority (numerically lower)
+ * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+ * The function is declared as __weak to be overwritten in case of other
+ * implementation in user file.
+ * @param TickPriority: Tick interrupt priority.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ uint32_t ticknumber = 0U;
+ uint32_t systicksel;
+
+ /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
+ if ((uint32_t)uwTickFreq == 0UL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check Clock source to calculate the tickNumber */
+ if(READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) == SysTick_CTRL_CLKSOURCE_Msk)
+ {
+ /* HCLK selected as SysTick clock source */
+ ticknumber = SystemCoreClock / (1000UL / (uint32_t)uwTickFreq);
+ }
+ else
+ {
+ systicksel = __HAL_RCC_GET_SYSTICK_SOURCE();
+ switch (systicksel)
+ {
+ /* HCLK_DIV8 selected as SysTick clock source */
+ case RCC_SYSTICKCLKSOURCE_HCLK_DIV8:
+ /* Calculate tick value */
+ ticknumber = (SystemCoreClock / (8000UL / (uint32_t)uwTickFreq));
+ break;
+
+ /* LSI selected as SysTick clock source */
+ case RCC_SYSTICKCLKSOURCE_LSI:
+ /* Calculate tick value */
+ ticknumber = (LSI_VALUE / (1000UL / (uint32_t)uwTickFreq));
+ break;
+
+ /* LSE selected as SysTick clock source */
+ case RCC_SYSTICKCLKSOURCE_LSE:
+ /* Calculate tick value */
+ ticknumber = (LSE_VALUE / (1000UL / (uint32_t)uwTickFreq));
+ break;
+
+ default:
+ /* Nothing to do */
+ break;
+ }
+ }
+
+ /* Configure the SysTick */
+ if (HAL_SYSTICK_Config(ticknumber) > 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Configure the SysTick IRQ priority */
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ uwTickPrio = TickPriority;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Group2 HAL Control functions
+ * @brief HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Provide a tick value in millisecond
+ (+) Provide a blocking delay in millisecond
+ (+) Suspend the time base source interrupt
+ (+) Resume the time base source interrupt
+ (+) Get the HAL API driver version
+ (+) Get the device identifier
+ (+) Get the device revision identifier
+ (+) Enable/Disable Debug module during SLEEP mode
+ (+) Enable/Disable Debug module during STOP mode
+ (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function is called to increment a global variable "uwTick"
+ * used as application time base.
+ * @note In the default implementation, this variable is incremented each 1ms
+ * in SysTick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_IncTick(void)
+{
+ uwTick += (uint32_t)uwTickFreq;
+}
+
+/**
+ * @brief Provides a tick value in millisecond.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval tick value
+ */
+__weak uint32_t HAL_GetTick(void)
+{
+ return uwTick;
+}
+
+/**
+ * @brief This function returns a tick priority.
+ * @retval tick priority
+ */
+uint32_t HAL_GetTickPrio(void)
+{
+ return uwTickPrio;
+}
+
+/**
+ * @brief Set new tick Freq.
+ * @retval Status
+ */
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_TickFreqTypeDef prevTickFreq;
+
+ assert_param(IS_TICKFREQ(Freq));
+
+ if (uwTickFreq != Freq)
+ {
+
+ /* Back up uwTickFreq frequency */
+ prevTickFreq = uwTickFreq;
+
+ /* Update uwTickFreq global variable used by HAL_InitTick() */
+ uwTickFreq = Freq;
+
+ /* Apply the new tick Freq */
+ status = HAL_InitTick(uwTickPrio);
+ if (status != HAL_OK)
+ {
+ /* Restore previous tick frequency */
+ uwTickFreq = prevTickFreq;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Return tick frequency.
+ * @retval Tick frequency.
+ * Value of @ref HAL_TickFreqTypeDef.
+ */
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+{
+ return uwTickFreq;
+}
+
+/**
+ * @brief This function provides minimum delay (in milliseconds) based
+ * on variable incremented.
+ * @note In the default implementation , SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals where uwTick
+ * is incremented.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @param Delay specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+__weak void HAL_Delay(uint32_t Delay)
+{
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t wait = Delay;
+
+ /* Add a freq to guarantee minimum wait */
+ if (wait < HAL_MAX_DELAY)
+ {
+ wait += (uint32_t)(uwTickFreq);
+ }
+
+ while ((HAL_GetTick() - tickstart) < wait)
+ {
+ }
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+ * is called, the SysTick interrupt will be disabled and so Tick increment
+ * is suspended.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_SuspendTick(void)
+{
+ /* Disable SysTick Interrupt */
+ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+ * is called, the SysTick interrupt will be enabled and so Tick increment
+ * is resumed.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_ResumeTick(void)
+{
+ /* Enable SysTick Interrupt */
+ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+ * @brief Returns the HAL revision
+ * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+ */
+uint32_t HAL_GetHalVersion(void)
+{
+ return __STM32U3xx_HAL_VERSION;
+}
+
+/**
+ * @brief Returns the device revision identifier.
+ * @retval Device revision identifier
+ */
+uint32_t HAL_GetREVID(void)
+{
+ return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16);
+}
+
+/**
+ * @brief Returns the device identifier.
+ * @retval Device identifier
+ */
+uint32_t HAL_GetDEVID(void)
+{
+ return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
+}
+
+/**
+ * @brief Return the first word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw0(void)
+{
+ return (READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+ * @brief Return the second word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw1(void)
+{
+ return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+ * @brief Return the third word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw2(void)
+{
+ return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
+ * @brief HAL Debug functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL Debug functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes
+ (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable the Debug Module during STOP0/STOP1/STOP2 modes.
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStopMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Disable the Debug Module during STOP0/STOP1/STOP2 modes.
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStopMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Enable the Debug Module during STANDBY mode.
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Disable the Debug Module during STANDBY mode.
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions
+ * @brief HAL SYSCFG configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL SYSCFG configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the Voltage reference buffer
+ (+) Enable/Disable the Voltage reference buffer
+ (+) Enable/Disable the I/O analog switch voltage booster
+ (+) Configure/Enable/Disable the compensation cell (VDD,VDDIO2)
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the internal voltage reference buffer voltage scale.
+ * @param VoltageScaling: specifies the output voltage to achieve
+ * This parameter can be one of the following values:
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 1.5 V.
+ * This requires VDDA equal to or higher than 1.8 V.
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT1 around 1.8 V.
+ * This requires VDDA equal to or higher than 2.1 V.
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT1 around 2.048 V.
+ * This requires VDDA equal to or higher than 2.4 V.
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT1 around 2.5 V.
+ * This requires VDDA equal to or higher than 2.8 V.
+ * @retval None
+ */
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
+
+ MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
+}
+
+/**
+ * @brief Configure the internal voltage reference buffer high impedance mode.
+ * @param Mode: specifies the high impedance mode
+ * This parameter can be one of the following values:
+ * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
+ * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
+ * @retval None
+ */
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
+
+ MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
+}
+
+/**
+ * @brief Tune the Internal Voltage Reference buffer (VREFBUF).
+ * @retval None
+ */
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
+
+ MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
+}
+
+/**
+ * @brief Enable the Internal Voltage Reference buffer (VREFBUF).
+ * @retval HAL_OK/HAL_TIMEOUT
+ */
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
+{
+ uint32_t tickstart;
+
+ SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* VRR detection is only available when bit HIZ is cleared */
+ if (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ) == 0UL)
+ {
+ /* Wait for VRR bit */
+ while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the Internal Voltage Reference buffer (VREFBUF).
+ *
+ * @retval None
+ */
+void HAL_SYSCFG_DisableVREFBUF(void)
+{
+ CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+
+/**
+ * @brief Enable the I/O analog switch voltage booster
+ *
+ * @retval None
+ */
+void HAL_SYSCFG_EnableIOAnalogBooster(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+ * @brief Disable the I/O analog switch voltage booster
+ *
+ * @retval None
+ */
+void HAL_SYSCFG_DisableIOAnalogBooster(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+ * @brief Enable the I/O analog switch voltage booster
+ *
+ * @retval None
+ */
+void HAL_SYSCFG_EnableIOAnalogSwitchVdd(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
+}
+
+/**
+ * @brief Disable the I/O analog switch voltage booster
+ *
+ * @retval None
+ */
+void HAL_SYSCFG_DisableIOAnalogSwitchVdd(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
+}
+
+/**
+ * @brief Enable the compensation cell
+ * @param Selection specifies the concerned compensation cell
+ * This parameter can the combination of the following values:
+ * @arg SYSCFG_IO_VDD_CELL Compensation cell for the I/O supplied by vdd
+ * @arg SYSCFG_IO_VDDIO2_CELL Compensation cell for the I/O supplied by vddio2
+ * @note The vdd compensation cell can be used only when the device supply
+ * voltage ranges from 1.71 to 3.6 V
+ * @retval None
+ */
+void HAL_SYSCFG_EnableCompensationCell(uint32_t Selection)
+{
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_COMPENSATION_CELL(Selection));
+
+ SET_BIT(SYSCFG->CCCSR, Selection);
+}
+
+/**
+ * @brief Disable the compensation cell
+ * @param Selection specifies the concerned compensation cell
+ * This parameter can the combination of the following values:
+ * @arg SYSCFG_IO_VDD_CELL Compensation cell for the I/O supplied by vdd
+ * @arg SYSCFG_IO_VDDIO2_CELL Compensation cell for the I/O supplied by vddio2
+ * @note The vdd compensation cell can be used only when the device supply
+ * voltage ranges from 1.71 to 3.6 V
+ * @retval None
+ */
+void HAL_SYSCFG_DisableCompensationCell(uint32_t Selection)
+{
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_COMPENSATION_CELL(Selection));
+
+ CLEAR_BIT(SYSCFG->CCCSR, Selection);
+}
+
+/**
+ * @brief Get the compensation cell ready status
+ * @param Selection specifies the concerned compensation cell
+ * This parameter can one of the following values:
+ * @arg SYSCFG_IO_VDD_CELL Compensation cell for the I/O supplied by vdd
+ * @arg SYSCFG_IO_VDDIO2_CELL Compensation cell for the I/O supplied by vddio2
+ * @retval Ready status (1 or 0)
+ */
+uint32_t HAL_SYSCFG_GetCompensationCellReadyStatus(uint32_t Selection)
+{
+ uint32_t flag;
+
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_COMPENSATION_CELL(Selection));
+
+ if (Selection == SYSCFG_IO_VDD_CELL)
+ {
+ flag = (((SYSCFG->CCCSR & SYSCFG_CCCSR_RDY1) == 0U) ? 0UL : 1UL);
+ }
+ else /* SYSCFG_IO_VDDIO2_CELL */
+ {
+ flag = (((SYSCFG->CCCSR & SYSCFG_CCCSR_RDY2) == 0U) ? 0UL : 1UL);
+ }
+
+ return flag;
+}
+
+/**
+ * @brief Configure the code selection for the compensation cell
+ * @param Selection specifies the concerned compensation cell
+ * This parameter can one of the following values:
+ * @arg SYSCFG_IO_VDD_CELL Compensation cell for the I/O supplied by vdd
+ * @arg SYSCFG_IO_VDDIO2_CELL Compensation cell for the I/O supplied by vddio2
+ * @param Code code selection to be applied for the I/O compensation cell
+ * This parameter can be one of the following values:
+ * @arg SYSCFG_IO_CELL_CODE Code from the cell (available in the SYSCFG_CCVR)
+ * @arg SYSCFG_IO_REGISTER_CODE Code from the compensation cell code register (SYSCFG_CCCR)
+ * @param NmosValue In case SYSCFG_IO_REGISTER_CODE is selected, it provides the Nmos value
+ * to apply in range 0 to 15 else this parameter is not used
+ * @param PmosValue In case SYSCFG_IO_REGISTER_CODE is selected, it provides the Pmos value
+ * to apply in range 0 to 15 else this parameter is not used
+ * @retval None
+ */
+void HAL_SYSCFG_ConfigCompensationCell(uint32_t Selection, uint32_t Code, uint32_t NmosValue, uint32_t PmosValue)
+{
+ uint32_t offset;
+
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_COMPENSATION_CELL(Selection));
+ assert_param(IS_SYSCFG_IO_COMPENSATION_CODE(Code));
+
+ if (Code == SYSCFG_IO_REGISTER_CODE)
+ {
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_IO_COMPENSATION_CELL_NMOS_VALUE(NmosValue));
+ assert_param(IS_SYSCFG_IO_COMPENSATION_CELL_PMOS_VALUE(PmosValue));
+
+ offset = ((Selection == SYSCFG_IO_VDD_CELL) ? 0U : 8U);
+
+ MODIFY_REG(SYSCFG->CCCR, (0xFFU << offset), ((NmosValue << offset) | (PmosValue << (offset + 4U))));
+ }
+
+ MODIFY_REG(SYSCFG->CCCSR, (Selection << 1U), (Code << (POSITION_VAL(Selection) + 1U)));
+}
+
+/**
+ * @brief Get the code selection for the compensation cell
+ * @param Selection specifies the concerned compensation cell
+ * This parameter can one of the following values:
+ * @arg SYSCFG_IO_VDD_CELL Compensation cell for the I/O supplied by vdd
+ * @arg SYSCFG_IO_VDDIO2_CELL Compensation cell for the I/O supplied by vddio2
+ * @param pCode pointer code selection
+ * @param pNmosValue pointer to the Nmos value in range 0 to 15
+ * @param pPmosValue pointer to the Pmos value in range 0 to 15
+ * @retval HAL_OK (all values available) or HAL_ERROR (check parameters)
+ */
+HAL_StatusTypeDef HAL_SYSCFG_GetCompensationCell(uint32_t Selection, uint32_t *pCode, uint32_t *pNmosValue,
+ uint32_t *pPmosValue)
+{
+ uint32_t reg;
+ uint32_t offset;
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check parameters */
+ if ((pCode != NULL) && (pNmosValue != NULL) && (pPmosValue != NULL))
+ {
+ *pCode = ((SYSCFG->CCCSR & (Selection << 1U)) == 0U) ? SYSCFG_IO_CELL_CODE : SYSCFG_IO_REGISTER_CODE;
+
+ reg = (*pCode == SYSCFG_IO_CELL_CODE) ? (SYSCFG->CCVR) : (SYSCFG->CCCR);
+ offset = ((Selection == SYSCFG_IO_VDD_CELL) ? 0U : 8U);
+
+ *pNmosValue = ((reg >> offset) & 0xFU);
+ *pPmosValue = ((reg >> (offset + 4U)) & 0xFU);
+
+ status = HAL_OK;
+ }
+ return status;
+}
+
+/**
+ * @brief Configure the infrared (IR) interface
+ * @param Modulation
+ * This parameter can one of the following values:
+ * @arg SYSCFG_IR_MOD_TIM16
+ * @arg SYSCFG_IR_MOD_USART1
+ * @arg SYSCFG_IR_MOD_UART4
+ * @param OutputPol
+ * This parameter can one of the following values:
+ * @arg SYSCFG_IR_OUTPUTPOL_NONINVERTED
+ * @arg SYSCFG_IR_OUTPUTPOL_INVERTED
+ * @retval None
+ */
+void HAL_SYSCFG_ConfigIR(uint32_t Modulation, uint32_t OutputPol)
+{
+ assert_param(IS_SYSCFG_IR_MODULATION(Modulation));
+ assert_param(IS_SYSCFG_IR_OUTPUTPOL(OutputPol));
+
+ MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD | SYSCFG_CFGR1_IR_POL, Modulation | OutputPol);
+}
+
+/**
+ * @brief Get the infrared (IR) interface configuration
+ * @param pModulation pointer to Modulation
+ * @param pOutputPol pointer to Output Polarity
+ * @retval HAL_OK (all values available) or HAL_ERROR (check parameters)
+ */
+HAL_StatusTypeDef HAL_SYSCFG_GetConfigIR(uint32_t *pModulation, uint32_t *pOutputPol)
+{
+ uint32_t reg;
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check parameters */
+ if ((pModulation != NULL) && (pOutputPol != NULL))
+ {
+ reg = SYSCFG->CFGR1;
+
+ *pModulation = (uint32_t)(READ_BIT(reg, SYSCFG_CFGR1_IR_MOD));
+ *pOutputPol = (uint32_t)(READ_BIT(reg, SYSCFG_CFGR1_IR_POL));
+
+ status = HAL_OK;
+ }
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Functions_Group5 HAL SYSCFG lock management functions
+ * @brief SYSCFG lock management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### SYSCFG lock functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Lock the SYSCFG item(s).
+ * @note Setting lock(s) depends on privilege mode in secure/non-secure code
+ * Lock(s) cleared only at system reset
+ * @param Item Item(s) to set lock on.
+ * This parameter can be a combination of @ref SYSCFG_Lock_items
+ * @retval None
+ */
+void HAL_SYSCFG_Lock(uint32_t Item)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_LOCK_ITEMS(Item));
+
+ /* Privilege secure/non-secure locks */
+ SYSCFG->CNSLCKR = (0xFFFFU & Item); /* non-secure lock item in 16 lowest bits */
+
+#if defined (CPU_IN_SECURE_STATE)
+ /* Privilege secure only locks */
+ SYSCFG->CSLCKR = ((0xFFFF0000U & Item) >> 16U); /* Secure-only lock item in 16 highest bits */
+#endif /* CPU_IN_SECURE_STATE */
+}
+
+/**
+ * @brief Get the lock state of SYSCFG item.
+ * @note Getting lock(s) depends on privilege mode in secure/non-secure code
+ * @param pItem pointer to return locked items
+ * the return value can be a combination of @ref SYSCFG_Lock_items
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem)
+{
+ uint32_t tmp_lock;
+
+ /* Check null pointer */
+ if (pItem == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Get the non-secure lock state */
+ tmp_lock = SYSCFG->CNSLCKR;
+
+ /* Get the secure lock state in secure code */
+#if defined (CPU_IN_SECURE_STATE)
+ tmp_lock |= (SYSCFG->CSLCKR << 16U);
+#endif /* CPU_IN_SECURE_STATE */
+
+ /* Return overall lock status */
+ *pItem = tmp_lock;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_Exported_Functions_Group6 HAL SYSCFG attributes management functions
+ * @brief SYSCFG attributes management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### SYSCFG attributes functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+#if defined (CPU_IN_SECURE_STATE)
+/**
+ * @brief Configure the SYSCFG item attribute(s).
+ * @note Available attributes are to secure SYSCFG items, so this function is
+ * only available in secure
+ * @param Item Item(s) to set attributes on.
+ * This parameter can be a one or a combination of @ref SYSCFG_Attributes_items
+ * @param Attributes specifies the secure/non-secure attributes.
+ * @retval None
+ */
+void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes)
+{
+ uint32_t tmp;
+
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_ITEMS_ATTRIBUTES(Item));
+ assert_param(IS_SYSCFG_ATTRIBUTES(Attributes));
+
+ tmp = SYSCFG_S->SECCFGR;
+
+ /* Set or reset Item */
+ if ((Attributes & SYSCFG_SEC) != 0x00U)
+ {
+ tmp |= Item;
+ }
+ else
+ {
+ tmp &= ~Item;
+ }
+
+ /* Set secure attributes */
+ SYSCFG_S->SECCFGR = tmp;
+}
+
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+ * @brief Get the attribute of a SYSCFG item.
+ * @note Available attributes are to secure SYSCFG items, so this function is
+ * only available in secure
+ * @param Item Single item to get secure/non-secure attribute from.
+ * @param pAttributes pointer to return the attribute.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes)
+{
+ /* Check null pointer */
+ if (pAttributes == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_SINGLE_ITEMS_ATTRIBUTES(Item));
+
+ /* Get the secure attribute state */
+ if ((SYSCFG->SECCFGR & Item) != 0U)
+ {
+ *pAttributes = SYSCFG_SEC;
+ }
+ else
+ {
+ *pAttributes = SYSCFG_NSEC;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+#endif /* HAL_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_adc.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_adc.c
new file mode 100644
index 0000000000..28319fe8b8
--- /dev/null
+++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_adc.c
@@ -0,0 +1,3769 @@
+/**
+ ******************************************************************************
+ * @file stm32u3xx_hal_adc.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Converter (ADC)
+ * peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ * Other functions (extended functions) are available in file
+ * "stm32u3xx_hal_adc_ex.c".
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### ADC peripheral features #####
+ ==============================================================================
+ [..]
+ (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
+
+ (+) Interrupt generation at the end of regular conversion and in case of
+ analog watchdog or overrun events.
+
+ (+) Single and continuous conversion modes.
+
+ (+) Scan mode for conversion of several channels sequentially.
+
+ (+) Data alignment with in-built data coherency.
+
+ (+) Programmable sampling time (channel wise)
+
+ (+) External trigger (timer or EXTI) with configurable polarity
+
+ (+) DMA request generation for transfer of conversions data of regular group.
+
+ (+) Configurable delay between conversions in Dual interleaved mode.
+
+ (+) ADC channels selectable single/differential input.
+
+ (+) ADC offset shared on 4 offset instances.
+
+ (+) ADC gain compensation
+
+ (+) ADC calibration
+
+ (+) ADC conversion of regular group.
+
+ (+) ADC supply requirements: 1.62 V to 3.6 V.
+
+ (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
+ Vdda or to an external voltage reference).
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+
+ *** Configuration of top level parameters related to ADC ***
+ ============================================================
+ [..]
+
+ (#) Enable the ADC interface
+ (++) As prerequisite, ADC clock must be configured at RCC top level.
+
+ (++) Two clock settings are mandatory:
+ (+++) ADC clock (core clock, also possibly conversion clock).
+
+ (+++) ADC clock (conversions clock).
+ Two possible clock sources: synchronous clock derived from AHB clock
+ or asynchronous clock derived from system clock, PLL2 or PLL3.
+
+ (+++) Example:
+ Into HAL_ADC_MspInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory)
+
+ RCC_ADCCLKSOURCE_PLL2 enable: (optional: if asynchronous clock selected)
+ (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit;
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+ (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
+ (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+ (++) ADC clock source and clock prescaler are configured at ADC level with
+ parameter "ClockPrescaler" using function HAL_ADC_Init().
+
+ (#) ADC pins configuration
+ (++) Enable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_ENABLE()
+ (++) Configure these ADC pins in analog mode
+ using function HAL_GPIO_Init()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Configure the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding ADC interruption vector
+ ADCx_IRQHandler().
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Configure the DMA (DMA channel, mode normal or circular, ...)
+ using function HAL_DMA_Init().
+ (++) Configure the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding DMA interruption vector
+ DMAx_Channelx_IRQHandler().
+
+ *** Configuration of ADC, group regular, channels parameters ***
+ ================================================================
+ [..]
+
+ (#) Configure the ADC parameters (resolution, data alignment, ...)
+ and regular group parameters (conversion trigger, sequencer, ...)
+ using function HAL_ADC_Init().
+
+ (#) Configure the channels for regular group parameters (channel number,
+ channel rank into sequencer, ..., into regular group)
+ using function HAL_ADC_ConfigChannel().
+
+ (#) Optionally, configure the analog watchdog parameters (channels
+ monitored, thresholds, ...)
+ using function HAL_ADC_AnalogWDGConfig().
+
+ *** Execution of ADC conversions ***
+ ====================================
+ [..]
+
+ (#) Optionally, perform an automatic ADC calibration to improve the
+ conversion accuracy
+ using function HAL_ADCEx_Calibration_Start().
+
+ (#) ADC driver can be used among three modes: polling, interruption,
+ transfer by DMA.
+
+ (++) ADC conversion by polling:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start()
+ (+++) Wait for ADC conversion completion
+ using function HAL_ADC_PollForConversion()
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop()
+
+ (++) ADC conversion by interruption:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_IT()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback()
+ (this function must be implemented in user program)
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_IT()
+
+ (++) ADC conversion with transfer by DMA:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_DMA()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+ (these functions must be implemented in user program)
+ (+++) Conversion results are automatically transferred by DMA into
+ destination variable address.
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_DMA()
+
+ [..]
+
+ (@) Callback functions must be implemented in user program:
+ (+@) HAL_ADC_ErrorCallback()
+ (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+ (+@) HAL_ADC_ConvCpltCallback()
+ (+@) HAL_ADC_ConvHalfCpltCallback
+
+ *** Deinitialization of ADC ***
+ ============================================================
+ [..]
+
+ (#) Disable the ADC interface
+ (++) ADC clock can be hard reset and disabled at RCC top level.
+ (++) Hard reset of ADC peripherals
+ using macro __HAL_RCC_ADCx_FORCE_RESET(), __HAL_RCC_ADCx_RELEASE_RESET().
+ (++) ADC clock disable
+ using the equivalent macro/functions as configuration step.
+ (+++) Example:
+ Into HAL_ADC_MspDeInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) __HAL_RCC_ADC_CLK_DISABLE(); (if not used anymore)
+ RCC_ADCCLKSOURCE_CLKP restore: (optional)
+ (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit;
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+ (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_CLKP;
+ (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+ (#) ADC pins configuration
+ (++) Disable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Disable the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Deinitialize the DMA
+ using function HAL_DMA_Init().
+ (++) Disable the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+
+ [..]
+
+ *** Callback registration ***
+ =============================================
+ [..]
+
+ The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_ADC_RegisterCallback()
+ to register an interrupt callback.
+ [..]
+
+ Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
+ (+) ConvCpltCallback : ADC conversion complete callback
+ (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
+ (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
+ (+) ErrorCallback : ADC error callback
+ (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
+ (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
+ (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
+ (+) EndOfSamplingCallback : ADC end of sampling callback
+ (+) MspInitCallback : ADC Msp Init callback
+ (+) MspDeInitCallback : ADC Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+ [..]
+
+ Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
+ weak function.
+ [..]
+
+ @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) ConvCpltCallback : ADC conversion complete callback
+ (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
+ (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
+ (+) ErrorCallback : ADC error callback
+ (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
+ (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
+ (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
+ (+) EndOfSamplingCallback : ADC end of sampling callback
+ (+) MspInitCallback : ADC Msp Init callback
+ (+) MspDeInitCallback : ADC Msp DeInit callback
+ [..]
+
+ By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ [..]
+
+ If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
+
+ Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ [..]
+
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
+ or @ref HAL_ADC_Init() function.
+ [..]
+
+ When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u3xx_hal.h"
+
+/** @addtogroup STM32U3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADC ADC
+ * @brief ADC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+#define ADC_CFGR1_FIELDS_1 ((uint32_t)(ADC_CFGR1_RES |\
+ ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |\
+ ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM |\
+ ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL)) /*!< ADC_CFGR1 fields of
+ parameters that can be updated when no regular conversion is on-going */
+
+#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR |\
+ ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
+ ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of
+ parameters that can be updated when no conversion (neither regular
+ nor injected) is on-going */
+
+/* Timeout values for ADC operations (enable settling time, */
+/* disable settling time, ...). */
+/* Values defined to be higher than worst cases: low clock frequency, */
+/* maximum prescalers. */
+#define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */
+#define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */
+
+/* Timeout to wait for current conversion on going to be completed. */
+/* Timeout fixed to longest ADC conversion possible, for 1 channel: */
+/* - maximum sampling time (640.5 adc_clk) */
+/* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */
+/* - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio) */
+/* - ADC oversampling ratio 256 */
+/* Calculation: 653 * 4096 * 256 CPU clock cycles max */
+/* Unit: cycles of CPU clock. */
+#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL) /*!< ADC conversion completion time-out value */
+
+#define ADC_LDO_RDY_TIMEOUT (1UL) /* Note: Timeout value independent of ADC clock frequency, for more
+ accurate value refer to LL_ADC_DELAY_INTERNAL_REGUL_STAB_US */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief ADC Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the ADC.
+ (+) De-initialize the ADC.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the ADC peripheral and regular group according to
+ * parameters specified in structure "ADC_InitTypeDef".
+ * @note As prerequisite, ADC clock must be configured at RCC top level
+ * (refer to description of RCC configuration for ADC
+ * in header of this file).
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+ * coming from ADC state reset. Following calls to this function can
+ * be used to reconfigure some parameters of ADC_InitTypeDef
+ * structure on the fly, without modifying MSP configuration. If ADC
+ * MSP has to be modified again, HAL_ADC_DeInit() must be called
+ * before HAL_ADC_Init().
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_InitTypeDef".
+ * @note This function configures the ADC within 2 scopes: scope of entire
+ * ADC and scope of regular group. For parameters details, see comments
+ * of structure "ADC_InitTypeDef".
+ * @note Parameters related to common ADC registers (ADC clock mode) are set
+ * only if all ADCs are disabled.
+ * If this is not the case, these common parameters setting are
+ * bypassed without error reporting: it can be the intended behaviour in
+ * case of update of a parameter of ADC_InitTypeDef on the fly,
+ * without disabling the other ADCs sharing the same ADC common instance.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmpCFGR1;
+ uint32_t tmp_adc_reg_is_conversion_on_going;
+ uint32_t tickstart;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check ADC handle */
+ if (hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+ assert_param(IS_ADC_GAIN_COMPENSATION(hadc->Init.GainCompensation));
+ assert_param(IS_ADC_SAMPLINGMODE(hadc->Init.SamplingMode));
+ assert_param(IS_ADC_CONVERSIONDATAMGT(hadc->Init.ConversionDataManagement));
+ assert_param(IS_ADC_EXTTRIG(hadc->Instance, hadc->Init.ExternalTrigConv));
+ assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+ assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
+
+ if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ {
+ assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+
+ if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ {
+ assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
+ }
+ }
+
+ /* DISCEN and CONT bits cannot be set at the same time */
+ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
+
+ /* Actions performed only if ADC is coming from state reset: */
+ /* - Initialization of ADC MSP */
+ if (hadc->State == HAL_ADC_STATE_RESET)
+ {
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ /* Init the ADC Callback settings */
+ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
+ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
+ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
+ hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
+ hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
+ hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */
+ hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */
+ hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */
+ hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */
+
+ if (hadc->MspInitCallback == NULL)
+ {
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hadc->MspInitCallback(hadc);
+#else
+ /* Init the low level hardware */
+ HAL_ADC_MspInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Initialize Lock */
+ hadc->Lock = HAL_UNLOCKED;
+ }
+
+ /* - Exit from deep-power-down mode and ADC voltage regulator enable */
+ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
+ {
+ /* Disable ADC deep power down mode */
+ LL_ADC_DisableDeepPowerDown(hadc->Instance);
+
+ /* System was in deep power down mode, calibration must
+ be relaunched or a previously saved calibration factor
+ re-applied once the ADC voltage regulator is enabled */
+ }
+ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
+ {
+ /* Clear flag ADC internal voltage regulator ready */
+ LL_ADC_ClearFlag_LDORDY(hadc->Instance);
+
+ /* Enable ADC internal voltage regulator */
+ LL_ADC_EnableInternalRegulator(hadc->Instance);
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Delay for ADC stabilization time */
+ while (LL_ADC_IsActiveFlag_LDORDY(hadc->Instance) == 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > ADC_LDO_RDY_TIMEOUT)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (LL_ADC_IsActiveFlag_LDORDY(hadc->Instance) == 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed and if there is no conversion on going on regular */
+ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
+ /* called to update a parameter on the fly). */
+ tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+
+ if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+ && (tmp_adc_reg_is_conversion_on_going == 0UL)
+ )
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Configuration of common ADC parameters */
+ /* (None) */
+
+ /* Configuration of ADC instance: */
+ /* - resolution Init.Resolution */
+ /* - external trigger to start conversion Init.ExternalTrigConv */
+ /* - external trigger polarity Init.ExternalTrigConvEdge */
+ /* - continuous conversion mode Init.ContinuousConvMode */
+ /* - overrun Init.Overrun */
+ /* - discontinuous mode Init.DiscontinuousConvMode */
+ /* - discontinuous mode channel count Init.NbrOfDiscConversion */
+
+ tmpCFGR1 = (ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
+ hadc->Init.Overrun |
+ hadc->Init.Resolution |
+ ADC_CFGR1_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
+
+ if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ {
+ tmpCFGR1 |= ADC_CFGR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
+ }
+
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ {
+ tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL)
+ | hadc->Init.ExternalTrigConvEdge
+ );
+ }
+
+ /* Update Configuration Register CFGR */
+ MODIFY_REG(hadc->Instance->CFGR1, ADC_CFGR1_FIELDS_1, tmpCFGR1);
+
+ /* Configuration of sampling mode */
+ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular and injected groups: */
+ /* - Conversion data management Init.ConversionDataManagement */
+ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */
+ /* - Oversampling parameters Init.Oversampling */
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ )
+ {
+ tmpCFGR1 = (
+ ADC_CFGR1_AUTODELAY((uint32_t)hadc->Init.LowPowerAutoWait) |
+ ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
+
+ MODIFY_REG(hadc->Instance->CFGR1, ADC_CFGR1_FIELDS_2, tmpCFGR1);
+
+ LL_ADC_SetGainCompensation(hadc->Instance, hadc->Init.GainCompensation);
+
+ if (hadc->Init.OversamplingMode == ENABLE)
+ {
+ assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
+ assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
+ assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
+ assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
+
+ if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
+ || (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
+ {
+ /* Multi trigger is not applicable to software-triggered conversions */
+ assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
+ }
+
+ /* Configuration of Oversampler: */
+ /* - Oversampling Ratio */
+ /* - Right bit shift */
+ /* - Left bit shift */
+ /* - Triggered mode */
+ /* - Oversampling mode (continued/resumed) */
+ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
+ ADC_CFGR2_ROVSE |
+ ((hadc->Init.Oversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
+ hadc->Init.Oversampling.RightBitShift |
+ hadc->Init.Oversampling.TriggeredMode |
+ hadc->Init.Oversampling.OversamplingStopReset);
+
+ }
+ else
+ {
+ /* Disable ADC oversampling scope on ADC group regular */
+ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
+ }
+
+ /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */
+ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
+ }
+
+ /* Configuration of regular group sequencer: */
+ /* - if scan mode is disabled, regular channels sequence length is set to */
+ /* 0x00: 1 channel converted (channel on regular rank 1) */
+ /* Parameter "NbrOfConversion" is discarded. */
+ /* Note: Scan mode is not present by hardware on this device, but */
+ /* emulated by software for alignment over all STM32 devices. */
+ /* - if scan mode is enabled, regular channels sequence length is set to */
+ /* parameter "NbrOfConversion". */
+
+ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+ {
+ /* Set number of ranks in regular group sequencer */
+ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
+ }
+ else
+ {
+ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
+ }
+
+ /* Initialize the ADC state */
+ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Deinitialize the ADC peripheral registers to their default reset
+ * values, with deinitialization of the ADC MSP.
+ * @note For devices with several ADCs: reset of ADC common registers is done
+ * only if all ADCs sharing the same common group are disabled.
+ * (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
+ * all ADC instances use the same core clock at RCC level, disabling
+ * the core clock reset all ADC instances).
+ * If this is not the case, reset of these common parameters reset is
+ * bypassed without error reporting: it can be the intended behavior in
+ * case of reset of a single ADC while the other ADCs sharing the same
+ * common group is still running.
+ * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
+ * this saves more power by reducing leakage currents
+ * and is particularly interesting before entering MCU low-power modes.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check ADC handle */
+ if (hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Stop potential conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+ }
+
+ /* Disable ADC internal voltage regulator */
+ LL_ADC_DisableInternalRegulator(hadc->Instance);
+
+ /* Enable ADC deep power down mode */
+ LL_ADC_EnableDeepPowerDown(hadc->Instance);
+
+ /* Note: HAL ADC deInit is done independently of ADC conversion stop */
+ /* and disable return status. In case of status fail, attempt to */
+ /* perform deinitialization anyway and it is up user code in */
+ /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */
+ /* system RCC hard reset. */
+
+ /* ========== Reset ADC registers ========== */
+ /* Reset register IER */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
+ ADC_IT_LDORDY |
+ ADC_IT_JQOVF | ADC_IT_OVR |
+ ADC_IT_JEOS | ADC_IT_JEOC |
+ ADC_IT_EOS | ADC_IT_EOC |
+ ADC_IT_EOSMP | ADC_IT_RDY));
+
+ /* Reset register ISR */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
+ ADC_FLAG_LDORDY |
+ ADC_FLAG_JQOVF | ADC_FLAG_OVR |
+ ADC_FLAG_JEOS | ADC_FLAG_JEOC |
+ ADC_FLAG_EOS | ADC_FLAG_EOC |
+ ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+
+ /* Reset register CR */
+ /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
+ ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
+ no direct reset applicable.
+ Update CR register to reset value where doable by software */
+ SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
+
+ /* Reset register CFGR1 */
+ CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_AWD1CH | ADC_CFGR1_JAUTO |
+ ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_JDISCEN |
+ ADC_CFGR1_DISCNUM | ADC_CFGR1_DISCEN | ADC_CFGR1_AUTDLY |
+ ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |
+ ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL |
+ ADC_CFGR1_RES | ADC_CFGR1_DMNGT | ADC_CFGR1_JQM);
+ SET_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JQDIS);
+
+ /* Reset register CFGR2 */
+ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SMPTRIG |
+ ADC_CFGR2_LFTRIG | ADC_CFGR2_LSHIFT |
+ ADC_CFGR2_SWTRIG | ADC_CFGR2_BULB |
+ ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS |
+ ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
+
+ /* Reset register SMPR1 */
+ CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
+
+ /* Reset register SMPR2 */
+ CLEAR_BIT(hadc->Instance->SMPR2,
+ ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
+ ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
+ ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
+
+ /* Reset registers of AWD1 thresholds */
+ CLEAR_BIT(hadc->Instance->AWD1LTR, ADC_AWD1LTR_LTR);
+ MODIFY_REG(hadc->Instance->AWD1HTR,
+ ADC_AWD1HTR_AWDFILT | ADC_AWD1HTR_HTR,
+ ADC_AWD1HTR_HTR & (~(ADC_AWD1HTR_AWDFILT | ADC_AWD1HTR_HTR_22)));
+
+ /* Reset registers of AWD2 thresholds */
+ CLEAR_BIT(hadc->Instance->AWD2LTR, ADC_AWD2LTR_LTR);
+ MODIFY_REG(hadc->Instance->AWD2HTR,
+ ADC_AWD2HTR_HTR,
+ ADC_AWD2HTR_HTR & (~(ADC_AWD2HTR_HTR_22)));
+
+ /* Reset registers of AWD3 thresholds */
+ CLEAR_BIT(hadc->Instance->AWD3LTR, ADC_AWD3LTR_LTR);
+ MODIFY_REG(hadc->Instance->AWD3HTR,
+ ADC_AWD3HTR_HTR,
+ ADC_AWD3HTR_HTR & (~(ADC_AWD3HTR_HTR_22)));
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
+ ADC_SQR1_SQ1 | ADC_SQR1_L);
+
+ /* Reset register SQR2 */
+ CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
+ ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
+
+ /* Reset register SQR3 */
+ CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
+ ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
+
+ /* Reset register SQR4 */
+ CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
+
+ /* Register JSQR was reset when the ADC was disabled */
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset register OFR1 */
+ CLEAR_BIT(hadc->Instance->OFCFGR1, ADC_OFCFGR1_SSAT | ADC_OFCFGR1_OFFSET_CH | ADC_OFCFGR1_USAT | ADC_OFCFGR1_POSOFF);
+ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET);
+ /* Reset register OFR2 */
+ CLEAR_BIT(hadc->Instance->OFCFGR2, ADC_OFCFGR2_SSAT | ADC_OFCFGR2_OFFSET_CH | ADC_OFCFGR1_USAT | ADC_OFCFGR2_POSOFF);
+ CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET);
+ /* Reset register OFR3 */
+ CLEAR_BIT(hadc->Instance->OFCFGR3, ADC_OFCFGR3_SSAT | ADC_OFCFGR3_OFFSET_CH | ADC_OFCFGR1_USAT | ADC_OFCFGR3_POSOFF);
+ CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET);
+ /* Reset register OFR4 */
+ CLEAR_BIT(hadc->Instance->OFCFGR4, ADC_OFCFGR4_SSAT | ADC_OFCFGR4_OFFSET_CH | ADC_OFCFGR1_USAT | ADC_OFCFGR4_POSOFF);
+ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET);
+
+ /* Reset register GCOMP */
+ CLEAR_BIT(hadc->Instance->GCOMP, ADC_GCOMP_GCOMP | ADC_GCOMP_GCOMPCOEFF);
+ SET_BIT(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF_12);
+
+ /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset register AWD2CR */
+ CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
+
+ /* Reset register AWD3CR */
+ CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
+
+
+ /* Reset register PCSEL */
+ CLEAR_BIT(hadc->Instance->PCSEL, ADC_PCSEL_PCSEL);
+
+ /* Reset register CALFACT */
+ CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT);
+
+ /* Reset register OR */
+ CLEAR_BIT(hadc->Instance->OR, ADC_OR_VDDCOREEN);
+
+ /* ========== Reset common ADC registers ========== */
+
+ /* Software is allowed to change common parameters only when all the other
+ ADCs are disabled. */
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ {
+ /* Reset configuration of ADC common register CCR:
+ - clock mode: CKMODE, PRESCEN
+ - multimode related parameters (when this feature is available): MDMA,
+ DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
+ - internal measurement paths: Vbat, temperature sensor, Vref (set into
+ HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
+ */
+ ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
+ }
+
+ /* ========== Hard reset ADC peripheral ========== */
+ /* Performs a global reset of the entire ADC peripherals instances */
+ /* sharing the same common ADC instance: ADC state is forced to */
+ /* a similar state as after device power-on. */
+ /* Note: A possible implementation is to add RCC bus reset of ADC */
+ /* (for example, using macro */
+ /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */
+ /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ if (hadc->MspDeInitCallback == NULL)
+ {
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware */
+ hadc->MspDeInitCallback(hadc);
+#else
+ /* DeInit the low level hardware */
+ HAL_ADC_MspDeInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Reset injected channel configuration parameters */
+ hadc->InjectionConfig.ContextQueue = 0;
+ hadc->InjectionConfig.ChannelCount = 0;
+
+ /* Set ADC state */
+ hadc->State = HAL_ADC_STATE_RESET;
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Initialize the ADC MSP.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_MspInit must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitialize the ADC MSP.
+ * @param hadc ADC handle
+ * @note All ADC instances use the same core clock at RCC level, disabling
+ * the core clock reset all ADC instances).
+ * @retval None
+ */
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_MspDeInit must be implemented in the user file.
+ */
+}
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User ADC Callback
+ * To be used instead of the weak predefined callback
+ * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
+ * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
+ * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
+ * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
+ * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
+ * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+ pADC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+ hadc->ConvCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_CONVERSION_HALF_CB_ID :
+ hadc->ConvHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+ hadc->LevelOutOfWindowCallback = pCallback;
+ break;
+
+ case HAL_ADC_ERROR_CB_ID :
+ hadc->ErrorCallback = pCallback;
+ break;
+
+ case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+ hadc->InjectedConvCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
+ hadc->InjectedQueueOverflowCallback = pCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
+ hadc->LevelOutOfWindow2Callback = pCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
+ hadc->LevelOutOfWindow3Callback = pCallback;
+ break;
+
+ case HAL_ADC_END_OF_SAMPLING_CB_ID :
+ hadc->EndOfSamplingCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_ADC_STATE_RESET == hadc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a ADC Callback
+ * ADC callback is redirected to the weak predefined callback
+ * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
+ * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
+ * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
+ * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
+ * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
+ * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
+ break;
+
+ case HAL_ADC_CONVERSION_HALF_CB_ID :
+ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
+ break;
+
+ case HAL_ADC_ERROR_CB_ID :
+ hadc->ErrorCallback = HAL_ADC_ErrorCallback;
+ break;
+
+ case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+ hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
+ break;
+
+ case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
+ hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
+ hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
+ hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
+ break;
+
+ case HAL_ADC_END_OF_SAMPLING_CB_ID :
+ hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
+ break;
+
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_ADC_STATE_RESET == hadc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
+ * @brief ADC IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion of regular group.
+ (+) Stop conversion of regular group.
+ (+) Poll for conversion complete on regular group.
+ (+) Poll for conversion event.
+ (+) Get result of regular channel conversion.
+ (+) Start conversion of regular group and enable interruptions.
+ (+) Stop conversion of regular group and disable interruptions.
+ (+) Handle ADC interrupt request
+ (+) Start conversion of regular group and enable DMA transfer.
+ (+) Stop conversion of regular group and disable ADC DMA transfer.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable ADC, start conversion of regular group.
+ * @note Interruptions enabled in this function: None.
+ * @note Case of multimode enabled (when multimode feature is available):
+ * if ADC is Slave, ADC is enabled but conversion is not started,
+ * if ADC is master, ADC is enabled and multimode conversion is started.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ const ADC_TypeDef *tmpADC_Master;
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+ - if ADC instance is master or if multimode feature is not available
+ - if multimode setting is disabled (ADC instance slave in independent mode) */
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ )
+ {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Set ADC error code */
+ /* Check if a conversion is on going on ADC group injected */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to regular conversions only */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Clear ADC group regular conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (when multimode feature is available): */
+ /* - if ADC is slave and dual regular conversions are enabled, ADC is */
+ /* enabled only (conversion is not started), */
+ /* - if ADC is master, ADC is enabled and conversion is started. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+ )
+ {
+ /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
+ if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ }
+ else
+ {
+ /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ /* if Master ADC JAUTO bit is set, update Slave State in setting
+ HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
+ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ if (READ_BIT(tmpADC_Master->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ }
+#else
+ if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+#endif /* ADC_MULTIMODE_SUPPORT */
+ }
+ else
+ {
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected channels in
+ * case of auto_injection mode), disable ADC peripheral.
+ * @note: ADC peripheral disable is forcing stop of potential
+ * conversion on injected group. If injected group is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going, on ADC groups regular and injected */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Wait for regular group conversion to be completed.
+ * @note ADC conversion flags EOS (end of sequence) and EOC (end of
+ * conversion) are cleared by this function, with an exception:
+ * if low power feature "LowPowerAutoWait" is enabled, flags are
+ * not cleared to not interfere with this feature until data register
+ * is read using function HAL_ADC_GetValue().
+ * @note This function cannot be used in a particular setup: ADC configured
+ * in DMA mode and polling for end of each conversion (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+ * In this case, DMA resets the flag EOC and polling cannot be
+ * performed on each conversion. Nevertheless, polling can still
+ * be performed on the complete sequence (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
+ * @param hadc ADC handle
+ * @param Timeout Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t tmp_Flag_End;
+ uint32_t tmp_cfgr;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ const ADC_TypeDef *tmpADC_Master;
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* If end of conversion selected to end of sequence conversions */
+ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+ {
+ tmp_Flag_End = ADC_FLAG_EOS;
+ }
+ /* If end of conversion selected to end of unitary conversion */
+ else /* ADC_EOC_SINGLE_CONV */
+ {
+ /* Verification that ADC configuration is compliant with polling for */
+ /* each conversion: */
+ /* Particular case is ADC configured in DMA mode and ADC sequencer with */
+ /* several ranks and polling for end of each conversion. */
+ /* For code simplicity sake, this particular case is generalized to */
+ /* ADC configured in DMA mode and and polling for end of each conversion. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+ )
+ {
+ /* Check ADC DMA mode in independent mode on ADC group regular */
+ if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT_0) != 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ return HAL_ERROR;
+ }
+ else
+ {
+ tmp_Flag_End = (ADC_FLAG_EOC);
+ }
+ }
+ else
+ {
+ /* Check ADC DMA mode in multimode on ADC group regular */
+ if (LL_ADC_GetMultiDataFormat(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DATA_EACH_ADC)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ return HAL_ERROR;
+ }
+ else
+ {
+ tmp_Flag_End = (ADC_FLAG_EOC);
+ }
+ }
+#else
+ /* Check ADC DMA mode */
+ if (LL_ADC_REG_GetDMATransfer(hadc->Instance) != LL_ADC_REG_DMA_TRANSFER_NONE)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ return HAL_ERROR;
+ }
+ else
+ {
+ tmp_Flag_End = (ADC_FLAG_EOC);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+ }
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Wait until End of unitary conversion or sequence conversions flag is raised */
+ while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+ && (hadc->Init.ContinuousConvMode == DISABLE)
+ )
+ {
+ /* Check whether end of sequence is reached */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ }
+
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+ )
+ {
+ /* Retrieve ADC CFGR1 register */
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+ }
+ else
+ {
+ /* Retrieve Master ADC CFGR register */
+ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ tmp_cfgr = READ_REG(tmpADC_Master->CFGR1);
+ }
+#else
+ /* Retrieve ADC CFGR1 register */
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Clear polled flag */
+ if (tmp_Flag_End == ADC_FLAG_EOS)
+ {
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
+ }
+ else
+ {
+ /* Clear end of conversion EOC flag of regular group if low power feature */
+ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
+ /* until data register is read using function HAL_ADC_GetValue(). */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR1_AUTDLY) == 0UL)
+ {
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Poll for ADC event.
+ * @param hadc ADC handle
+ * @param EventType the ADC event type.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
+ * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on
+ * all STM32 series)
+ * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on
+ * all STM32 series)
+ * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on
+ * all STM32 series)
+ * @arg @ref ADC_OVR_EVENT ADC Overrun event
+ * @param Timeout Timeout value in millisecond.
+ * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
+ * Indeed, the latter is reset only if hadc->Init.Overrun field is set
+ * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
+ * by a new converted data as soon as OVR is cleared.
+ * To reset OVR flag once the preserved data is retrieved, the user can resort
+ * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_EVENT_TYPE(EventType));
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Check selected event flag */
+ while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ switch (EventType)
+ {
+ /* End Of Sampling event */
+ case ADC_EOSMP_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+
+ /* Clear the End Of Sampling flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+
+ break;
+
+ /* Analog watchdog (level out of window) event */
+ /* Note: In case of several analog watchdog enabled, if needed to know */
+ /* which one triggered and on which ADCx, test ADC state of analog watchdog */
+ /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */
+ /* For example: */
+ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */
+ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */
+ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */
+
+ /* Check analog watchdog 1 flag */
+ case ADC_AWD_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+
+ break;
+
+ /* Check analog watchdog 2 flag */
+ case ADC_AWD2_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+
+ break;
+
+ /* Check analog watchdog 3 flag */
+ case ADC_AWD3_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+
+ break;
+
+ /* Injected context queue overflow event */
+ case ADC_JQOVF_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+ /* Set ADC error code to Injected context queue overflow */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+
+ /* Clear ADC Injected context queue overflow flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+
+ break;
+
+ /* Overrun event */
+ default: /* Case ADC_OVR_EVENT */
+ /* If overrun is set to overwrite previous data, overrun event is not */
+ /* considered as an error. */
+ /* (cf ref manual "Managing conversions without using the DMA and without */
+ /* overrun ") */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+ /* Set ADC error code to overrun */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+ }
+ else
+ {
+ /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
+ otherwise, data register is potentially overwritten by new converted data as soon
+ as OVR is cleared. */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ }
+ break;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable ADC, start conversion of regular group with interruption.
+ * @note Interruptions enabled in this function according to initialization
+ * setting : EOC (end of conversion), EOS (end of sequence),
+ * OVR overrun.
+ * Each of these interruptions has its dedicated callback function.
+ * @note Case of multimode enabled (when multimode feature is available):
+ * HAL_ADC_Start_IT() must be called for ADC Slave first, then for
+ * ADC Master.
+ * For ADC Slave, ADC is enabled only (conversion is not started).
+ * For ADC Master, ADC is enabled and multimode conversion is started.
+ * @note To guarantee a proper reset of all interruptions once all the needed
+ * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
+ * a correct stop of the IT-based conversions.
+ * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
+ * interruption. If required (e.g. in case of oversampling with trigger
+ * mode), the user must:
+ * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
+ * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
+ * before calling HAL_ADC_Start_IT().
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ const ADC_TypeDef *tmpADC_Master;
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+ - if ADC instance is master or if multimode feature is not available
+ - if multimode setting is disabled (ADC instance slave in independent mode) */
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ )
+ {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Set ADC error code */
+ /* Check if a conversion is on going on ADC group injected */
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
+ {
+ /* Reset ADC error code fields related to regular conversions only */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Clear ADC group regular conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Disable all interruptions before enabling the desired ones */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+ /* Enable ADC end of conversion interrupt */
+ switch (hadc->Init.EOCSelection)
+ {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
+ break;
+ }
+
+ /* Enable ADC overrun interrupt */
+ /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
+ ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
+ behavior and no CPU time is lost for a non-processed interruption */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+ {
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+ }
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (when multimode feature is available): */
+ /* - if ADC is slave and dual regular conversions are enabled, ADC is */
+ /* enabled only (conversion is not started), */
+ /* - if ADC is master, ADC is enabled and conversion is started. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+ )
+ {
+ /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
+ if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+
+ /* Enable as well injected interruptions in case
+ HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
+ allows to start regular and injected conversions when JAUTO is
+ set with a single call to HAL_ADC_Start_IT() */
+ switch (hadc->Init.EOCSelection)
+ {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+ break;
+ }
+ }
+
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ }
+ else
+ {
+ /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ /* if Master ADC JAUTO bit is set, Slave injected interruptions
+ are enabled nevertheless (for same reason as above) */
+ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ if (READ_BIT(tmpADC_Master->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
+ {
+ /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
+ and in resetting HAL_ADC_STATE_INJ_EOC bit */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ /* Next, set Slave injected interruptions */
+ switch (hadc->Init.EOCSelection)
+ {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+ break;
+ }
+ }
+ }
+#else
+ /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
+ if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+
+ /* Enable as well injected interruptions in case
+ HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
+ allows to start regular and injected conversions when JAUTO is
+ set with a single call to HAL_ADC_Start_IT() */
+ switch (hadc->Init.EOCSelection)
+ {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+ break;
+ }
+ }
+
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+#endif /* ADC_MULTIMODE_SUPPORT */
+ }
+ else
+ {
+ __HAL_UNLOCK(hadc);
+ }
+
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable interrution of
+ * end-of-conversion, disable ADC peripheral.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going, on ADC groups regular and injected */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC end of conversion interrupt for regular group */
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Enable ADC, start conversion of regular group and transfer result through DMA.
+ * @note Interruptions enabled in this function:
+ * overrun (if applicable), DMA half transfer, DMA transfer complete.
+ * Each of these interruptions has its dedicated callback function.
+ * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
+ * is designed for single-ADC mode only. For multimode, the dedicated
+ * HAL_ADCEx_MultiModeStart_DMA() function must be used.
+ * @param hadc ADC handle
+ * @param pData Destination Buffer address.
+ * @param Length Number of data to be transferred from ADC peripheral to memory
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+ uint32_t LengthInBytes;
+ DMA_NodeConfTypeDef node_conf;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Ensure that multimode regular conversions are not enabled. */
+ /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */
+ if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+ )
+#endif /* ADC_MULTIMODE_SUPPORT */
+ {
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+ - if ADC instance is master or if multimode feature is not available
+ - if multimode setting is disabled (ADC instance slave in independent mode) */
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ )
+ {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check if a conversion is on going on ADC group injected */
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
+ {
+ /* Reset ADC error code fields related to regular conversions only */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */
+ /* ADC start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* With DMA, overrun event is always considered as an error even if
+ hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
+ ADC_IT_OVR is enabled. */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Start the DMA channel */
+ /* Check linkedlist mode */
+ if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL))
+ {
+ /* Length should be converted to number of bytes */
+ if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hadc->DMA_Handle->LinkedListQueue->Head) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Length should be converted to number of bytes */
+ if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+ {
+ /* Word -> Bytes */
+ LengthInBytes = Length * 4U;
+ }
+ else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+ {
+ /* Halfword -> Bytes */
+ LengthInBytes = Length * 2U;
+ }
+ else /* Bytes */
+ {
+ /* Same size already expressed in Bytes */
+ LengthInBytes = Length;
+ }
+
+ hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)LengthInBytes;
+ hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
+ (uint32_t)&hadc->Instance->DR;
+ hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+ tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle);
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Length should be converted to number of bytes */
+ if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+ {
+ /* Word -> Bytes */
+ LengthInBytes = Length * 4U;
+ }
+ else if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+ {
+ /* Halfword -> Bytes */
+ LengthInBytes = Length * 2U;
+ }
+ else /* Bytes */
+ {
+ /* Same size already expressed in Bytes */
+ LengthInBytes = Length;
+ }
+
+ /* Start the DMA channel */
+ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, \
+ LengthInBytes);
+ }
+
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ }
+ }
+ else
+ {
+ __HAL_UNLOCK(hadc);
+ }
+ }
+#if defined(ADC_MULTIMODE_SUPPORT)
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ __HAL_UNLOCK(hadc);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable ADC DMA transfer, disable
+ * ADC peripheral.
+ * @note: ADC peripheral disable is forcing stop of potential
+ * conversion on ADC group injected. If ADC group injected is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @note Case of multimode enabled (when multimode feature is available):
+ * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
+ * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential ADC group regular conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
+ MODIFY_REG(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT_0 | ADC_CFGR1_DMNGT_1, 0UL);
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop */
+ /* while DMA transfer is on going) */
+ if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
+ {
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripheral */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, */
+ /* to keep in memory a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ tmp_hal_status = ADC_Disable(hadc);
+ }
+ else
+ {
+ (void)ADC_Disable(hadc);
+ }
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Get ADC regular group conversion result.
+ * @note Reading register DR automatically clears ADC flag EOC
+ * (ADC group regular end of unitary conversion).
+ * @note This function returns an unsigned value. Using the ADC offset
+ * feature can result in negative conversion data.
+ * To read conversion data with ADC offset enabled
+ * use function @ref HAL_ADC_GetSignedValue.
+ * @note This function does not clear ADC flag EOS
+ * (ADC group regular end of sequence conversion).
+ * Occurrence of flag EOS rising:
+ * - If sequencer is composed of 1 rank, flag EOS is equivalent
+ * to flag EOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag EOC only is raised, at the end of the scan sequence
+ * both flags EOC and EOS are raised.
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADC_PollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+ * @param hadc ADC handle
+ * @retval ADC group regular conversion data
+ */
+uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Note: EOC flag is not cleared here by software because automatically */
+ /* cleared by hardware when reading register DR. */
+
+ /* Return ADC converted value */
+ return hadc->Instance->DR;
+}
+
+/**
+ * @brief Get ADC regular group conversion result.
+ * @note Reading register DR automatically clears ADC flag EOC
+ * (ADC group regular end of unitary conversion).
+ * @note This function does not clear ADC flag EOS
+ * (ADC group regular end of sequence conversion).
+ * Occurrence of flag EOS rising:
+ * - If sequencer is composed of 1 rank, flag EOS is equivalent
+ * to flag EOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag EOC only is raised, at the end of the scan sequence
+ * both flags EOC and EOS are raised.
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADC_PollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+ * @param hadc ADC handle
+ * @retval ADC group regular conversion data
+ */
+int32_t HAL_ADC_GetSignedValue(const ADC_HandleTypeDef *hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Note: EOC flag is not cleared here by software because automatically */
+ /* cleared by hardware when reading register DR. */
+
+ /* Return ADC converted value */
+ return (int32_t)(hadc->Instance->DR);
+}
+
+/**
+ * @brief Start ADC conversion sampling phase of regular group
+ * @note: This function should only be called to start sampling when
+ * - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling
+ * mode has been selected
+ * - @ref ADC_SOFTWARE_START has been selected as trigger source
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Start sampling */
+ SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop ADC conversion sampling phase of regular group and start conversion
+ * @note: This function should only be called to stop sampling when
+ * - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling
+ * mode has been selected
+ * - @ref ADC_SOFTWARE_START has been selected as trigger source
+ * - after sampling has been started using @ref HAL_ADC_StartSampling.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Start sampling */
+ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle ADC interrupt request.
+ * @param hadc ADC handle
+ * @retval None
+ */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
+{
+ uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
+ uint32_t tmp_isr = hadc->Instance->ISR;
+ uint32_t tmp_ier = hadc->Instance->IER;
+ uint32_t tmp_adc_inj_is_trigger_source_sw_start;
+ uint32_t tmp_adc_reg_is_trigger_source_sw_start;
+ uint32_t tmp_cfgr;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ const ADC_TypeDef *tmpADC_Master;
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+
+ /* ========== Check End of Sampling flag for ADC group regular ========== */
+ if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
+ {
+ /* Update state machine on end of sampling status if not in error state */
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+ }
+
+ /* End Of Sampling callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->EndOfSamplingCallback(hadc);
+#else
+ HAL_ADCEx_EndOfSamplingCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+ }
+
+ /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
+ if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
+ (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
+ {
+ /* Update state machine on conversion status if not in error state */
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+ }
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going */
+ /* to disable interruption. */
+ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+ {
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+ )
+ {
+ /* check CONT bit directly in handle ADC CFGR register */
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+ }
+ else
+ {
+ /* else need to check Master ADC CONT bit */
+ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ tmp_cfgr = READ_REG(tmpADC_Master->CFGR1);
+ }
+#else
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Carry on if continuous mode is disabled */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR1_CONT) != ADC_CFGR1_CONT)
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Disable ADC end of sequence conversion interrupt */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+ }
+
+ /* Conversion complete callback */
+ /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */
+ /* to determine if conversion has been triggered from EOC or EOS, */
+ /* possibility to use: */
+ /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvCpltCallback(hadc);
+#else
+ HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear regular group conversion flag */
+ /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
+ /* conversion flags clear induces the release of the preserved data.*/
+ /* Therefore, if the preserved data value is needed, it must be */
+ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+ }
+
+ /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
+ if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
+ (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
+ {
+ /* Update state machine on conversion status if not in error state */
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+ }
+
+ /* Retrieve ADC configuration */
+ tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
+ tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+ )
+ {
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+ }
+ else
+ {
+ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ tmp_cfgr = READ_REG(tmpADC_Master->CFGR1);
+ }
+#else
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Disable interruption if no further conversion upcoming by injected */
+ /* external trigger or by automatic injected conversion with regular */
+ /* group having no further conversion upcoming (same conditions as */
+ /* regular group interruption disabling above), */
+ /* and if injected scan sequence is completed. */
+ if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
+ {
+ if (((READ_BIT(tmp_cfgr, ADC_CFGR1_JAUTO) == 0UL) ||
+ ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+ (READ_BIT(tmp_cfgr, ADC_CFGR1_CONT) == 0UL))))
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+ {
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Disable ADC end of sequence conversion interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ }
+ }
+ }
+
+ /* Injected Conversion complete callback */
+ /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
+ if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
+ if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
+ interruption has been triggered by end of conversion or end of
+ sequence. */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->InjectedConvCpltCallback(hadc);
+#else
+ HAL_ADCEx_InjectedConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear injected group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
+ }
+
+ /* ========== Check Analog watchdog 1 flag ========== */
+ if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Level out of window 1 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->LevelOutOfWindowCallback(hadc);
+#else
+ HAL_ADC_LevelOutOfWindowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+ }
+
+ /* ========== Check analog watchdog 2 flag ========== */
+ if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+ /* Level out of window 2 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->LevelOutOfWindow2Callback(hadc);
+#else
+ HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+ }
+
+ /* ========== Check analog watchdog 3 flag ========== */
+ if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+ /* Level out of window 3 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->LevelOutOfWindow3Callback(hadc);
+#else
+ HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+ }
+
+ /* ========== Check Overrun flag ========== */
+ if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
+ {
+ /* If overrun is set to overwrite previous data (default setting), */
+ /* overrun event is not considered as an error. */
+ /* (cf ref manual "Managing conversions without using the DMA and without */
+ /* overrun ") */
+ /* Exception for usage with DMA overrun event always considered as an */
+ /* error. */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+ {
+ overrun_error = 1UL;
+ }
+ else
+ {
+ /* Check DMA configuration */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT)
+ {
+ overrun_error = 1UL;
+
+ /* Multimode (when feature is available) is enabled,
+ Common Control Register MDMA bits must be checked. */
+ if (LL_ADC_GetMultiDataFormat(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DATA_EACH_ADC)
+ {
+ overrun_error = 1UL;
+ }
+ }
+ else
+#endif /* ADC_MULTIMODE_SUPPORT */
+ {
+ /* Multimode not set or feature not available or ADC independent */
+ if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMNGT) != 0UL)
+ {
+ overrun_error = 1UL;
+ }
+ }
+ }
+
+ if (overrun_error == 1UL)
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+ /* Set ADC error code to overrun */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+
+ /* Error callback */
+ /* Note: In case of overrun, ADC conversion data is preserved until */
+ /* flag OVR is reset. */
+ /* Therefore, old ADC conversion data can be retrieved in */
+ /* function "HAL_ADC_ErrorCallback()". */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
+ HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+
+ /* Clear ADC overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ }
+
+ /* ========== Check Injected context queue overflow flag ========== */
+ if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
+ {
+ /* Change ADC state to overrun state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+ /* Set ADC error code to Injected context queue overflow */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+
+ /* Clear the Injected context queue overflow flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+
+ /* Injected context queue overflow callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->InjectedQueueOverflowCallback(hadc);
+#else
+ HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+
+}
+
+
+/**
+ * @brief Conversion complete callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvCpltCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Conversion DMA half-transfer callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog 1 callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief ADC error callback in non-blocking mode
+ * (ADC conversion with interruption or transfer by DMA).
+ * @note In case of error due to overrun when using ADC with DMA transfer
+ * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
+ * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
+ * - If needed, restart a new ADC conversion using function
+ * "HAL_ADC_Start_DMA()"
+ * (this function is also clearing overrun flag)
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ErrorCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels on regular group
+ (+) Configure the analog watchdog
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure a channel to be assigned to ADC group regular.
+ * @note In case of usage of internal measurement channels (VrefInt, ...):
+ * These internal paths can be disabled using function
+ * HAL_ADC_DeInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes channel into ADC group regular,
+ * following calls to this function can be used to reconfigure
+ * some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
+ * without resetting the ADC.
+ * The setting of these parameters is conditioned to ADC state:
+ * Refer to comments of structure "ADC_ChannelConfTypeDef".
+ * @param hadc ADC handle
+ * @param pConfig Structure of ADC channel assigned to ADC group regular.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmpOffsetShifted;
+ uint32_t tmp_config_common_path_internal_channel;
+ uint32_t tmp_config_path_internal_channel;
+ __IO uint32_t wait_loop_index = 0UL;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank));
+ assert_param(IS_ADC_SAMPLING_TIME(pConfig->SamplingTime));
+ assert_param(IS_ADC_OFFSET_NUMBER(pConfig->OffsetNumber));
+ assert_param(IS_ADC_OFFSET(pConfig->Offset));
+
+ assert_param(IS_ADC_CHANNEL(hadc, pConfig->Channel));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Channel number */
+ /* - Channel rank */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* ADC channels preselection */
+ LL_ADC_SetChannelPreselection(hadc->Instance, pConfig->Channel);
+
+ /* Set ADC group regular sequence: channel on the selected scan sequence rank */
+ LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Channel sampling time */
+ /* - Channel offset */
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ )
+ {
+ /* Set sampling time of the selected ADC channel */
+ LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
+
+ /* Configure the offset: offset enable/disable, channel, offset value */
+
+ /* Shift the offset with respect to the selected ADC resolution. */
+ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
+ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset);
+
+ if (pConfig->OffsetNumber != ADC_OFFSET_NONE)
+ {
+ /* Set ADC selected offset number */
+ LL_ADC_SetOffsetChannel(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel);
+ LL_ADC_SetOffsetLevel(hadc->Instance, pConfig->OffsetNumber, tmpOffsetShifted);
+
+ assert_param(IS_ADC_OFFSET_SIGN(pConfig->OffsetSign));
+ assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSignedSaturation));
+ assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSaturation));
+ /* Signed and unsigned saturation cannot be set at the same time */
+ assert_param(!((pConfig->OffsetSignedSaturation == ENABLE) && (pConfig->OffsetSaturation == ENABLE)));
+
+
+ /* Set ADC offset sign */
+ LL_ADC_SetOffsetSign(hadc->Instance, pConfig->OffsetNumber, pConfig->OffsetSign);
+ /* Set ADC offset signed saturation */
+ LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfig->OffsetNumber, \
+ (pConfig->OffsetSignedSaturation == ENABLE) \
+ ? LL_ADC_OFFSET_SIGNED_SAT_ENABLE \
+ : LL_ADC_OFFSET_SIGNED_SAT_DISABLE);
+ /* Set ADC offset unsigned saturation */
+ LL_ADC_SetOffsetUnsignedSaturation(hadc->Instance, pConfig->OffsetNumber, \
+ (pConfig->OffsetSaturation == ENABLE) \
+ ? LL_ADC_OFFSET_UNSIGNED_SAT_ENABLE \
+ : LL_ADC_OFFSET_UNSIGNED_SAT_DISABLE);
+ }
+ else
+ {
+ /* Scan each offset register to check if the selected channel is targeted.
+ If this is the case, the corresponding offset number is disabled. */
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
+ == __HAL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
+ {
+ LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_1, 0UL);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
+ == __HAL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
+ {
+ LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_2, 0UL);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
+ == __HAL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
+ {
+ LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_3, 0UL);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
+ == __HAL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
+ {
+ LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_4, 0UL);
+ }
+ }
+ }
+
+ /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
+ /* If internal channel selected, enable dedicated internal buffers and */
+ /* paths. */
+ /* Note: these internal measurement paths can be disabled using */
+ /* HAL_ADC_DeInit(). */
+
+ if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
+ {
+ tmp_config_common_path_internal_channel =
+ LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+ tmp_config_path_internal_channel = LL_ADC_GetPathInternalCh(hadc->Instance);
+ /* If the requested internal measurement path has already been enabled, */
+ /* bypass the configuration processing. */
+ if ((pConfig->Channel == ADC_CHANNEL_VREFINT)
+ && ((tmp_config_common_path_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+ {
+ if (ADC_VREFINT_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_common_path_internal_channel);
+ }
+ }
+ else if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+ && ((tmp_config_common_path_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+ {
+ if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_common_path_internal_channel);
+
+ /* Delay for temperature sensor stabilization time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+ }
+ else if ((pConfig->Channel == ADC_CHANNEL_VBAT)
+ && ((tmp_config_common_path_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
+ {
+ if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_VBAT | tmp_config_common_path_internal_channel);
+ }
+ }
+ else if (((pConfig->Channel == ADC_CHANNEL_VDDCORE)
+ && ((tmp_config_path_internal_channel & LL_ADC_PATH_INTERNAL_VDDCORE) == 0UL)))
+ {
+ if (ADC_VDDCORE_INSTANCE(hadc))
+ {
+ LL_ADC_SetPathInternalCh(hadc->Instance, LL_ADC_PATH_INTERNAL_VDDCORE | tmp_config_path_internal_channel);
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ }
+ }
+
+ /* If a conversion is on going on regular group, no update on regular */
+ /* channel could be done on neither of the channel configuration structure */
+ /* parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Configure the analog watchdog.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the selected analog watchdog, successive
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_AnalogWDGConfTypeDef".
+ * @note On this STM32 series, analog watchdog thresholds can be modified
+ * while ADC conversion is on going.
+ * In this case, some constraints must be taken into account:
+ * the programmed threshold values are effective from the next
+ * ADC EOC (end of unitary conversion).
+ * Considering that registers write delay may happen due to
+ * bus activity, this might cause an uncertainty on the
+ * effective timing of the new programmed threshold values.
+ * @param hadc ADC handle
+ * @param pAnalogWDGConfig Structure of ADC analog watchdog configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmp_awd_high_threshold_shifted;
+ uint32_t tmp_awd_low_threshold_shifted;
+ uint32_t tmp_adc_resolution;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber));
+ assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode));
+ assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode));
+
+ if ((pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
+ (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
+ (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
+ {
+ assert_param(IS_ADC_CHANNEL(hadc, pAnalogWDGConfig->Channel));
+ }
+
+ /* Verify thresholds range */
+ if (hadc->Init.OversamplingMode == ENABLE)
+ {
+ /* Case of oversampling enabled: thresholds are compared to oversampling
+ intermediate computation (after ratio, before shift application) */
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc),
+ pAnalogWDGConfig->HighThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc),
+ pAnalogWDGConfig->LowThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
+ }
+ else
+ {
+ /* Verify if thresholds are within the selected ADC resolution */
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on ADC groups regular and injected: */
+ /* - Analog watchdog channels */
+ /* - Analog watchdog thresholds */
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ )
+ {
+ /* Format analog watchdog thresholds data in function of the selected ADC resolution */
+ tmp_adc_resolution = LL_ADC_GetResolution(hadc->Instance);
+ tmp_awd_high_threshold_shifted = __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(tmp_adc_resolution,
+ pAnalogWDGConfig->HighThreshold);
+ tmp_awd_low_threshold_shifted = __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(tmp_adc_resolution,
+ pAnalogWDGConfig->LowThreshold);
+
+ /* Analog watchdog configuration */
+ if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
+ {
+ /* Configuration of analog watchdog: */
+ /* - Set the analog watchdog enable mode: one or overall group of */
+ /* channels, on groups regular and-or injected. */
+ switch (pAnalogWDGConfig->WatchdogMode)
+ {
+ case ADC_ANALOGWATCHDOG_SINGLE_REG:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
+ __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
+ LL_ADC_GROUP_REGULAR));
+ break;
+
+ case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
+ __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
+ LL_ADC_GROUP_INJECTED));
+ break;
+
+ case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
+ __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
+ LL_ADC_GROUP_REGULAR_INJECTED));
+ break;
+
+ case ADC_ANALOGWATCHDOG_ALL_REG:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
+ break;
+
+ case ADC_ANALOGWATCHDOG_ALL_INJEC:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ);
+ break;
+
+ case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
+ break;
+
+ default: /* ADC_ANALOGWATCHDOG_NONE */
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
+ break;
+ }
+
+ /* Set the filtering configuration */
+ assert_param(IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(pAnalogWDGConfig->FilteringConfig));
+ LL_ADC_SetAWDFilteringConfiguration(hadc->Instance, hadc->Instance->AWD1HTR, pAnalogWDGConfig->FilteringConfig);
+
+ /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+ LL_ADC_SetAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber,
+ LL_ADC_AWD_THRESHOLD_HIGH, tmp_awd_high_threshold_shifted);
+ LL_ADC_SetAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber,
+ LL_ADC_AWD_THRESHOLD_LOW, tmp_awd_low_threshold_shifted);
+
+ /* Update state, clear previous result related to AWD1 */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Clear flag ADC analog watchdog */
+ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
+ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
+ /* (in case left enabled by previous ADC operations). */
+ LL_ADC_ClearFlag_AWD1(hadc->Instance);
+
+ /* Configure ADC analog watchdog interrupt */
+ if (pAnalogWDGConfig->ITMode == ENABLE)
+ {
+ LL_ADC_EnableIT_AWD1(hadc->Instance);
+ }
+ else
+ {
+ LL_ADC_DisableIT_AWD1(hadc->Instance);
+ }
+ }
+ /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
+ else
+ {
+ switch (pAnalogWDGConfig->WatchdogMode)
+ {
+ case ADC_ANALOGWATCHDOG_SINGLE_REG:
+ case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
+ case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
+ /* Update AWD by bitfield to keep the possibility to monitor */
+ /* several channels by successive calls of this function. */
+ if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+ {
+ SET_BIT(hadc->Instance->AWD2CR, (1UL \
+ << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
+ }
+ else
+ {
+ SET_BIT(hadc->Instance->AWD3CR, (1UL \
+ << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
+ }
+ break;
+
+ case ADC_ANALOGWATCHDOG_ALL_REG:
+ case ADC_ANALOGWATCHDOG_ALL_INJEC:
+ case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
+ /* Update AWD by bitfield to keep the possibility to monitor */
+ /* several channels by successive calls of this function. */
+ if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+ {
+ SET_BIT(hadc->Instance->AWD2CR, (1UL \
+ << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
+ }
+ else
+ {
+ SET_BIT(hadc->Instance->AWD3CR, (1UL \
+ << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
+ }
+ break;
+
+ default: /* ADC_ANALOGWATCHDOG_NONE */
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
+ break;
+ }
+
+ if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+ {
+ /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+ MODIFY_REG(hadc->Instance->AWD2LTR, ADC_AWD2LTR_LTR, tmp_awd_low_threshold_shifted);
+ MODIFY_REG(hadc->Instance->AWD2HTR, ADC_AWD2HTR_HTR, tmp_awd_high_threshold_shifted);
+ }
+ else
+ {
+ /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+ MODIFY_REG(hadc->Instance->AWD3LTR, ADC_AWD3LTR_LTR, tmp_awd_low_threshold_shifted);
+ MODIFY_REG(hadc->Instance->AWD3HTR, ADC_AWD3HTR_HTR, tmp_awd_high_threshold_shifted);
+ }
+
+ if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+ {
+ /* Update state, clear previous result related to AWD2 */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+ /* Clear flag ADC analog watchdog */
+ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
+ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
+ /* (in case left enabled by previous ADC operations). */
+ LL_ADC_ClearFlag_AWD2(hadc->Instance);
+
+ /* Configure ADC analog watchdog interrupt */
+ if (pAnalogWDGConfig->ITMode == ENABLE)
+ {
+ LL_ADC_EnableIT_AWD2(hadc->Instance);
+ }
+ else
+ {
+ LL_ADC_DisableIT_AWD2(hadc->Instance);
+ }
+ }
+ /* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
+ else
+ {
+ /* Update state, clear previous result related to AWD3 */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+ /* Clear flag ADC analog watchdog */
+ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
+ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
+ /* (in case left enabled by previous ADC operations). */
+ LL_ADC_ClearFlag_AWD3(hadc->Instance);
+
+ /* Configure ADC analog watchdog interrupt */
+ if (pAnalogWDGConfig->ITMode == ENABLE)
+ {
+ LL_ADC_EnableIT_AWD3(hadc->Instance);
+ }
+ else
+ {
+ LL_ADC_DisableIT_AWD3(hadc->Instance);
+ }
+ }
+ }
+
+ }
+ /* If a conversion is on going on ADC group regular or injected, no update */
+ /* could be done on neither of the AWD configuration structure parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+ * @brief ADC Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral state and errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions to get in run-time the status of the
+ peripheral.
+ (+) Check the ADC state
+ (+) Check the ADC error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the ADC handle state.
+ * @note ADC state machine is managed by bitfields, ADC status must be
+ * compared with states bits.
+ * For example:
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
+ * @param hadc ADC handle
+ * @retval ADC handle state (bitfield on 32 bits)
+ */
+uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Return ADC handle state */
+ return hadc->State;
+}
+
+/**
+ * @brief Return the ADC error code.
+ * @param hadc ADC handle
+ * @retval ADC error code (bitfield on 32 bits)
+ */
+uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ return hadc->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Functions ADC Private Functions
+ * @{
+ */
+
+/**
+ * @brief Stop ADC conversion.
+ * @param hadc ADC handle
+ * @param ConversionGroup ADC group regular and/or injected.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type.
+ * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
+ * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
+{
+ uint32_t tickstart;
+ uint32_t conversion_timeout_cpu_cycles = 0UL;
+ uint32_t conversion_group_reassigned = ConversionGroup;
+ uint32_t tmp_ADC_CR_ADSTART_JADSTART;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
+
+ /* Verification if ADC is not already stopped (on regular and injected */
+ /* groups) to bypass this function if not needed. */
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ if ((tmp_adc_is_conversion_on_going_regular != 0UL)
+ || (tmp_adc_is_conversion_on_going_injected != 0UL)
+ )
+ {
+ /* Particular case of continuous auto-injection mode combined with */
+ /* auto-delay mode. */
+ /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
+ /* injected group stop ADC_CR_JADSTP). */
+ /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
+ /* (see reference manual). */
+ if (((hadc->Instance->CFGR1 & ADC_CFGR1_JAUTO) != 0UL)
+ && (hadc->Init.ContinuousConvMode == ENABLE)
+ && (hadc->Init.LowPowerAutoWait == ENABLE)
+ )
+ {
+ /* Use stop of regular group */
+ conversion_group_reassigned = ADC_REGULAR_GROUP;
+
+ /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
+ while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
+ {
+ if (conversion_timeout_cpu_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ conversion_timeout_cpu_cycles ++;
+ }
+
+ /* Clear JEOS */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
+ }
+
+ /* Stop potential conversion on going on ADC group regular */
+ if (conversion_group_reassigned != ADC_INJECTED_GROUP)
+ {
+ /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+ {
+ if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
+ {
+ /* Stop ADC group regular conversion */
+ LL_ADC_REG_StopConversion(hadc->Instance);
+ }
+ }
+ }
+
+ /* Stop potential conversion on going on ADC group injected */
+ if (conversion_group_reassigned != ADC_REGULAR_GROUP)
+ {
+ /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+ {
+ if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
+ {
+ /* Stop ADC group injected conversion */
+ LL_ADC_INJ_StopConversion(hadc->Instance);
+ }
+ }
+ }
+
+ /* Selection of start and stop bits with respect to the regular or injected group */
+ switch (conversion_group_reassigned)
+ {
+ case ADC_REGULAR_INJECTED_GROUP:
+ tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
+ break;
+ case ADC_INJECTED_GROUP:
+ tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
+ break;
+ /* Case ADC_REGULAR_GROUP only*/
+ default:
+ tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
+ break;
+ }
+
+ /* Wait for conversion effectively stopped */
+ tickstart = HAL_GetTick();
+
+ while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the selected ADC.
+ * @note Prerequisite condition to use this function: ADC must be disabled
+ * and voltage regulator must be enabled (done into HAL_ADC_Init()).
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
+{
+ uint32_t tickstart;
+ uint32_t wait_loop_index;
+
+ /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
+ /* enabling phase not yet completed: flag ADC ready not yet set). */
+ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
+ /* causes: ADC clock not running, ...). */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ /* Check if conditions to enable the ADC are fulfilled */
+ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
+ | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+
+ /* Enable the ADC peripheral */
+ LL_ADC_Enable(hadc->Instance);
+
+ if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))
+ & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
+ {
+ /* Delay for temperature sensor buffer stabilization time */
+ /* Note: Value LL_ADC_DELAY_TEMPSENSOR_STAB_US used instead of */
+ /* LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US because needed */
+ /* in case of ADC enable after a system wake up */
+ /* from low power mode. */
+
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+
+ /* Wait for ADC effectively enabled */
+ tickstart = HAL_GetTick();
+
+ while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+ {
+ /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
+ has been cleared (after a calibration), ADEN bit is reset by the
+ calibration logic.
+ The workaround is to continue setting ADEN until ADRDY is becomes 1.
+ Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
+ 4 ADC clock cycle duration */
+ /* Note: Test of ADC enabled required due to hardware constraint to */
+ /* not enable ADC if already enabled. */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ LL_ADC_Enable(hadc->Instance);
+ }
+
+ if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the selected ADC.
+ * @note Prerequisite condition to use this function: ADC conversions must be
+ * stopped.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
+{
+ uint32_t tickstart;
+ const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
+
+ /* Verification if ADC is not already disabled: */
+ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
+ /* disabled. */
+ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+ && (tmp_adc_is_disable_on_going == 0UL)
+ )
+ {
+ /* Check if conditions to disable the ADC are fulfilled */
+ if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
+ {
+ /* Disable the ADC peripheral */
+ LL_ADC_Disable(hadc->Instance);
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+
+ /* Wait for ADC effectively disabled */
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DMA transfer complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Update state machine on conversion status if not in error state */
+ if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going */
+ /* to disable interruption. */
+ /* Is it the end of the regular sequence ? */
+ if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
+ {
+ /* Are conversions software-triggered ? */
+ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+ {
+ /* Is CONT bit set ? */
+ if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_CONT) == 0UL)
+ {
+ /* CONT bit is not set, no more conversions expected */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* DMA End of Transfer interrupt was triggered but conversions sequence
+ is not over. If DMACFG is set to 0, conversions are stopped. */
+ if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT) == 0UL)
+ {
+ /* DMACFG bit is not set, conversions are stopped. */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ }
+
+ /* Conversion complete callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvCpltCallback(hadc);
+#else
+ HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+ else /* DMA and-or internal error occurred */
+ {
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
+ {
+ /* Call HAL ADC Error Callback function */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
+ HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Call ADC DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback(hdma);
+ }
+ }
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Half conversion callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvHalfCpltCallback(hadc);
+#else
+ HAL_ADC_ConvHalfCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA error callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void ADC_DMAError(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+
+ /* Set ADC error code to DMA error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
+
+ /* Error callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
+ HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_adc_ex.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_adc_ex.c
new file mode 100644
index 0000000000..a6154954b9
--- /dev/null
+++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_adc_ex.c
@@ -0,0 +1,2352 @@
+/**
+ ******************************************************************************
+ * @file stm32u3xx_hal_adc_ex.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Converter (ADC)
+ * peripheral:
+ * + Peripheral Control functions
+ * Other functions (generic functions) are available in file
+ * "stm32u3xx_hal_adc.c".
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ [..]
+ (@) Sections "ADC peripheral features" and "How to use this driver" are
+ available in file of generic functions "stm32u3xx_hal_adc.c".
+ [..]
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u3xx_hal.h"
+
+/** @addtogroup STM32U3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADCEx ADCEx
+ * @brief ADC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
+ * @{
+ */
+
+#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
+ ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
+ ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime
+ once the ADC is enabled */
+
+#define ADC_JSQR_LOW_FIELDS (ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN) /*!< ADC_JSQR fields of parameters that can be updated anytime
+ once the ADC is enabled */
+
+/* Fixed timeout value for ADC calibration. */
+/* Values defined to be higher than worst cases: low clock frequency, */
+/* maximum prescalers. */
+/* Ex of profile low frequency : */
+/* Convertion_cycle = (12.5 + 1500.5) = 1513 */
+/* Calibration_time MAX = 1513 / f_ADC */
+/* = 1513 / (f_CPU/256) = 387328 CPU cycles */
+#define ADC_CALIBRATION_TIMEOUT (387328UL) /*!< ADC calibration time-out value (unit: CPU cycles) */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
+ * @brief Extended IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+ (+) Perform the ADC self-calibration for single and differential ending.
+ (+) Get calibration factors for single or differential ending.
+ (+) Set calibration factors for single or differential ending.
+
+ (+) Start conversion of ADC group injected.
+ (+) Stop conversion of ADC group injected.
+ (+) Poll for conversion complete on ADC group injected.
+ (+) Get result of ADC group injected channel conversion.
+ (+) Start conversion of ADC group injected and enable interruptions.
+ (+) Stop conversion of ADC group injected and disable interruptions.
+
+ (+) When multimode feature is available, start multimode and enable DMA transfer.
+ (+) Stop multimode and disable ADC DMA transfer.
+ (+) Get result of multimode conversion.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform an ADC automatic self-calibration
+ * Calibration prerequisite: ADC must be disabled (execute this
+ * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+ * @param hadc ADC handle
+ * @param SingleDiff Selection of single-ended or differential input
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
+{
+ UNUSED(SingleDiff);
+ HAL_StatusTypeDef tmp_hal_status;
+ __IO uint32_t wait_loop_index = 0UL;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Calibration prerequisite: ADC must be disabled. */
+
+ /* Disable the ADC (if not already disabled) */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+ /* Start ADC calibration */
+ LL_ADC_StartCalibration(hadc->Instance);
+
+ /* Wait for calibration completion */
+ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
+ {
+
+ wait_loop_index++;
+ if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Note: No need to update variable "tmp_hal_status" here: already set */
+ /* to state "HAL_ERROR" by function disabling the ADC. */
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Get the calibration factor.
+ * @param hadc ADC handle.
+ * @param SingleDiff This parameter can be only:
+ * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
+ * @retval Calibration value.
+ */
+uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+ /* Return the selected ADC calibration value */
+ return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff);
+}
+
+/**
+ * @brief Set the calibration factor to overwrite automatic conversion result.
+ * ADC must be enabled and no conversion is ongoing.
+ * @param hadc ADC handle
+ * @param SingleDiff This parameter can be only:
+ * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
+ * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
+ uint32_t CalibrationFactor)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+ assert_param(IS_ADC_CALFACT(CalibrationFactor));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Verification of hardware constraints before modifying the calibration */
+ /* factors register: ADC must be enabled, no conversion on going. */
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ if ((LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ && (tmp_adc_is_conversion_on_going_regular == 0UL)
+ && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ )
+ {
+ /* Set the selected ADC calibration value */
+ LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor);
+ }
+ else
+ {
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ /* Update ADC error code */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ /* Update ADC state machine to error */
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+/**
+ * @brief Enable ADC, start conversion of injected group.
+ * @note Interruptions enabled in this function: None.
+ * @note Case of multimode enabled when multimode feature is available:
+ * HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
+ * then for ADC master.
+ * For ADC slave, ADC is enabled only (conversion is not started).
+ * For ADC master, ADC is enabled and multimode conversion is started.
+ * @param hadc ADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t tmp_config_injected_queue;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+ {
+ return HAL_BUSY;
+ }
+ else
+ {
+ /* In case of software trigger detection enabled, JQDIS must be set
+ (which can be done only if ADSTART and JADSTART are both cleared).
+ If JQDIS is not set at that point, returns an error
+ - since software trigger detection is disabled. User needs to
+ resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
+ - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
+ the queue is empty */
+ tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JQDIS);
+
+ if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
+ && (tmp_config_injected_queue == 0UL)
+ )
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Check if a regular conversion is ongoing */
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ {
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+ - if ADC instance is master or if multimode feature is not available
+ - if multimode setting is disabled (ADC instance slave in independent mode) */
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ )
+ {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Clear ADC group injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Enable conversion of injected group, if automatic injected conversion */
+ /* is disabled. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (when multimode feature is available): */
+ /* if ADC is slave, */
+ /* - ADC is enabled only (conversion is not started), */
+ /* - if multimode only concerns regular conversion, ADC is enabled */
+ /* and conversion is started. */
+ /* If ADC is master or independent, */
+ /* - ADC is enabled and conversion is started. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+ )
+ {
+ /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+ {
+ LL_ADC_INJ_StartConversion(hadc->Instance);
+ }
+ }
+ else
+ {
+ /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#else
+ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+ {
+ /* Start ADC group injected conversion */
+ LL_ADC_INJ_StartConversion(hadc->Instance);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ }
+ else
+ {
+ __HAL_UNLOCK(hadc);
+ }
+
+ return tmp_hal_status;
+ }
+}
+
+/**
+ * @brief Stop conversion of injected channels. Disable ADC peripheral if
+ * no regular conversion is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @note If injected group mode auto-injection is enabled,
+ * function HAL_ADC_Stop must be used.
+ * @note In case of multimode enabled (when multimode feature is available),
+ * HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
+ * For ADC master, conversion is stopped and ADC is disabled.
+ * For ADC slave, ADC is disabled only (conversion stop of ADC master
+ * has already stopped conversion of ADC slave).
+ * @param hadc ADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going on injected group only. */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if injected conversions are effectively stopped */
+ /* and if no conversion on regular group is on-going */
+ if (tmp_hal_status == HAL_OK)
+ {
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on injected group is stopped, but ADC not disabled since */
+ /* conversion on regular group is still running. */
+ else
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Wait for injected group conversion to be completed.
+ * @param hadc ADC handle
+ * @param Timeout Timeout value in millisecond.
+ * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is
+ * checked and cleared depending on AUTDLY bit status.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t tmp_Flag_End;
+ uint32_t tmp_adc_inj_is_trigger_source_sw_start;
+ uint32_t tmp_adc_reg_is_trigger_source_sw_start;
+ uint32_t tmp_cfgr;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ const ADC_TypeDef *tmpADC_Master;
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* If end of sequence selected */
+ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+ {
+ tmp_Flag_End = ADC_FLAG_JEOS;
+ }
+ else /* end of conversion selected */
+ {
+ tmp_Flag_End = ADC_FLAG_JEOC;
+ }
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait until End of Conversion or Sequence flag is raised */
+ while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Retrieve ADC configuration */
+ tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
+ tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
+ /* Get relevant register CFGR1 in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+ )
+ {
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+ }
+ else
+ {
+ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ tmp_cfgr = READ_REG(tmpADC_Master->CFGR1);
+ }
+#else
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+
+ /* Determine whether any further conversion upcoming on group injected */
+ /* by external trigger or by automatic injected conversion */
+ /* from group regular. */
+ if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
+ ((READ_BIT(tmp_cfgr, ADC_CFGR1_JAUTO) == 0UL) &&
+ ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+ (READ_BIT(tmp_cfgr, ADC_CFGR1_CONT) == 0UL))))
+ {
+ /* Check whether end of sequence is reached */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+
+ }
+ }
+
+ /* Clear polled flag */
+ if (tmp_Flag_End == ADC_FLAG_JEOS)
+ {
+ /* Clear end of sequence JEOS flag of injected group if low power feature */
+ /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */
+ /* For injected groups, no new conversion will start before JEOS is */
+ /* cleared. */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR1_AUTDLY) == 0UL)
+ {
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+ }
+ }
+ else
+ {
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+ }
+
+ /* Return API HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable ADC, start conversion of injected group with interruption.
+ * @note Interruptions enabled in this function according to initialization
+ * setting : JEOC (end of conversion) or JEOS (end of sequence)
+ * @note Case of multimode enabled (when multimode feature is enabled):
+ * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
+ * then for ADC master.
+ * For ADC slave, ADC is enabled only (conversion is not started).
+ * For ADC master, ADC is enabled and multimode conversion is started.
+ * @param hadc ADC handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t tmp_config_injected_queue;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+ {
+ return HAL_BUSY;
+ }
+ else
+ {
+ /* In case of software trigger detection enabled, JQDIS must be set
+ (which can be done only if ADSTART and JADSTART are both cleared).
+ If JQDIS is not set at that point, returns an error
+ - since software trigger detection is disabled. User needs to
+ resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
+ - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
+ the queue is empty */
+ tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JQDIS);
+
+ if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
+ && (tmp_config_injected_queue == 0UL)
+ )
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Check if a regular conversion is ongoing */
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ {
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+ - if ADC instance is master or if multimode feature is not available
+ - if multimode setting is disabled (ADC instance slave in independent mode) */
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ )
+ {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Clear ADC group injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Enable ADC Injected context queue overflow interrupt if this feature */
+ /* is enabled. */
+ if ((hadc->Instance->CFGR1 & ADC_CFGR1_JQM) != 0UL)
+ {
+ __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
+ }
+
+ /* Enable ADC end of conversion interrupt */
+ switch (hadc->Init.EOCSelection)
+ {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+ break;
+ }
+
+ /* Enable conversion of injected group, if automatic injected conversion */
+ /* is disabled. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (when multimode feature is available): */
+ /* if ADC is slave, */
+ /* - ADC is enabled only (conversion is not started), */
+ /* - if multimode only concerns regular conversion, ADC is enabled */
+ /* and conversion is started. */
+ /* If ADC is master or independent, */
+ /* - ADC is enabled and conversion is started. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+ )
+ {
+ /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+ {
+ LL_ADC_INJ_StartConversion(hadc->Instance);
+ }
+ }
+ else
+ {
+ /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#else
+ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+ {
+ /* Start ADC group injected conversion */
+ LL_ADC_INJ_StartConversion(hadc->Instance);
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ }
+ else
+ {
+ __HAL_UNLOCK(hadc);
+ }
+
+ return tmp_hal_status;
+ }
+}
+
+/**
+ * @brief Stop conversion of injected channels, disable interruption of
+ * end-of-conversion. Disable ADC peripheral if no regular conversion
+ * is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @note If injected group mode auto-injection is enabled,
+ * function HAL_ADC_Stop must be used.
+ * @note Case of multimode enabled (when multimode feature is available):
+ * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
+ * then for ADC slave.
+ * For ADC master, conversion is stopped and ADC is disabled.
+ * For ADC slave, ADC is disabled only (conversion stop of ADC master
+ * has already stopped conversion of ADC slave).
+ * @note In case of auto-injection mode, HAL_ADC_Stop() must be used.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going on injected group only. */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if injected conversions are effectively stopped */
+ /* and if no conversion on the other group (regular group) is intended to */
+ /* continue. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC end of conversion interrupt for injected channels */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
+
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on injected group is stopped, but ADC not disabled since */
+ /* conversion on regular group is still running. */
+ else
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA.
+ * @note Multimode must have been previously configured using
+ * HAL_ADCEx_MultiModeConfigChannel() function.
+ * Interruptions enabled in this function:
+ * overrun, DMA half transfer, DMA transfer complete.
+ * Each of these interruptions has its dedicated callback function.
+ * @note Conversion data of both multimode ADC instances will take each one buffer element, therefore
+ buffer total size should be doubled to get similar data size for each ADC instance vs independent mode.
+ * @note State field of Slave ADC handle is not updated in this configuration:
+ * user should not rely on it for information related to Slave regular
+ * conversions.
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+ * @param pData Destination Buffer address.
+ * @param Length Length of data to be transferred from ADC peripheral to memory (unit: number of transfers)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ ADC_HandleTypeDef tmphadcSlave;
+ ADC_Common_TypeDef *tmp_adc_common;
+ uint32_t LengthInBytes;
+ DMA_NodeConfTypeDef node_conf;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+ {
+ return HAL_BUSY;
+ }
+ else
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+ ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+ if (tmphadcSlave.Instance == NULL)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Enable the ADC peripherals: master and slave (in case if not already */
+ /* enabled previously) */
+ tmp_hal_status = ADC_Enable(hadc);
+ if (tmp_hal_status == HAL_OK)
+ {
+ tmp_hal_status = ADC_Enable(&tmphadcSlave);
+ }
+
+ /* Start multimode conversion of ADCs pair */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP),
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
+
+ /* Pointer to the common control register */
+ tmp_adc_common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Enable ADC overrun interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Start the DMA channel */
+ if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+ {
+ if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL))
+ {
+ /* Length should be converted to number of bytes */
+ if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hadc->DMA_Handle->LinkedListQueue->Head) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Length should be converted to number of bytes */
+ if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+ {
+ /* Word -> Bytes */
+ LengthInBytes = Length * 4U;
+ }
+ else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+ {
+ /* Halfword -> Bytes */
+ LengthInBytes = Length * 2U;
+ }
+ else /* Bytes */
+ {
+ /* Same size already expressed in Bytes */
+ LengthInBytes = Length;
+ }
+
+ hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)LengthInBytes;
+ hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+ (uint32_t)&tmp_adc_common->CDR;
+ hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+ tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle);
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Length should be converted to number of bytes */
+ if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+ {
+ /* Word -> Bytes */
+ LengthInBytes = Length * 4U;
+ }
+ else if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+ {
+ /* Halfword -> Bytes */
+ LengthInBytes = Length * 2U;
+ }
+ else /* Bytes */
+ {
+ /* Same size already expressed in Bytes */
+ LengthInBytes = Length;
+ }
+
+ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmp_adc_common->CDR, (uint32_t)pData,
+ LengthInBytes);
+ }
+
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ }
+ }
+ else
+ {
+ __HAL_UNLOCK(hadc);
+ }
+
+ return tmp_hal_status;
+ }
+}
+
+/**
+ * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
+ * @note Multimode is kept enabled after this function. MultiMode DMA bits
+ * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
+ * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
+ * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
+ * resort to HAL_ADCEx_DisableMultiMode() API.
+ * @note In case of DMA configured in circular mode, function
+ * HAL_ADC_Stop_DMA() must be called after this function with handle of
+ * ADC slave, to properly disable the DMA channel.
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t tickstart;
+ ADC_HandleTypeDef tmphadcSlave;
+ uint32_t tmphadcSlave_conversion_on_going;
+ HAL_StatusTypeDef tmphadcSlave_disable_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+
+ /* 1. Stop potential multimode conversion on going, on regular and injected groups */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+ ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+ if (tmphadcSlave.Instance == NULL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Procedure to disable the ADC peripheral: wait for conversions */
+ /* effectively stopped (ADC master and ADC slave), then disable ADC */
+
+ /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
+ tickstart = HAL_GetTick();
+
+ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+ || (tmphadcSlave_conversion_on_going == 1UL)
+ )
+ {
+ if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+ || (tmphadcSlave_conversion_on_going == 1UL)
+ )
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ }
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop */
+ /* while DMA transfer is on going) */
+ /* Note: DMA channel of ADC slave should be stopped after this function */
+ /* with HAL_ADC_Stop_DMA() API. */
+ if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
+ {
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status == HAL_ERROR)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripherals: master and slave */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
+ /* memory a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ tmphadcSlave_disable_status = ADC_Disable(&tmphadcSlave);
+ if ((ADC_Disable(hadc) == HAL_OK) &&
+ (tmphadcSlave_disable_status == HAL_OK))
+ {
+ tmp_hal_status = HAL_OK;
+ }
+ }
+ else
+ {
+ /* In case of error, attempt to disable ADC master and slave without status assert */
+ (void) ADC_Disable(hadc);
+ (void) ADC_Disable(&tmphadcSlave);
+ }
+
+ /* Set ADC state (ADC master) */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration.
+ * @note Multimode data contains ADC master and slave conversion data
+ * concatenated. Data is usable under conditions of ADC multimode
+ * data format selected and data width,
+ * refer to @ref ADCEx_Dual_Mode_Data_Format.
+ * The recommended method, without any constraint, is to use
+ * DMA transfer. refer to @ref HAL_ADCEx_MultiModeStart_DMA.
+ * @note Another solution exists to retrieve multimode conversion data
+ * without packing (refer to @ref LL_ADC_REG_ReadMultiConvNoPacking)
+ * but with timing constraints.
+ * The recommended method, without any constraint, is to use
+ * DMA transfer. refer to @ref HAL_ADCEx_MultiModeStart_DMA.
+ * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
+ * @retval The converted data values.
+ */
+uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc)
+{
+ const ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */
+ UNUSED(hadc);
+
+ /* Pointer to the common control register */
+ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+ /* Return the multi mode conversion value */
+ return tmpADC_Common->CDR;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Get ADC injected group conversion result.
+ * @note Reading register JDRx automatically clears ADC flag JEOC
+ * (ADC group injected end of unitary conversion).
+ * @note This function returns an unsigned value. Using the ADC offset
+ * feature can result in negative conversion data.
+ * To read conversion data with ADC offset enabled
+ * use function @ref HAL_ADCEx_InjectedGetSignedValue.
+ * @note This function does not clear ADC flag JEOS
+ * (ADC group injected end of sequence conversion)
+ * Occurrence of flag JEOS rising:
+ * - If sequencer is composed of 1 rank, flag JEOS is equivalent
+ * to flag JEOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag JEOC only is raised, at the end of the scan sequence
+ * both flags JEOC and EOS are raised.
+ * Flag JEOS must not be cleared by this function because
+ * it would not be compliant with low power features
+ * (feature low power auto-wait, not available on all STM32 families).
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
+ * @param hadc ADC handle
+ * @param InjectedRank the converted ADC injected rank.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
+ * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
+ * @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
+ * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
+ * @retval ADC group injected conversion data
+ */
+uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
+{
+ uint32_t tmp_jdr;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+
+ /* Get ADC converted value */
+ switch (InjectedRank)
+ {
+ case ADC_INJECTED_RANK_4:
+ tmp_jdr = hadc->Instance->JDR4;
+ break;
+ case ADC_INJECTED_RANK_3:
+ tmp_jdr = hadc->Instance->JDR3;
+ break;
+ case ADC_INJECTED_RANK_2:
+ tmp_jdr = hadc->Instance->JDR2;
+ break;
+ case ADC_INJECTED_RANK_1:
+ default:
+ tmp_jdr = hadc->Instance->JDR1;
+ break;
+ }
+
+ /* Return ADC converted value */
+ return tmp_jdr;
+}
+
+/**
+ * @brief Get ADC injected group conversion result.
+ * @note Reading register JDRx automatically clears ADC flag JEOC
+ * (ADC group injected end of unitary conversion).
+ * @note This function does not clear ADC flag JEOS
+ * (ADC group injected end of sequence conversion)
+ * Occurrence of flag JEOS rising:
+ * - If sequencer is composed of 1 rank, flag JEOS is equivalent
+ * to flag JEOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag JEOC only is raised, at the end of the scan sequence
+ * both flags JEOC and EOS are raised.
+ * Flag JEOS must not be cleared by this function because
+ * it would not be compliant with low power features
+ * (feature low power auto-wait, not available on all STM32 families).
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
+ * @param hadc ADC handle
+ * @param InjectedRank the converted ADC injected rank.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
+ * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
+ * @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
+ * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
+ * @retval ADC group injected conversion data
+ */
+int32_t HAL_ADCEx_InjectedGetSignedValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
+{
+ int32_t tmp_jdr;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+
+ /* Get ADC converted value */
+ switch (InjectedRank)
+ {
+ case ADC_INJECTED_RANK_4:
+ tmp_jdr = (int32_t)(hadc->Instance->JDR4);
+ break;
+ case ADC_INJECTED_RANK_3:
+ tmp_jdr = (int32_t)(hadc->Instance->JDR3);
+ break;
+ case ADC_INJECTED_RANK_2:
+ tmp_jdr = (int32_t)(hadc->Instance->JDR2);
+ break;
+ case ADC_INJECTED_RANK_1:
+ default:
+ tmp_jdr = (int32_t)(hadc->Instance->JDR1);
+ break;
+ }
+
+ /* Return ADC converted value */
+ return tmp_jdr;
+}
+
+/**
+ * @brief Injected conversion complete callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Injected context queue overflow callback.
+ * @note This callback is called if injected context queue is enabled
+ (parameter "QueueInjectedContext" in injected channel configuration)
+ and if a new injected context is set when queue is full (maximum 2
+ contexts).
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog 2 callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog 3 callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
+ */
+}
+
+
+/**
+ * @brief End Of Sampling callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected channels in
+ * case of auto_injection mode), disable ADC peripheral if no
+ * conversion is on going on injected group.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential regular conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if regular conversions are effectively stopped
+ and if no injected conversions are on-going */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Clear HAL_ADC_STATE_REG_BUSY bit */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on injected group is stopped, but ADC not disabled since */
+ /* conversion on regular group is still running. */
+ else
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+
+/**
+ * @brief Stop ADC conversion of ADC groups regular and injected,
+ * disable interrution of end-of-conversion,
+ * disable ADC peripheral if no conversion is on going
+ * on injected group.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential regular conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped
+ and if no injected conversion is on-going */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Clear HAL_ADC_STATE_REG_BUSY bit */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ /* Disable all regular-related interrupts */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+ /* 2. Disable ADC peripheral if no injected conversions are on-going */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ tmp_hal_status = ADC_Disable(hadc);
+ /* if no issue reported */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable ADC DMA transfer, disable
+ * ADC peripheral if no conversion is on going
+ * on injected group.
+ * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
+ * For multimode (when multimode feature is available),
+ * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential regular conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped
+ and if no injected conversion is on-going */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Clear HAL_ADC_STATE_REG_BUSY bit */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ /* Disable ADC DMA (ADC DMA configuration ADC_CFGR1_DMACFG is kept) */
+ MODIFY_REG(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT_0 | ADC_CFGR1_DMNGT_1, 0UL);
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* while DMA transfer is on going) */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripheral */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, */
+ /* to keep in memory a potential failing status. */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ if (tmp_hal_status == HAL_OK)
+ {
+ tmp_hal_status = ADC_Disable(hadc);
+ }
+ else
+ {
+ (void)ADC_Disable(hadc);
+ }
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected
+ * conversion is on-going.
+ * @note Multimode is kept enabled after this function. Multimode DMA bits
+ * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
+ * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
+ * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
+ * resort to HAL_ADCEx_DisableMultiMode() API.
+ * @note In case of DMA configured in circular mode, function
+ * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
+ * ADC slave, to properly disable the DMA channel.
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t tickstart;
+ ADC_HandleTypeDef tmphadcSlave;
+ uint32_t tmphadcSlave_conversion_on_going;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+
+ /* 1. Stop potential multimode conversion on going, on regular groups */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Clear HAL_ADC_STATE_REG_BUSY bit */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+ ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+ if (tmphadcSlave.Instance == NULL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Procedure to disable the ADC peripheral: wait for conversions */
+ /* effectively stopped (ADC master and ADC slave), then disable ADC */
+
+ /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
+ tickstart = HAL_GetTick();
+
+ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+ || (tmphadcSlave_conversion_on_going == 1UL)
+ )
+ {
+ if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+ || (tmphadcSlave_conversion_on_going == 1UL)
+ )
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ }
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop */
+ /* while DMA transfer is on going) */
+ /* Note: DMA channel of ADC slave should be stopped after this function */
+ /* with HAL_ADCEx_RegularStop_DMA() API. */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripherals: master and slave if no injected */
+ /* conversion is on-going. */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
+ /* memory a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ tmp_hal_status = ADC_Disable(hadc);
+ if (tmp_hal_status == HAL_OK)
+ {
+ if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) == 0UL)
+ {
+ tmp_hal_status = ADC_Disable(&tmphadcSlave);
+ }
+ }
+ }
+
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Both Master and Slave ADC's could be disabled. Update Master State */
+ /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* injected (Master or Slave) conversions are still on-going,
+ no Master State change */
+ }
+ }
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
+ * @brief ADC Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels on injected group
+ (+) Configure multimode (when multimode feature is available)
+ (+) Disable ADC voltage regulator
+ (+) Enter ADC deep-power-down mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure a channel to be assigned to ADC group injected.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes injected group, following calls to this
+ * function can be used to reconfigure some parameters of structure
+ * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
+ * The setting of these parameters is conditioned to ADC state:
+ * Refer to comments of structure "ADC_InjectionConfTypeDef".
+ * @note In case of usage of internal measurement channels (VrefInt, ...):
+ * These internal paths can be disabled using function
+ * HAL_ADC_DeInit().
+ * @param hadc ADC handle
+ * @param pConfigInjected Structure of ADC injected group and ADC channel for
+ * injected group.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
+ const ADC_InjectionConfTypeDef *pConfigInjected)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmpOffsetShifted;
+ uint32_t tmp_config_common_path_internal_channel;
+ uint32_t tmp_config_path_internal_channel;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+ __IO uint32_t wait_loop_index = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SAMPLING_TIME(pConfigInjected->InjectedSamplingTime));
+ assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->AutoInjectedConv));
+ assert_param(IS_ADC_EXTTRIGINJEC_EDGE(pConfigInjected->ExternalTrigInjecConvEdge));
+ assert_param(IS_ADC_EXTTRIGINJEC(hadc->Instance, pConfigInjected->ExternalTrigInjecConv));
+ assert_param(IS_ADC_OFFSET_NUMBER(pConfigInjected->InjectedOffsetNumber));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset));
+ assert_param(IS_ADC_OFFSET_SIGN(pConfigInjected->InjectedOffsetSign));
+ assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjecOversamplingMode));
+
+ if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ {
+ assert_param(IS_ADC_INJECTED_RANK(pConfigInjected->InjectedRank));
+ assert_param(IS_ADC_INJECTED_NB_CONV(pConfigInjected->InjectedNbrOfConversion));
+ assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedDiscontinuousConvMode));
+ }
+
+ /* Check offset range according to oversampling setting */
+ if (hadc->Init.OversamplingMode == ENABLE)
+ {
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc),
+ pConfigInjected->InjectedOffset / (hadc->Init.Oversampling.Ratio + 1U)));
+ }
+ else
+ {
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset));
+ }
+
+ /* JDISCEN and JAUTO bits can't be set at the same time */
+ assert_param(!((pConfigInjected->InjectedDiscontinuousConvMode == ENABLE) \
+ && (pConfigInjected->AutoInjectedConv == ENABLE)));
+
+ /* DISCEN and JAUTO bits can't be set at the same time */
+ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (pConfigInjected->AutoInjectedConv == ENABLE)));
+
+ assert_param(IS_ADC_CHANNEL(hadc, pConfigInjected->InjectedChannel));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Configuration of injected group sequencer: */
+ /* - if scan mode is disabled: */
+ /* * Injected channels sequence length is set to 0x00: 1 channel */
+ /* converted (channel on injected rank 1) */
+ /* Parameter "InjectedNbrOfConversion" is discarded. */
+ /* - if scan mode is enabled: */
+ /* * Injected channels sequence length is set to parameter */
+ /* "InjectedNbrOfConversion". */
+ /* Note: Scan mode is not present by hardware on this device, but used */
+ /* by software for alignment over all STM32 devices. */
+
+ if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
+ (pConfigInjected->InjectedNbrOfConversion == 1U))
+ {
+ /* Configuration of context register JSQR: */
+ /* - number of ranks in injected group sequencer: fixed to 1st rank */
+ /* (scan mode disabled, only rank 1 used) */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity */
+ /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
+
+ if (pConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
+ {
+ /* Enable external trigger if trigger selection is different of */
+ /* software start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+ {
+ MODIFY_REG(hadc->Instance->JSQR,
+ ADC_JSQR_FIELDS,
+ ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
+ | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
+ | pConfigInjected->ExternalTrigInjecConvEdge);
+ }
+ else
+ {
+ MODIFY_REG(hadc->Instance->JSQR,
+ ADC_JSQR_FIELDS,
+ ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
+ }
+ }
+ }
+ else
+ {
+ /* Case of scan mode enabled, several channels to set into injected group */
+ /* sequencer. */
+
+ MODIFY_REG(hadc->Instance->JSQR,
+ ADC_JSQR_LOW_FIELDS,
+ ADC_JSQR_RK(pConfigInjected->InjectedChannel, pConfigInjected->InjectedRank)
+ | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
+ | pConfigInjected->ExternalTrigInjecConvEdge
+ | ((pConfigInjected->InjectedNbrOfConversion - 1U) & ADC_JSQR_JL));
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on injected group: */
+ /* - Injected discontinuous mode: can be enabled only if auto-injected */
+ /* mode is disabled. */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* ADC channels preselection */
+ LL_ADC_SetChannelPreselection(hadc->Instance, pConfigInjected->InjectedChannel);
+
+ /* If auto-injected mode is disabled: no constraint */
+ if (pConfigInjected->AutoInjectedConv == DISABLE)
+ {
+ MODIFY_REG(hadc->Instance->CFGR1,
+ ADC_CFGR1_JDISCEN,
+ ADC_CFGR1_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode));
+ }
+ /* If auto-injected mode is enabled: Injected discontinuous setting is */
+ /* discarded. */
+ else
+ {
+ MODIFY_REG(hadc->Instance->CFGR1,
+ ADC_CFGR1_JDISCEN,
+ ADC_CFGR1_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode));
+ }
+
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular and injected groups: */
+ /* - Automatic injected conversion: can be enabled if injected group */
+ /* external triggers are disabled. */
+ /* - Channel sampling time */
+ /* - Channel offset */
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ )
+ {
+ /* If injected group external triggers are disabled (set to injected */
+ /* software start): no constraint */
+ if ((pConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
+ || (pConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
+ {
+ if (pConfigInjected->AutoInjectedConv == ENABLE)
+ {
+ SET_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO);
+ }
+ else
+ {
+ CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO);
+ }
+ }
+ /* If Automatic injected conversion was intended to be set and could not */
+ /* due to injected group external triggers enabled, error is reported. */
+ else
+ {
+ if (pConfigInjected->AutoInjectedConv == ENABLE)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ else
+ {
+ CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO);
+ }
+ }
+
+ if (pConfigInjected->InjecOversamplingMode == ENABLE)
+ {
+ assert_param(IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio));
+ assert_param(IS_ADC_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift));
+
+ /* JOVSE must be reset in case of triggered regular mode */
+ assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) ==
+ (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
+
+ /* Configuration of Injected Oversampler: */
+ /* - Oversampling Ratio */
+ /* - Right bit shift */
+
+ /* Enable OverSampling mode */
+ MODIFY_REG(hadc->Instance->CFGR2,
+ ADC_CFGR2_JOVSE |
+ ADC_CFGR2_OVSR |
+ ADC_CFGR2_OVSS,
+ ADC_CFGR2_JOVSE |
+ ((pConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
+ pConfigInjected->InjecOversampling.RightBitShift
+ );
+ }
+ else
+ {
+ /* Disable Regular OverSampling */
+ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
+ }
+
+ /* Set sampling time of the selected ADC channel */
+ LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel,
+ pConfigInjected->InjectedSamplingTime);
+
+ /* Configure the offset: offset enable/disable, channel, offset value */
+
+ /* Shift the offset with respect to the selected ADC resolution. */
+ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
+ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, pConfigInjected->InjectedOffset);
+
+ if (pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
+ {
+ /* Set ADC selected offset number */
+ LL_ADC_SetOffsetChannel(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedChannel);
+ LL_ADC_SetOffsetLevel(hadc->Instance, pConfigInjected->InjectedOffsetNumber, tmpOffsetShifted);
+
+ assert_param(IS_ADC_OFFSET_SIGN(pConfigInjected->InjectedOffsetSign));
+ assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedOffsetSignedSaturation));
+ assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedOffsetSaturation));
+ /* Signed and unsigned saturation cannot be set at the same time */
+ assert_param(!((pConfigInjected->InjectedOffsetSignedSaturation == ENABLE)
+ && (pConfigInjected->InjectedOffsetSaturation == ENABLE)));
+
+ /* Set ADC selected offset sign */
+ LL_ADC_SetOffsetSign(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedOffsetSign);
+ /* Set ADC selected offset signed saturation */
+ LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber,
+ (pConfigInjected->InjectedOffsetSignedSaturation == ENABLE)
+ ? LL_ADC_OFFSET_SIGNED_SAT_ENABLE \
+ : LL_ADC_OFFSET_SIGNED_SAT_DISABLE);
+ /* Set ADC offset unsigned saturation */
+ LL_ADC_SetOffsetUnsignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber, \
+ (pConfigInjected->InjectedOffsetSaturation == ENABLE) \
+ ? LL_ADC_OFFSET_UNSIGNED_SAT_ENABLE \
+ : LL_ADC_OFFSET_UNSIGNED_SAT_DISABLE);
+ }
+ else
+ {
+ /* Scan each offset register to check if the selected channel is targeted. */
+ /* If this is the case, the corresponding offset number is disabled. */
+ /* Scan each offset register to check if the selected channel is targeted.
+ If this is the case, the corresponding offset number is disabled. */
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
+ == __HAL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_1, 0UL);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
+ == __HAL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_2, 0UL);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
+ == __HAL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_3, 0UL);
+ }
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
+ == __HAL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_4, 0UL);
+ }
+ }
+
+ }
+
+ /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
+ /* internal measurement paths enable: If internal channel selected, */
+ /* enable dedicated internal buffers and path. */
+ /* Note: these internal measurement paths can be disabled using */
+ /* HAL_ADC_DeInit(). */
+
+ if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfigInjected->InjectedChannel))
+ {
+ tmp_config_common_path_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+ tmp_config_path_internal_channel = LL_ADC_GetPathInternalCh(hadc->Instance);
+
+ /* If the requested internal measurement path has already been enabled, */
+ /* bypass the configuration processing. */
+ if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
+ && ((tmp_config_common_path_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+ {
+ if (ADC_VREFINT_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_common_path_internal_channel);
+ }
+ }
+ else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
+ && ((tmp_config_common_path_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+ {
+ if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_common_path_internal_channel);
+
+ /* Delay for temperature sensor stabilization time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+ }
+ else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
+ && ((tmp_config_common_path_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
+ {
+ if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ LL_ADC_PATH_INTERNAL_VBAT | tmp_config_common_path_internal_channel);
+ }
+ }
+ else if (((pConfigInjected->InjectedChannel == ADC_CHANNEL_VDDCORE)
+ && ((tmp_config_path_internal_channel & LL_ADC_PATH_INTERNAL_VDDCORE) == 0UL)))
+ {
+ if (ADC_VDDCORE_INSTANCE(hadc))
+ {
+ LL_ADC_SetPathInternalCh(hadc->Instance, LL_ADC_PATH_INTERNAL_VDDCORE | tmp_config_path_internal_channel);
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Enable ADC multimode and configure multimode parameters
+ * @note Possibility to update parameters on the fly:
+ * This function initializes multimode parameters, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_MultiModeTypeDef" on the fly, without resetting
+ * the ADCs.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_MultiModeTypeDef".
+ * @note To move back configuration from multimode to single mode, ADC must
+ * be reset (using function HAL_ADC_Init() ).
+ * @param hadc Master ADC handle
+ * @param pMultimode Structure of ADC multimode configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc,
+ const ADC_MultiModeTypeDef *pMultimode)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_Common_TypeDef *tmpADC_Common;
+ ADC_HandleTypeDef tmphadcSlave;
+ uint32_t tmphadcSlave_conversion_on_going;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_MULTIMODE(pMultimode->Mode));
+ if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
+ {
+ assert_param(IS_ADC_DUAL_DATA_MODE(pMultimode->DualModeData));
+ assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+ ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
+ ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+ if (tmphadcSlave.Instance == NULL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Multimode DMA configuration */
+ /* - Multimode DMA mode */
+ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ && (tmphadcSlave_conversion_on_going == 0UL))
+ {
+ /* Pointer to the common control register */
+ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+ /* If multimode is selected, configure all multimode parameters. */
+ /* Otherwise, reset multimode parameters (can be used in case of */
+ /* transition from multimode to independent mode). */
+ if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
+ {
+ MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, pMultimode->DualModeData);
+
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Multimode mode selection */
+ /* - Multimode delay */
+ /* Note: Delay range depends on selected resolution: */
+ /* from 1 to 12 clock cycles for 12 bits */
+ /* from 1 to 10 clock cycles for 10 bits, */
+ /* from 1 to 8 clock cycles for 8 bits */
+ /* from 1 to 6 clock cycles for 6 bits */
+ /* If a higher delay is selected, it will be clipped to maximum delay */
+ /* range */
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ {
+ MODIFY_REG(tmpADC_Common->CCR,
+ ADC_CCR_DUAL |
+ ADC_CCR_DELAY,
+ pMultimode->Mode |
+ pMultimode->TwoSamplingDelay
+ );
+ }
+ }
+ else /* ADC_MODE_INDEPENDENT */
+ {
+ CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF);
+
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Multimode mode selection */
+ /* - Multimode delay */
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ {
+ CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
+ }
+ }
+ }
+ /* If one of the ADC sharing the same common group is enabled, no update */
+ /* could be done on neither of the multimode structure parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(hadc);
+
+ return tmp_hal_status;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Enable Injected Queue
+ * @note This function resets CFGR1 register JQDIS bit in order to enable the
+ * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
+ * are both equal to 0 to ensure that no regular nor injected
+ * conversion is ongoing.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+ /* Parameter can be set only if no conversion is on-going */
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ )
+ {
+ CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JQDIS);
+
+ /* Update state, clear previous result related to injected queue overflow */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+ tmp_hal_status = HAL_OK;
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Disable Injected Queue
+ * @note This function sets CFGR1 register JQDIS bit in order to disable the
+ * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
+ * are both equal to 0 to ensure that no regular nor injected
+ * conversion is ongoing.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+ /* Parameter can be set only if no conversion is on-going */
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ )
+ {
+ LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE);
+ tmp_hal_status = HAL_OK;
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Disable ADC voltage regulator.
+ * @note Disabling voltage regulator allows to save power. This operation can
+ * be carried out only when ADC is disabled.
+ * @note To enable again the voltage regulator, the user is expected to
+ * resort to HAL_ADC_Init() API.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ LL_ADC_DisableInternalRegulator(hadc->Instance);
+ tmp_hal_status = HAL_OK;
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Enter ADC deep-power-down mode
+ * @note This mode is achieved in setting DEEPPWD bit and allows to save power
+ * in reducing leakage currents. It is particularly interesting before
+ * entering stop modes.
+ * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the
+ * ADC voltage regulator. This means that this API encompasses
+ * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
+ * calibration is lost.
+ * @note To exit the ADC deep-power-down mode, the user is expected to
+ * resort to HAL_ADC_Init() API as well as to relaunch a calibration
+ * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
+ * saved calibration factor.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ LL_ADC_EnableDeepPowerDown(hadc->Instance);
+ tmp_hal_status = HAL_OK;
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_ccb.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_ccb.c
new file mode 100644
index 0000000000..3e5e830547
--- /dev/null
+++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_ccb.c
@@ -0,0 +1,5324 @@
+/**
+ ******************************************************************************
+ * @file stm32u3xx_hal_ccb.c
+ * @author MCD Application Team
+ * @brief CCB HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Inter Integrated Circuit (CCB) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The CCB HAL driver can be used as follows:
+
+ (#) Declare a CCB_HandleTypeDef handle structure, for example: CCB_HandleTypeDef hccb;
+
+ (#) Initialize the CCB low level resources by implementing the HAL_CCB_MspInit() API:
+ (##) Enable the CCB interface clock
+
+ (#) Initialize the CCB registers by calling the HAL_CCB_Init() API which trig
+ HAL_CCB_MspInit().
+
+ (#) Fill entirely the structures corresponding to your operation:
+ For instance: CCB_ECDSACurveParamTypeDef and CCB_ECDSAKeyBlobTypeDef
+ for HAL_CCB_ECDSA_WrapPrivateKey().
+
+ (#) Execute the operation and check the returned value.
+
+ (#) Call the function HAL_CCB_DeInit() to restore the default configuration which trig
+ HAL_CCB_MspDeInit().
+
+ *** High level operation ***
+ =================================
+ [..]
+ (+) Input structure requires buffers as uint8_t array.
+
+ (+) Output structure requires buffers as uint8_t array.
+
+ (+) Proteted ECDSA Sign
+ (++) HAL_CCB_ECDSA_WrapPrivateKey() for protected ECDSA blob creation when using user key.
+ (++) HAL_CCB_ECDSA_GenerateWrapPrivateKey() for protected ECDSA blob creation when using internal key.
+ (++) HAL_CCB_ECDSA_Sign() for protected ECDSA Signing message usage.
+ (++) HAL_CCB_ECDSA_ComputePublicKey() for protected ECDSA computing public key usage.
+
+ (+) Proteted ECC Scalar Multiplication
+ (++) HAL_CCB_ECC_WrapPrivateKey() for protected ECC blob creation when using user key.
+ (++) HAL_CCB_ECC_GenerateWrapPrivateKey() for protected ECC blob creation when using internal key.
+ (++) HAL_CCB_ECC_ComputeScalarMul() for protected ECC scalar multiplication usage.
+
+ (+) Proteted RSA Modular Exponentiation
+ (++) HAL_CCB_RSA_WrapPrivateKey() for protected RSA blob creation when using user key.
+ (++) HAL_CCB_RSA_ComputeModularExp() for protected RSA computing modular exponetiation usage.
+
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32u3xx_hal.h"
+
+/** @addtogroup STM32U3xx_HAL_Driver
+ * @{
+ */
+#if defined(CCB) && defined(HAL_CCB_MODULE_ENABLED)
+
+/** @defgroup CCB CCB
+ * @brief CCB HAL module driver
+ * @{
+ */
+
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup CCB_Private_Defines
+ * @{
+ */
+
+/** @defgroup CCB_TIMEOUT_DEFAULT_VALUE CCB timout Default Value
+ * @{
+ */
+#ifndef HAL_CCB_TIMEOUT_DEFAULT_VALUE
+#define HAL_CCB_TIMEOUT_DEFAULT_VALUE 0xFFFFU /* CCB Timeout.*/
+#endif /*HAL_CCB_TIMEOUT_DEFAULT_VALUE */
+
+/**
+ * @}
+ */
+
+/** @defgroup CCB_Operations CCB Operations
+ * @{
+ */
+#define CCB_ECDSA_SIGN_CPU_BLOB_CREATION (0x000000C0U) /*!< ECDSA signature blob creation with priv key from the CPU */
+#define CCB_ECDSA_SIGN_RNG_BLOB_CREATION (0x000000C2U) /*!< ECDSA signature blob creation with priv key from the RNG */
+#define CCB_ECDSA_SIGN_BLOB_USE (0x000000C3U) /*!< ECDSA signature blob use for ECDSA signature */
+#define CCB_ECC_SCALAR_MUL_CPU_BLOB_CREATION (0x00000080U) /*!< ECC scalar multiplication blob creation with priv key from the CPU- */
+#define CCB_ECC_SCALAR_MUL_RNG_BLOB_CREATION (0x00000082U) /*!< ECC scalar multiplication blob creation with priv key from the RNG */
+#define CCB_ECC_SCALAR_MUL_BLOB_USE (0x00000081U) /*!< ECC Scalar multiplication blob use, or ECDSA signature blob use for public key computation */
+#define CCB_MODULAR_EXP_CPU_BLOB_CREATION (0x00000044U) /*!< Modular exponentiation blob creation with priv key from the CPU */
+#define CCB_MODULAR_EXP_BLOB_USE (0x00000045U) /*!< Modular exponentiation blob use */
+#define CCB_PKA_ECDSA_VERIF_OK (0x0000D60DU) /*!< PKA ECDSA Signature verification success */
+
+/**
+ * @}
+ */
+
+/** @defgroup CCB_PKA_Mode CCB PKA mode
+ * @{
+ */
+#define CCB_PKA_MODE_MODULAR_EXP_PROTECT (0x00000003U) /*!< PKA Modular exponentiation */
+#define CCB_PKA_ECC_MUL_MODE (0x00000020U) /*!< PKA ECC scalar multiplication */
+#define CCB_PKA_ECDSA_SIGNATURE_MODE (0x00000024U) /*!< PKA ECDSA signature */
+#define CCB_PKA_MODE_ECDSA_VERIFICATION (0x00000026U) /*!< PKA ECDSA verification */
+#define CCB_PKA_ERROR_OPERATION_NONE (0x0000D60DU) /*!< No PKA Hardware operation error */
+#define CCB_PKA_RAM_SIZE (0x00000536U) /*!< CCB PKA Ram Size */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CCB_Private_Constants CCB Private Constants
+ * @{
+ */
+#define CCB_FAKE_VALUE 0X0001UL /*!< Fake value used for SAES_IVRs */
+#define CCB_MAGIC_VALUE 0X0CCBUL /*!< Magic number used when chaining key from SAES to PKA RAM */
+#define CCB_IV0_VALUE 0X0002UL /*!< SAES_IVR0 that must be equal to 0x2 */
+#define CCB_BLOCK_SIZE 0X0004UL /*!< Block size is 128 Bits (4*32 bits) */
+#define CCB_SIZE_SKEY_INWORD 0X0008UL /*!< Symmetric key size is always 256 (8*32 bits) */
+#define CCB_COMPUTE_PUBLIC_KEY 0x02U /*!< CCB compute public key */
+#define CCB_VERIF_OPERATION_ENABLED 0x01U /*!< CCB verification enabled */
+#define CCB_VERIF_OPERATION_DISABLED 0U /*!< CCB verification disabled */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @addtogroup CCB_Private_Macros
+ * @{
+ */
+#define RAM_PARAM_END(TAB,INDEX) do{ \
+ TAB[INDEX] = 0UL; \
+ TAB[INDEX + 1U] = 0UL; \
+ } while(0)
+
+#define HAL_CCB_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR)\
+ & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+#define HAL_CCB_GET_SAES_FLAG(__FLAG__) (((__FLAG__)>1U) ? \
+ (((SAES->SR & (__FLAG__)) == (__FLAG__)) ? SET : RESET) :\
+ (((SAES->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET) )
+
+#define HAL_CCB_GET_PKA_FLAG(__FLAG__) ((((PKA->SR)\
+ & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+#define HAL_CCB_CLEAR_PKA_FLAG(__FLAG__) WRITE_REG(PKA->CLRFR, (__FLAG__))
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Polling Private function */
+static HAL_StatusTypeDef CCB_WaitOperStep(CCB_HandleTypeDef *hccb, uint32_t step, uint32_t Timeout);
+static HAL_StatusTypeDef CCB_WaitFLAG(CCB_HandleTypeDef *hccb, uint32_t flag, uint32_t Timeout);
+static HAL_StatusTypeDef Protect_PKA_WaitFLAG(CCB_HandleTypeDef *hccb, uint32_t flag, uint32_t Timeout);
+static HAL_StatusTypeDef Unprotect_PKA_WaitFLAG(uint32_t flag, uint32_t Timeout);
+static HAL_StatusTypeDef CCB_RNG_Wait_SET_FLAG(uint32_t flag, uint32_t Timeout);
+static HAL_StatusTypeDef Protect_SAES_WaitFLAG(CCB_HandleTypeDef *hccb, uint32_t flag, FlagStatus Status,
+ uint32_t Timeout);
+
+/* Set parameters Private function */
+static HAL_StatusTypeDef CCB_ECDSASign_SetPram(CCB_HandleTypeDef *hccb, CCB_ECDSACurveParamTypeDef *in);
+static HAL_StatusTypeDef CCB_ECCMul_SetPram(CCB_HandleTypeDef *hccb, CCB_ECCMulCurveParamTypeDef *in);
+static HAL_StatusTypeDef CCB_RSAModExp_SetPram(CCB_HandleTypeDef *hccb, CCB_RSAParamTypeDef *in);
+static HAL_StatusTypeDef CCB_SetPram(CCB_HandleTypeDef *hccb, uint32_t modulusSizeByte, uint32_t dst_address,
+ const uint8_t *src);
+
+/* Initialization Private function */
+static HAL_StatusTypeDef Protect_PKA_Init(CCB_HandleTypeDef *hccb, uint32_t Operation);
+static HAL_StatusTypeDef Unprotected_PKA_Init(void);
+static HAL_StatusTypeDef CCB_RNG_Init(void);
+
+/* Wrapping Private function */
+static HAL_StatusTypeDef WrappingKeyConfiguration(CCB_HandleTypeDef *hccb, uint32_t Operation,
+ CCB_WrappingKeyTypeDef *pWrappingKey);
+static HAL_StatusTypeDef Protect_SAES_UnwrapKey(CCB_HandleTypeDef *hccb, const CCB_WrappingKeyTypeDef *pWrappingKey,
+ uint32_t Timeout);
+
+/* Data managementPrivate function */
+static uint32_t GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb);
+static void CCB_Memcpy_u8_to_u32(__IO uint32_t dst[], const uint8_t src[], size_t size);
+static void CCB_Memcpy_u32_to_u8(uint8_t dst[], __IO const uint32_t src[], size_t n);
+static void CCB_Memcpy_u32_to_u32(__IO uint32_t dst[], __IO const uint32_t src[], size_t n);
+static void CCB_Memcpy_u8_to_u64(__IO uint32_t dst[], const uint8_t src[]);
+static void CCB_Memcpy_Not_Align(__IO uint32_t dst[], const uint8_t src[], size_t size);
+static uint32_t CCB_get_cipherkey_size(CCB_ECDSACurveParamTypeDef *pCurveParam);
+
+/* Blob processing Private function */
+static HAL_StatusTypeDef CCB_WrapSymmetricKey(CCB_HandleTypeDef *hccb, const uint32_t *pClearAESKey, uint32_t operation,
+ CCB_WrappingKeyTypeDef *pWrappingKey);
+static HAL_StatusTypeDef CCB_BlobCreation_InitialPhase(CCB_HandleTypeDef *hccb, uint32_t *IV);
+static HAL_StatusTypeDef CCB_BlobUse_InitialPhase(CCB_HandleTypeDef *hccb, const uint32_t *pIV, uint32_t *pTag);
+static HAL_StatusTypeDef CCB_BlobCreation_FinalPhase(CCB_HandleTypeDef *hccb, uint32_t Operation, uint32_t *pTag,
+ uint32_t sizeparam);
+static HAL_StatusTypeDef CCB_BlobUse_FinalPhase(CCB_HandleTypeDef *hccb, uint32_t Operation, uint32_t sizeparam);
+static HAL_StatusTypeDef CCB_ECDSA_SignBlobCreation(CCB_HandleTypeDef *hccb, CCB_ECDSACurveParamTypeDef *pCurveParam,
+ const uint8_t *pClearPrivateKey,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ uint32_t *pIV, uint32_t *pTag, uint32_t *pWarappedKey,
+ uint8_t CCB_Operation);
+static HAL_StatusTypeDef CCB_ECC_ScalarMulBlobCreation(CCB_HandleTypeDef *hccb,
+ CCB_ECCMulCurveParamTypeDef *pCurveParam,
+ const uint8_t *pClearPrivateKey,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ uint32_t *pIV, uint32_t *pTag, uint32_t *pWarappedKey,
+ uint8_t CCB_Operation);
+static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_ECCMulCurveParamTypeDef *pCurveParam,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ uint32_t *pIV, uint32_t *pTag, uint32_t *pWarappedKey,
+ CCB_ECCMulPointTypeDef *pInputPoint,
+ CCB_ECCMulPointTypeDef *pOutputPoint,
+ const uint32_t *pPublicKey,
+ uint8_t VerifOperation);
+static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RSAParamTypeDef *pParam,
+ const CCB_RSAClearKeyTypeDef *pRSAClearPrivateKey,
+ CCB_WrappingKeyTypeDef *pWrappingKey, uint32_t *pIV,
+ uint32_t *pTag, uint32_t *pWrappedExp, uint32_t *pWrappedPhi);
+static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_RSAParamTypeDef *pParam,
+ CCB_WrappingKeyTypeDef *pWrappingKey, uint32_t *pIV,
+ uint32_t *pTag, uint32_t *pWrappedExp, uint32_t *pWrappedPhi,
+ const uint8_t *pOperand, uint8_t *pModularExp,
+ const uint32_t *pReferenceModularExp, uint8_t VerifOperation);
+static HAL_StatusTypeDef PKA_ECDSASign(CCB_ECDSACurveParamTypeDef *pCurveParam,
+ const uint8_t *pClearPrivateKey, uint8_t *pInteger, uint8_t *pHash,
+ CCB_ECDSASignTypeDef *pSignature);
+
+static HAL_StatusTypeDef PKA_ECC_ComputeScalarMul(CCB_ECCMulCurveParamTypeDef *pCurveParam,
+ const uint8_t *pClearPrivateKey, uint32_t PublicKey[2][20]);
+static HAL_StatusTypeDef PKA_RSA_ComputeModularExp(CCB_RSAParamTypeDef *pParam,
+ const CCB_RSAClearKeyTypeDef *pRSAClearPrivateKey,
+ uint8_t *pOp1, uint32_t *pReferenceModularExp);
+static HAL_StatusTypeDef PKA_ECDSAVerif(CCB_ECDSACurveParamTypeDef *pCurveParam,
+ CCB_ECCMulPointTypeDef *pPublicKeyOut, const uint8_t *pHash,
+ CCB_ECDSASignTypeDef *pSignature);
+static uint32_t PKA_ECDSAVerif_Result(void);
+static HAL_StatusTypeDef PKA_RAM_Erase(void);
+static void CCB_PKA_RAMReset(void);
+/** @defgroup CCB_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ deinitialize the CCB peripheral:
+
+ (+) User must implement HAL_CCB_MspInit() function in which he configures
+ all related peripherals resources.
+
+ (+) Call the function HAL_CCB_Init() to configure the device.
+
+ (+) Call the function HAL_CCB_DeInit() to restore the default configuration
+ of the selected CCB peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the CCB associated handle
+ * according to the specified parameters.
+ * @param hccb CCB handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CCB_Init(CCB_HandleTypeDef *hccb)
+{
+ /* Check the CCB handle allocation */
+ if (hccb == NULL)
+ {
+ /* Return error */
+ return HAL_ERROR;
+ }
+
+ /* Initialization of the hardware */
+ HAL_CCB_MspInit(hccb);
+
+ /* PKA RAM RESET*/
+ CCB_PKA_RAMReset();
+
+ /* Update the CCB state */
+ hccb->State = HAL_CCB_STATE_READY;
+
+ /* Return HAL OK */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the CCB MSP.
+ * @param hccb CCB handle
+ * @retval None
+ */
+__weak void HAL_CCB_MspInit(CCB_HandleTypeDef *hccb)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hccb);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CCB_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the CCB peripheral.
+ * @param hccb CCB handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CCB_DeInit(CCB_HandleTypeDef *hccb)
+{
+ /* Check the CCB handle allocation */
+ if (hccb == NULL)
+ {
+ /* Return error */
+ return HAL_ERROR;
+ }
+
+ /* Set CCB IPRST */
+ SET_BIT(hccb->Instance->CR, CCB_CR_IPRST);
+
+ /* CCB is busy while CCB IPRST is in progress --> waiting flag */
+ if (CCB_WaitFLAG(hccb, CCB_SR_BUSY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* clear CCB IPRST */
+ CLEAR_BIT(hccb->Instance->CR, CCB_CR_IPRST);
+
+ /* De-initialize the hardware */
+ HAL_CCB_MspDeInit(hccb);
+
+ /* Reset the driver state */
+ hccb->State = HAL_CCB_STATE_RESET;
+
+ /* Return HAL OK */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the CCB MSP.
+ * @param hccb CCB handle
+ * @retval None
+ */
+__weak void HAL_CCB_MspDeInit(CCB_HandleTypeDef *hccb)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hccb);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CCB_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CCB_Exported_Functions_Group2 Peripheral State and Errorfunctions
+ * @brief set symmetric key functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Error functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the CCB error code.
+ * @param hccb : pointer to a CCB_HandleTypeDef structure
+ * @retval CCB error code
+ */
+uint32_t HAL_CCB_GetError(const CCB_HandleTypeDef *hccb)
+{
+ return hccb->ErrorCode;
+}
+
+/**
+ * @brief Returns the CCB state.
+ * @param hccb: pointer to a CCB_HandleTypeDef structure
+ * @retval State code
+ */
+uint32_t HAL_CCB_GetState(const CCB_HandleTypeDef *hccb)
+{
+ return hccb->State;
+}
+
+/**
+ * @brief Return the CCB hardware operartion error code.
+ * @param hccb : pointer to a CCB_HandleTypeDef structure
+ * @retval CCB hardware operartion error code
+ */
+uint32_t HAL_CCB_GetOperationError(const CCB_HandleTypeDef *hccb)
+{
+ return ((hccb->Instance->SR & 0x1F00U) >> 8U);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CCB_Exported_Functions_Group3 operation functions
+ * @brief set symmetric key functions
+ *
+@verbatim
+ ===============================================================================
+ ##### operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the CCB operations.
+
+ (#) There are three type of CCB/PKA protected operations:
+ (++) ECDSA sign : The operation is performed in the polling mode.
+ These functions return when data operation is completed.
+ (++) ECC Scalar Multiplication : The operation is performed using Interrupts.
+ These functions return immediately.
+ The end of the operation is indicated by HAL_PKA_ErrorCallback in case of error.
+ The end of the operation is indicated by HAL_PKA_OperationCpltCallback in case of success.
+ To stop any operation in interrupt mode, use HAL_PKA_Abort().
+ (++) RSA Modular Exponentiation : The operation is performed using Interrupts.
+ These functions return immediately.
+ The end of the operation is indicated by HAL_PKA_ErrorCallback in case of error.
+ The end of the operation is indicated by HAL_PKA_OperationCpltCallback in case of success.
+ To stop any operation in interrupt mode, use HAL_PKA_Abort().
+
+ (#) ECDSA sign functions are :
+ (++) HAL_CCB_ECDSA_WrapPrivateKey()for blob creation.
+ (++) HAL_CCB_ECDSA_GenerateWrapPrivateKey()for blob creation.
+ (++) HAL_CCB_ECDSA_Sign() for blob usage.
+ (++) HAL_CCB_ECDSA_ComputePublicKey() for blob usage.
+
+ (#) ECC Scalar Multiplication functions are :
+ (++) HAL_CCB_ECC_WrapPrivateKey()for blob creation.
+ (++) HAL_CCB_ECC_GenerateWrapPrivateKey()for blob creation.
+ (++) HAL_CCB_ECC_ComputeScalarMul() for blob usage.
+
+ (#) RSA Modular Exponentiation functions are :
+ (++) HAL_CCB_RSA_WrapPrivateKey()for blob creation.
+ (++) HAL_CCB_RSA_ComputeModularExp() for blob usage.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief ECDSA Wrap Symmetric Key.
+ * @param hccb CCB handle.
+ * @param pClearAESKey pointer to the clear AES Key.
+ * @param pWrappingKey pointer to the Wrapping Key structure.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CCB_ECDSA_WrapSymmetricKey(CCB_HandleTypeDef *hccb, const uint32_t *pClearAESKey,
+ CCB_WrappingKeyTypeDef *pWrappingKey)
+{
+ return (CCB_WrapSymmetricKey(hccb, pClearAESKey, CCB_ECDSA_SIGN_CPU_BLOB_CREATION, pWrappingKey));
+}
+
+/**
+ * @brief ECC Wrap Symmetric Key.
+ * @param hccb CCB handle.
+ * @param pClearAESKey pointer to the clear AES Key.
+ * @param pWrappingKey pointer to the Wrapping Key structure.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CCB_ECC_WrapSymmetricKey(CCB_HandleTypeDef *hccb, const uint32_t *pClearAESKey,
+ CCB_WrappingKeyTypeDef *pWrappingKey)
+{
+ return (CCB_WrapSymmetricKey(hccb, pClearAESKey, CCB_ECC_SCALAR_MUL_CPU_BLOB_CREATION, pWrappingKey));
+}
+
+/**
+ * @brief RSA Wrap Symmetric Key.
+ * @param hccb CCB handle.
+ * @param pClearAESKey pointer to the clear AES Key.
+ * @param pWrappingKey pointer to the Wrapping Key structure.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CCB_RSA_WrapSymmetricKey(CCB_HandleTypeDef *hccb, const uint32_t *pClearAESKey,
+ CCB_WrappingKeyTypeDef *pWrappingKey)
+{
+ return (CCB_WrapSymmetricKey(hccb, pClearAESKey, CCB_MODULAR_EXP_CPU_BLOB_CREATION, pWrappingKey));
+}
+
+/**
+ * @brief Blob Creation: ECDSA Wrap the private Key (input from user).
+ * @param hccb CCB handle.
+ * @param pCurveParam pointer to the Curve parameters.
+ * @param pClearPrivateKey pointer to the clear private key.
+ * @param pWrappingKey pointer to the Wrapping Key structure.
+ * @param pWrappedPrivateKeyBlob pointer to the related wrapped Private Key Blob.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CCB_ECDSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECDSACurveParamTypeDef *pCurveParam,
+ const uint8_t *pClearPrivateKey, CCB_WrappingKeyTypeDef *pWrappingKey,
+ const CCB_ECDSAKeyBlobTypeDef *pWrappedPrivateKeyBlob)
+{
+ uint32_t count;
+ __IO uint16_t f_count;
+ uint16_t random0 = 0;
+ uint16_t random1 = 0;
+ uint16_t random2 = 0;
+ uint16_t random3 = 0;
+ uint32_t key_size;
+ uint32_t tickstart;
+
+ uint8_t hash[80U] = {0};
+ uint8_t r_sign[80U] = {0};
+ uint8_t s_sign[80U] = {0};
+ uint8_t point_x[80U] = {0};
+ uint8_t point_y[80U] = {0};
+ uint8_t integer[80U] = {0};
+ uint32_t iv_temp[4] = {0};
+ uint32_t tag_temp[4] = {0};
+ uint32_t wrapped_key_temp[80U] = {0};
+
+ CCB_ECDSASignTypeDef signature = {r_sign, s_sign};
+ CCB_ECCMulPointTypeDef publicKeyOut = {(uint8_t *)point_x, (uint8_t *)point_y};
+
+ if (CCB_RNG_Init() != HAL_OK)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ for (count = 0U; count < (pCurveParam->primeOrderSizeByte); count++)
+ {
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ tickstart = HAL_GetTick();
+
+ while (hash[count] == 0U)
+ {
+ hash[count] = (uint8_t)((RNG->DR) & 0x000000FFU);
+ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE)
+ {
+ /* Set state and return error */
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ tickstart = HAL_GetTick();
+
+ while (random0 == 0U)
+ {
+ random0 = (uint16_t)(RNG->DR & 0x3FFU);
+ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE)
+ {
+ /* Set state and return error */
+ return HAL_ERROR;
+ }
+ }
+
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ tickstart = HAL_GetTick();
+
+ while (random1 == 0U)
+ {
+ random1 = (uint16_t)(RNG->DR & 0x3FFU);
+ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE)
+ {
+ /* Set state and return error */
+ return HAL_ERROR;
+ }
+ }
+
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ tickstart = HAL_GetTick();
+
+ while (random2 == 0U)
+ {
+ random2 = (uint16_t)(RNG->DR & 0x3FFU);
+ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE)
+ {
+ /* Set state and return error */
+ return HAL_ERROR;
+ }
+ }
+
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ tickstart = HAL_GetTick();
+
+ while (random3 == 0U)
+ {
+ random3 = (uint16_t)(RNG->DR & 0x3FFU);
+ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE)
+ {
+ /* Set state and return error */
+ return HAL_ERROR;
+ }
+ }
+
+ for (count = 0U; count < (pCurveParam->primeOrderSizeByte); count++)
+ {
+ tickstart = HAL_GetTick();
+
+ while (integer[count] == 0U)
+ {
+ integer[count] = (uint8_t)((RNG->DR) & 0x000000FFU);
+ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE)
+ {
+ /* Set state and return error */
+ return HAL_ERROR;
+ }
+ }
+
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ if (hccb->State == HAL_CCB_STATE_READY)
+ {
+
+ if (Unprotected_PKA_Init() != HAL_OK)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ if (PKA_ECDSASign(pCurveParam, pClearPrivateKey, (uint8_t *)integer, (uint8_t *)hash,
+ &signature) != HAL_OK)
+ {
+ if (PKA_RAM_Erase() != HAL_OK)
+ {
+ hccb->ErrorCode |= HAL_CCB_ERROR_PKARAM_ERASE;
+ }
+ return HAL_ERROR;
+ }
+
+ f_count = 0;
+ while (f_count < random0)
+ {
+ f_count++;
+ }
+
+ /* Signature blob creation */
+ if (CCB_ECDSA_SignBlobCreation(hccb, pCurveParam, pClearPrivateKey, pWrappingKey, iv_temp, tag_temp,
+ wrapped_key_temp, CCB_ECDSA_SIGN_CPU_BLOB_CREATION) != HAL_OK)
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+
+ /* Reset each element in the PKA RAM */
+ for (uint32_t index = 0U; index < CCB_PKA_RAM_SIZE; index++)
+ {
+ /* Clear the content */
+ PKA->RAM[index] = 0UL;
+ }
+
+ /* Create ECDSA public key */
+ if (CCB_ECC_ComputeScalarMul(hccb, pCurveParam, pWrappingKey, iv_temp, tag_temp,
+ wrapped_key_temp, NULL, &publicKeyOut, NULL,
+ CCB_COMPUTE_PUBLIC_KEY) != HAL_OK)
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+
+ if (Unprotected_PKA_Init() != HAL_OK)
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+
+ /* PKA ECDSA valid R & S signature */
+ if (PKA_ECDSAVerif(pCurveParam, &publicKeyOut, hash, &signature) != HAL_OK)
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+
+ f_count = 0;
+ while (f_count < random1)
+ {
+ f_count++;
+ }
+
+ /* Check if it is valid signature and improve robustness against intrusion (intentional) */
+ if ((PKA_ECDSAVerif_Result() != CCB_PKA_ECDSA_VERIF_OK) || (f_count != random1) || (f_count == 0U))
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+
+ f_count = 0;
+ while (f_count < random2)
+ {
+ f_count++;
+ }
+
+ /* Check if it is valid signature and improve robustness against intrusion (intentional) */
+ if ((PKA_ECDSAVerif_Result() != CCB_PKA_ECDSA_VERIF_OK) || (f_count != random2) || (f_count == 0U))
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+
+ f_count = 0;
+ while (f_count < random3)
+ {
+ f_count++;
+ }
+
+ /* Check if it is valid signature and improve robustness against intrusion (intentional) */
+ if ((PKA_ECDSAVerif_Result() != CCB_PKA_ECDSA_VERIF_OK) || (f_count != random3) || (f_count == 0U))
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+ }
+
+ else
+ {
+ /* Set state, error code and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ hccb->ErrorCode = HAL_CCB_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Update the CCB state */
+ hccb->State = HAL_CCB_STATE_READY;
+
+ /* Export created Blob */
+ key_size = CCB_get_cipherkey_size(pCurveParam);
+ for (count = 0U; count < key_size; count++)
+ {
+ if (count < CCB_BLOCK_SIZE)
+ {
+ pWrappedPrivateKeyBlob->pIV[count] = iv_temp[count];
+ pWrappedPrivateKeyBlob->pTag[count] = tag_temp[count];
+ }
+ pWrappedPrivateKeyBlob->pWrappedKey[count] = wrapped_key_temp[count];
+ }
+
+ /* Return HAL OK */
+ return HAL_OK;
+}
+
+/**
+ * @brief Blob Creation: ECDSA generate (by RNG) and wrap the private Key (no user input).
+ * @param hccb CCB handle.
+ * @param pCurveParam pointer to the Curve parameters.
+ * @param pWrappingKey pointer to the Wrapping Key structure.
+ * @param pWrappedPrivateKeyBlob pointer to the related wrapped Private Key Blob.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CCB_ECDSA_GenerateWrapPrivateKey(CCB_HandleTypeDef *hccb,
+ CCB_ECDSACurveParamTypeDef *pCurveParam,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ CCB_ECDSAKeyBlobTypeDef *pWrappedPrivateKeyBlob)
+{
+ uint32_t count;
+ uint32_t key_size;
+ uint32_t iv_temp[4] = {0};
+ uint32_t tag_temp[4] = {0};
+ uint32_t wrapped_key_temp[80U] = {0};
+
+ if (hccb->State == HAL_CCB_STATE_READY)
+ {
+
+ /* Signature blob creation */
+ if (CCB_ECDSA_SignBlobCreation(hccb, pCurveParam, NULL, pWrappingKey, iv_temp, tag_temp, wrapped_key_temp,
+ CCB_ECDSA_SIGN_RNG_BLOB_CREATION) != HAL_OK)
+ {
+ /* Set state, error code and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Set state, error code and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ hccb->ErrorCode = HAL_CCB_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Update the CCB state */
+ hccb->State = HAL_CCB_STATE_READY;
+
+ /* Export created Blob */
+ key_size = CCB_get_cipherkey_size(pCurveParam);
+ for (count = 0U; count < key_size; count++)
+ {
+ if (count < CCB_BLOCK_SIZE)
+ {
+ pWrappedPrivateKeyBlob->pIV[count] = iv_temp[count];
+ pWrappedPrivateKeyBlob->pTag[count] = tag_temp[count];
+ }
+ pWrappedPrivateKeyBlob->pWrappedKey[count] = wrapped_key_temp[count];
+ }
+
+ /* Return HAL OK */
+ return HAL_OK;
+}
+
+/**
+ * @brief Blob Usage: ECDSA Signature.
+ * @param hccb CCB handle.
+ * @param pCurveParam pointer to the Curve parameters.
+ * @param pWrappingKey pointer to the Wrapping Key structure.
+ * @param pWrappedPrivateKeyBlob pointer to the related wrapped Private Key Blob.
+ * @param pHash pointer to the Hash.
+ * @param pSignature pointer to the signature.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CCB_ECDSA_Sign(CCB_HandleTypeDef *hccb, CCB_ECDSACurveParamTypeDef *pCurveParam,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ CCB_ECDSAKeyBlobTypeDef *pWrappedPrivateKeyBlob, const uint8_t *pHash,
+ CCB_ECDSASignTypeDef *pSignature)
+
+{
+ uint32_t count;
+ uint32_t count_block = 0;
+ uint32_t offset;
+ uint32_t operand_size;
+ uint32_t cipherkey_size;
+
+ if (hccb->State == HAL_CCB_STATE_READY)
+ {
+ /* Set Operation in CCB */
+ MODIFY_REG(CCB->CR, CCB_CR_CCOP, CCB_ECDSA_SIGN_BLOB_USE);
+
+ /* Wait until OPSTEP is set to 0x01 */
+ if (CCB_WaitOperStep(hccb, 0x01, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Initialize RNG */
+ if (CCB_RNG_Init() != HAL_OK)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Initialize PKA */
+ if (Protect_PKA_Init(hccb, CCB_ECDSA_SIGN_BLOB_USE) != HAL_OK)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Initialize SAES */
+ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* Disable the SAES peripheral */
+ SAES->CR &= ~AES_CR_EN;
+
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Update the state */
+ hccb->State = HAL_CCB_STATE_BUSY;
+
+ /* Wrapping Key configuration */
+ if (WrappingKeyConfiguration(hccb, CCB_ECDSA_SIGN_BLOB_USE, pWrappingKey) != HAL_OK)
+ {
+ /* Set state, error code and return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x012 */
+ if (CCB_WaitOperStep(hccb, 0x012, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Update the state */
+ hccb->State = HAL_CCB_STATE_BUSY;
+
+ /* set operand size (in word 32bits)*/
+
+ operand_size = 2UL * ((uint32_t)(((pCurveParam->modulusSizeByte) + 7UL) / 8UL) + 1UL);
+
+ if ((operand_size % 4UL) != 0UL)
+ {
+ cipherkey_size = operand_size - 2UL;
+ }
+ else
+ {
+ cipherkey_size = operand_size;
+ }
+
+ /* Set Hash message */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_HASH_E ], pHash, pCurveParam->modulusSizeByte);
+
+ /* Initial Phase Processing */
+ if (CCB_BlobUse_InitialPhase(hccb, pWrappedPrivateKeyBlob->pIV, pWrappedPrivateKeyBlob->pTag) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x13 */
+ if (CCB_WaitOperStep(hccb, 0x13, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Set ECDSA parameters */
+ if (CCB_ECDSASign_SetPram(hccb, pCurveParam) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Set SAES GCMPH Payload phase and trig OPSTEP that trig OPSTEP transition 0x13 --> 0x14 */
+ MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_1);
+
+ /* Wait until OPSTEP is set to 0x14 */
+ if (CCB_WaitOperStep(hccb, 0x14, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Write encrypted Key*/
+ for (offset = 0UL; offset < cipherkey_size; offset++)
+ {
+ WRITE_REG(SAES->DINR, pWrappedPrivateKeyBlob->pWrappedKey[cipherkey_size - (offset + 1UL)]);
+
+ if ((offset % 4UL) == 0x3UL)
+ {
+ /* Wait until CCF flag is SET in SAES */
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Write key in PKA RAM */
+ for (count = 0UL; count < 4UL; count++)
+ {
+ PKA->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + count_block + count] = CCB_MAGIC_VALUE;
+ }
+ count_block += 4UL;
+ }
+ }
+
+ if ((operand_size % 4UL) != 0UL)
+ {
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + cipherkey_size);
+ }
+ /* Wait until DATAOKF flag is SET in PKA and trig OPSTEP transition 0x14 --> 0x16 */
+ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_DATAOKF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x16 */
+ if (CCB_WaitOperStep(hccb, 0x16, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Write random k */
+ for (offset = 0UL; offset < (operand_size - 2UL); offset++)
+ {
+ /* Wait for RNG Data Ready flag */
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+ PKA->RAM[PKA_ECDSA_SIGN_IN_K + offset] = CCB_FAKE_VALUE;
+ }
+
+ /* Padding at zero */
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_K + offset);
+
+ /* Wait for PKA RNGOK flag : GCMPH = 0x3 (final phase) as events that trig OPSTEP transition 0x16 --> 0x17 */
+ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_RNGOKF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x17 */
+ if (CCB_WaitOperStep(hccb, 0x17, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Final phase processing */
+ if (CCB_BlobUse_FinalPhase(hccb, CCB_ECDSA_SIGN_BLOB_USE, pCurveParam->modulusSizeByte) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x18 */
+ if (CCB_WaitOperStep(hccb, 0x18, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* SET PKA START operation bit and trig OPSTEP transition 0x18 --> 0x19 */
+ SET_BIT(PKA->CR, PKA_CR_START);
+
+ /* Wait until OPSTEP is set to 0x19 */
+ if (CCB_WaitOperStep(hccb, 0x19, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until end of operation flag is SET in PKA and trig OPSTEP transition 0x19 --> 0x1A */
+ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_PROCENDF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x1A */
+ if (CCB_WaitOperStep(hccb, 0x1A, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Check PKA Operation error result */
+ if ((PKA->RAM[PKA_ECDSA_SIGN_OUT_ERROR]) != CCB_PKA_ERROR_OPERATION_NONE)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+ /* Read r part signature */
+ CCB_Memcpy_u32_to_u8(pSignature->pRSign, &PKA->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], pCurveParam->modulusSizeByte);
+ /* Read s part signature */
+ CCB_Memcpy_u32_to_u8(pSignature->pSSign, &PKA->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], pCurveParam->modulusSizeByte);
+
+
+ /* set CCB IPRST */
+ SET_BIT(hccb->Instance->CR, CCB_CR_IPRST);
+
+ /* CCB is busy while CCB IPRST is in progress */
+ if (CCB_WaitFLAG(hccb, CCB_SR_BUSY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* clear CCB IPRST */
+ CLEAR_BIT(hccb->Instance->CR, CCB_CR_IPRST);
+
+ /* Update the CCB state */
+ hccb->State = HAL_CCB_STATE_READY;
+ }
+
+ else
+ {
+ /* Set state, error code and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ hccb->ErrorCode = HAL_CCB_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Return HAL OK */
+ return HAL_OK;
+}
+
+/**
+ * @brief Blob Usage: ECDSA Compute Public Key.
+ * @param hccb CCB handle.
+ * @param pCurveParam pointer to the Curve parameters.
+ * @param pWrappingKey pointer to the Wrapping Key structure.
+ * @param pWrappedPrivateKeyBlob pointer to the related wrapped Private Key Blob.
+ * @param pPublicKey pointer to the output public key.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CCB_ECDSA_ComputePublicKey(CCB_HandleTypeDef *hccb, CCB_ECDSACurveParamTypeDef *pCurveParam,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ CCB_ECDSAKeyBlobTypeDef *pWrappedPrivateKeyBlob,
+ CCB_ECCMulPointTypeDef *pPublicKey)
+{
+ if (hccb->State == HAL_CCB_STATE_READY)
+ {
+ if (CCB_ECC_ComputeScalarMul(hccb, pCurveParam, pWrappingKey, pWrappedPrivateKeyBlob->pIV,
+ pWrappedPrivateKeyBlob->pTag, pWrappedPrivateKeyBlob->pWrappedKey, NULL, pPublicKey,
+ NULL, CCB_COMPUTE_PUBLIC_KEY) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ else
+ {
+ /* Set state, error code and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ hccb->ErrorCode = HAL_CCB_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Return HAL OK */
+ return HAL_OK;
+}
+
+/**
+ * @brief Blob Creation: ECC Wrap the private Key (input from user).
+ * @param hccb CCB handle.
+ * @param pCurveParam pointer to the Curve parameters.
+ * @param pClearPrivateKey pointer to the clear private key.
+ * @param pWrappingKey pointer to the Wrapping Key structure.
+ * @param pWrappedPrivateKeyBlob pointer to the related wrapped Private Key Blob.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CCB_ECC_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_ECCMulCurveParamTypeDef *pCurveParam,
+ const uint8_t *pClearPrivateKey, CCB_WrappingKeyTypeDef *pWrappingKey,
+ CCB_ECCMulKeyBlobTypeDef *pWrappedPrivateKeyBlob)
+{
+ uint8_t random = 0;
+ uint32_t public_key[2][20] = {{0UL}, {0UL}};
+ __IO uint8_t f_count;
+ uint32_t count;
+ uint32_t key_size;
+ uint32_t iv_temp[4] = {0};
+ uint32_t tag_temp[4] = {0};
+ uint32_t wrapped_key_temp[80] = {0};
+ uint32_t tickstart;
+
+ if (hccb->State == HAL_CCB_STATE_READY)
+ {
+
+ if (Unprotected_PKA_Init() != HAL_OK)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ if (CCB_RNG_Init() != HAL_OK)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ if (PKA_ECC_ComputeScalarMul(pCurveParam, pClearPrivateKey, public_key) != HAL_OK)
+ {
+ if (PKA_RAM_Erase() != HAL_OK)
+ {
+ hccb->ErrorCode |= HAL_CCB_ERROR_PKARAM_ERASE;
+ }
+ return HAL_ERROR;
+ }
+
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ tickstart = HAL_GetTick();
+
+ while (random == 0U)
+ {
+ random = (uint8_t)(RNG->DR & 0xFFU);
+ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE)
+ {
+ /* Set state and return error */
+ return HAL_ERROR;
+ }
+ }
+
+ f_count = 0;
+ while (f_count < random)
+ {
+ f_count++;
+ }
+
+ if (CCB_ECC_ScalarMulBlobCreation(hccb, pCurveParam, pClearPrivateKey, pWrappingKey,
+ iv_temp, tag_temp, wrapped_key_temp,
+ CCB_ECC_SCALAR_MUL_CPU_BLOB_CREATION) != HAL_OK)
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+
+ /* Compute CCB public key */
+ if (CCB_ECC_ComputeScalarMul(hccb, pCurveParam, pWrappingKey, iv_temp, tag_temp, wrapped_key_temp, NULL,
+ NULL, &public_key[0][0], CCB_VERIF_OPERATION_ENABLED) != HAL_OK)
+
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+
+ }
+
+ else
+ {
+ /* Set state, error code and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ hccb->ErrorCode = HAL_CCB_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Update the CCB state */
+ hccb->State = HAL_CCB_STATE_READY;
+
+ /* Export created Blob */
+ key_size = CCB_get_cipherkey_size(pCurveParam);
+ for (count = 0U; count < key_size; count++)
+ {
+ if (count < CCB_BLOCK_SIZE)
+ {
+ pWrappedPrivateKeyBlob->pIV[count] = iv_temp[count];
+ pWrappedPrivateKeyBlob->pTag[count] = tag_temp[count];
+ }
+ pWrappedPrivateKeyBlob->pWrappedKey[count] = wrapped_key_temp[count];
+ }
+
+ /* Return HAL OK */
+ return HAL_OK;
+}
+
+/**
+ * @brief Blob Creation: ECC generate (by RNG) and wrap the private Key (no user input).
+ * @param hccb CCB handle.
+ * @param pCurveParam pointer to the Curve parameters.
+ * @param pWrappingKey pointer to the Wrapping Key structure.
+ * @param pWrappedPrivateKeyBlob pointer to the related wrapped Private Key Blob.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CCB_ECC_GenerateWrapPrivateKey(CCB_HandleTypeDef *hccb,
+ CCB_ECCMulCurveParamTypeDef *pCurveParam,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ CCB_ECCMulKeyBlobTypeDef *pWrappedPrivateKeyBlob)
+{
+
+ if (hccb->State == HAL_CCB_STATE_READY)
+ {
+ /* CCB ECC generate private wrap key */
+ if (CCB_ECC_ScalarMulBlobCreation(hccb, pCurveParam, NULL, pWrappingKey,
+ pWrappedPrivateKeyBlob->pIV, pWrappedPrivateKeyBlob->pTag,
+ pWrappedPrivateKeyBlob->pWrappedKey,
+ CCB_ECC_SCALAR_MUL_RNG_BLOB_CREATION) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Set state, error code and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ hccb->ErrorCode = HAL_CCB_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Update the CCB state */
+ hccb->State = HAL_CCB_STATE_READY;
+
+ /* Return HAL OK */
+ return HAL_OK;
+}
+
+/**
+ * @brief Blob Usage: ECC Compute Scalar Multiplication.
+ * @param hccb CCB handle.
+ * @param pCurveParam pointer to the Curve parameters.
+ * @param pWrappingKey pointer to the Wrapping Key structure.
+ * @param pInputPoint pointer to the input point structure.
+ * @param pWrappedPrivateKeyBlob pointer to the related wrapped Private Key Blob.
+ * @param pOutputPoint pointer to the output point.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_ECCMulCurveParamTypeDef *pCurveParam,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ CCB_ECCMulKeyBlobTypeDef *pWrappedPrivateKeyBlob,
+ CCB_ECCMulPointTypeDef *pInputPoint,
+ CCB_ECCMulPointTypeDef *pOutputPoint)
+{
+ if (hccb->State == HAL_CCB_STATE_READY)
+ {
+ if (CCB_ECC_ComputeScalarMul(hccb, pCurveParam, pWrappingKey, pWrappedPrivateKeyBlob->pIV,
+ pWrappedPrivateKeyBlob->pTag, pWrappedPrivateKeyBlob->pWrappedKey,
+ pInputPoint, pOutputPoint, NULL, CCB_VERIF_OPERATION_DISABLED) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ else
+ {
+ /* Set state, error code and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ hccb->ErrorCode = HAL_CCB_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Return HAL OK */
+ return HAL_OK;
+}
+
+/**
+ * @brief Blob Creation: RSA Wrap the private Key (input from user).
+ * @param hccb CCB handle.
+ * @param pParam pointer to the modular exponatiation parameters.
+ * @param pRSAClearPrivateKey pointer to the clear Private Key.
+ * @param pWrappingKey pointer to the Wrapping Key structure.
+ * @param pWrappedPrivateKeyBlob pointer to the related wrapped Private Key Blob.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CCB_RSA_WrapPrivateKey(CCB_HandleTypeDef *hccb, CCB_RSAParamTypeDef *pParam,
+ const CCB_RSAClearKeyTypeDef *pRSAClearPrivateKey,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ CCB_RSAKeyBlobTypeDef *pWrappedPrivateKeyBlob)
+{
+ uint8_t exp_base[520U] = {0};
+ uint32_t count;
+ __IO uint16_t f_count;
+ uint16_t random0 = 0;
+ uint32_t modular_exp_ref[520U] = {0};
+ uint32_t operand_size;
+ uint32_t cipherkey_size;
+ uint32_t iv_temp[4] = {0};
+ uint32_t tag_temp[4] = {0};
+ uint32_t wrapped_exp[520U] = {0};
+ uint32_t wrapped_phi[520U] = {0};
+ uint32_t tickstart;
+
+ if (hccb->State == HAL_CCB_STATE_READY)
+ {
+ if (CCB_RNG_Init() != HAL_OK)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ for (uint32_t offset = 0U; offset < pParam->modulusSizeByte; offset++)
+ {
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ tickstart = HAL_GetTick();
+
+ while (exp_base[offset] == 0U)
+ {
+ exp_base[offset] = (uint8_t)(RNG->DR & 0xFFU);
+ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE)
+ {
+ /* Set state and return error */
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ tickstart = HAL_GetTick();
+
+ while (random0 == 0U)
+ {
+ random0 = (uint16_t)(RNG->DR & 0x3FFU);
+ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE)
+ {
+ /* Set state and return error */
+ return HAL_ERROR;
+ }
+ }
+
+ if (Unprotected_PKA_Init() != HAL_OK)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ if (PKA_RSA_ComputeModularExp(pParam, pRSAClearPrivateKey, (uint8_t *)exp_base, modular_exp_ref) != HAL_OK)
+ {
+ if (PKA_RAM_Erase() != HAL_OK)
+ {
+ hccb->ErrorCode |= HAL_CCB_ERROR_PKARAM_ERASE;
+ }
+ return HAL_ERROR;
+ }
+
+ if (CCB_RNG_Init() != HAL_OK)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ f_count = 0;
+ while (f_count < random0)
+ {
+ f_count++;
+ }
+
+ if (CCB_RSA_ExpBlobCreation(hccb, pParam, pRSAClearPrivateKey, pWrappingKey, iv_temp, tag_temp, wrapped_exp,
+ wrapped_phi) != HAL_OK)
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+
+ if (CCB_RSA_ComputeModularExp(hccb, pParam, pWrappingKey, iv_temp, tag_temp, wrapped_exp, wrapped_phi,
+ (uint8_t *)exp_base, NULL, modular_exp_ref,
+ CCB_VERIF_OPERATION_ENABLED) != HAL_OK)
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+ }
+
+ else
+ {
+ /* Set state, error code and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ hccb->ErrorCode = HAL_CCB_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Update the CCB state */
+ hccb->State = HAL_CCB_STATE_READY;
+
+ /* set operand size */
+ operand_size = 2UL * ((uint32_t)(((pParam->modulusSizeByte) + 7UL) / 8UL) + 1UL);
+ if ((operand_size % 4UL) != 0UL)
+ {
+ cipherkey_size = operand_size - 2UL;
+ }
+ else
+ {
+ cipherkey_size = operand_size;
+ }
+
+ /* Export created Blob */
+ for (count = 0U; count < cipherkey_size; count++)
+ {
+ if (count < CCB_BLOCK_SIZE)
+ {
+ pWrappedPrivateKeyBlob->pIV[count] = iv_temp[count];
+ pWrappedPrivateKeyBlob->pTag[count] = tag_temp[count];
+ }
+ pWrappedPrivateKeyBlob->pWrappedExp[count] = wrapped_exp[count];
+ pWrappedPrivateKeyBlob->pWrappedPhi[count] = wrapped_phi[count];
+ }
+
+ /* Return HAL OK */
+ return HAL_OK;
+}
+
+/**
+ * @brief Blob Usage: RSA Compute Modular exponentiation.
+ * @param hccb CCB handle.
+ * @param pParam pointer to the modular exponatiation parameters.
+ * @param pWrappingKey pointer to the Wrapping Key structure.
+ * @param pOperand pointer to the operand.
+ * @param pWrappedPrivateKeyBlob pointer to the related wrapped Private Key Blob.
+ * @param pModularExp pointer to the output operation.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_RSAParamTypeDef *pParam,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ CCB_RSAKeyBlobTypeDef *pWrappedPrivateKeyBlob,
+ const uint8_t *pOperand, uint8_t *pModularExp)
+{
+ if (hccb->State == HAL_CCB_STATE_READY)
+ {
+ if (CCB_RSA_ComputeModularExp(hccb, pParam, pWrappingKey, pWrappedPrivateKeyBlob->pIV,
+ pWrappedPrivateKeyBlob->pTag, pWrappedPrivateKeyBlob->pWrappedExp,
+ pWrappedPrivateKeyBlob->pWrappedPhi, pOperand,
+ pModularExp, NULL, CCB_VERIF_OPERATION_DISABLED) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ else
+ {
+ /* Set state, error code and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ hccb->ErrorCode = HAL_CCB_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Update the CCB state */
+ hccb->State = HAL_CCB_STATE_READY;
+
+ /* Return HAL OK */
+ return HAL_OK;
+}
+
+/**
+ * @brief Processing Error callback. Infinite loop against intrusion.
+ * @param hccb : CCB handle
+ * @retval None
+ */
+__weak void HAL_CCB_IntrusionCallback(CCB_HandleTypeDef *hccb)
+{
+ for (;;)
+ {
+ NVIC_SystemReset();
+ }
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CCB_IntrusionCallback could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/**
+ * @brief Wait CCB Operation step
+ * @param hccb CCB handle
+ * @param step ctep to wait
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CCB_WaitOperStep(CCB_HandleTypeDef *hccb, uint32_t step, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ tickstart = HAL_GetTick();
+
+ /* Wait until OPSTEP is set */
+ while ((READ_REG(hccb->Instance->SR) & step) != step)
+ {
+ /* Check for the Timeout */
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Wait CCB Flag
+ * @param hccb CCB handle
+ * @param flag Specifies the flag to check
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CCB_WaitFLAG(CCB_HandleTypeDef *hccb, uint32_t flag, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while (HAL_IS_BIT_SET(hccb->Instance->SR, flag))
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Wait PKA Flag
+ * @param hccb CCB handle
+ * @param flag Specifies the flag to check
+ * @param Timeout Timeout duration
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef Protect_PKA_WaitFLAG(CCB_HandleTypeDef *hccb, uint32_t flag, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while (HAL_IS_BIT_CLR(PKA->SR, flag))
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ CLEAR_BIT(PKA->CR, PKA_CR_EN);
+
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Clear flag */
+ SET_BIT(PKA->CLRFR, flag);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Wait PKA Flag
+ * @param flag Specifies the flag to check
+ * @param Timeout Timeout duration
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef Unprotect_PKA_WaitFLAG(uint32_t flag, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while (HAL_IS_BIT_CLR(PKA->SR, flag))
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ CLEAR_BIT(PKA->CR, PKA_CR_EN);
+
+ /* return error */
+ return HAL_ERROR;
+ }
+ }
+
+ /* Clear flag */
+ SET_BIT(PKA->CLRFR, flag);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Wait RNG Flag
+ * @param flag Specifies the flag to check
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CCB_RNG_Wait_SET_FLAG(uint32_t flag, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while (HAL_IS_BIT_CLR(RNG->SR, flag))
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ RNG->CR &= ~RNG_CR_RNGEN;
+
+ /* Set state and return error */
+ return HAL_ERROR;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Wait SAES Flag
+ * @param hccb CCB handle
+ * @param flag Specifies the flag to check
+ * @param Status Flag status (SET or RESET)
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef Protect_SAES_WaitFLAG(CCB_HandleTypeDef *hccb, uint32_t flag, FlagStatus Status,
+ uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while (HAL_CCB_GET_SAES_FLAG(flag) != Status)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ SAES->CR &= ~AES_CR_EN;
+
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Clear flag */
+ SET_BIT(SAES->ICR, flag);
+
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set ECDSA signture parameters in related PKA RAM address
+ * @param hccb CCB handle
+ * @param in pointer to the ECDSA signture parametersstructure
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CCB_ECDSASign_SetPram(CCB_HandleTypeDef *hccb, CCB_ECDSACurveParamTypeDef *in)
+{
+ /* Get the prime order n length */
+ PKA->RAM[PKA_ECDSA_SIGN_IN_ORDER_NB_BITS]
+ = GetOptBitSize_u8(in->primeOrderSizeByte, *(in->pPrimeOrder));
+ PKA->RAM[PKA_ECDSA_SIGN_IN_ORDER_NB_BITS + 1U] = 0x0U;
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Get the modulus p length */
+ PKA->RAM[PKA_ECDSA_SIGN_IN_MOD_NB_BITS] = GetOptBitSize_u8(in->modulusSizeByte, *(in->pModulus));
+ PKA->RAM[PKA_ECDSA_SIGN_IN_MOD_NB_BITS + 1U] = 0x0U;
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Get the coefficient a sign */
+ PKA->RAM[PKA_ECDSA_SIGN_IN_A_COEFF_SIGN] = in->coefSignA;
+ PKA->RAM[PKA_ECDSA_SIGN_IN_A_COEFF_SIGN + 1U] = 0x0;
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Move the input parameters coefficient |a| to PKA RAM */
+ if (CCB_SetPram(hccb, in->modulusSizeByte, PKA_ECDSA_SIGN_IN_A_COEFF, in->pAbsCoefA) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Move the input parameters coefficient B to PKA RAM */
+ if (CCB_SetPram(hccb, in->modulusSizeByte, PKA_ECDSA_SIGN_IN_B_COEFF, in->pCoefB) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Move the input parameters modulus value p to PKA RAM */
+ if (CCB_SetPram(hccb, in->modulusSizeByte, PKA_ECDSA_SIGN_IN_MOD_GF, in->pModulus) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Move the input parameters prime order n to PKA RAM */
+ if (CCB_SetPram(hccb, in->modulusSizeByte, PKA_ECDSA_SIGN_IN_ORDER_N, in->pPrimeOrder) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Move the input parameters base point G coordinate x to PKA RAM */
+ if (CCB_SetPram(hccb, in->modulusSizeByte, PKA_ECDSA_SIGN_IN_INITIAL_POINT_X, in->pPointX) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Move the input parameters base point G coordinate y to PKA RAM */
+ if (CCB_SetPram(hccb, in->modulusSizeByte, PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y, in->pPointY) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set ECC scalar multiplication parameters in related PKA RAM address
+ * @param hccb CCB handle
+ * @param in pointer to the ECC parametersstructure
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CCB_ECCMul_SetPram(CCB_HandleTypeDef *hccb, CCB_ECCMulCurveParamTypeDef *in)
+{
+ /* Get the prime order n length */
+ PKA->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS]
+ = GetOptBitSize_u8(in->primeOrderSizeByte, *(in->pPrimeOrder));
+ PKA->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS + 1U] = 0x0;
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Get the modulus p length */
+ PKA->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = GetOptBitSize_u8(in->modulusSizeByte, *(in->pModulus));
+ PKA->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS + 1U] = 0x0;
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Get the coefficient a sign */
+ PKA->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = in->coefSignA;
+ PKA->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN + 1U] = 0x0;
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Move the input parameters coefficient |a| to PKA RAM */
+ if (CCB_SetPram(hccb, in->modulusSizeByte, PKA_ECC_SCALAR_MUL_IN_A_COEFF, in->pAbsCoefA) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Move the input parameters coefficient B to PKA RAM */
+ if (CCB_SetPram(hccb, in->modulusSizeByte, PKA_ECC_SCALAR_MUL_IN_B_COEFF, in->pCoefB) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Move the input parameters modulus value p to PKA RAM */
+ if (CCB_SetPram(hccb, in->modulusSizeByte, PKA_ECC_SCALAR_MUL_IN_MOD_GF, in->pModulus) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Move the input parameters prime order n to PKA RAM */
+ if (CCB_SetPram(hccb, in->modulusSizeByte, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER, in->pPrimeOrder) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set RSA sModular Exponentiation parameters in related PKA RAM address
+ * @param hccb CCB handle
+ * @param in pointer to the ECC parametersstructure
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CCB_RSAModExp_SetPram(CCB_HandleTypeDef *hccb, CCB_RSAParamTypeDef *in)
+{
+ /* Get the exp length */
+ PKA->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = GetOptBitSize_u8(in->expSizeByte, *(in->pMod));
+ PKA->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS + 1U] = 0x0U;
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Get the modulus n length */
+ PKA->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = GetOptBitSize_u8(in->modulusSizeByte, *(in->pMod));
+ PKA->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS + 1U] = 0x0U;
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Move the input parameters modulus to PKA RAM */
+ if (CCB_SetPram(hccb, in->modulusSizeByte, PKA_MODULAR_EXP_PROTECT_IN_MODULUS, in->pMod) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set CCB parameters
+ * @param hccb CCB handle
+ * @param modulusSizeByte Modulus size in byte
+ * @param dst_address destination address
+ * @param src Pointer to source
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CCB_SetPram(CCB_HandleTypeDef *hccb, uint32_t modulusSizeByte, uint32_t dst_address,
+ const uint8_t *src)
+{
+ uint32_t offset;
+ uint32_t operand_size;
+ operand_size = 2UL * ((uint32_t)(((modulusSizeByte) + 7UL) / 8UL) + 1UL);
+
+ if ((modulusSizeByte % 8UL) != 0UL)
+ {
+ for (offset = 0; offset < (operand_size - 4UL); offset += 2UL)
+ {
+ CCB_Memcpy_u8_to_u64(&PKA->RAM[dst_address + offset],
+ &src[(modulusSizeByte) - ((offset * 4UL) + 1UL)]);
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+ }
+
+ CCB_Memcpy_Not_Align(&PKA->RAM[dst_address + offset],
+ &src[(modulusSizeByte) - ((offset * 4UL) + 1UL)], modulusSizeByte % 8UL);
+
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+ RAM_PARAM_END(PKA->RAM, dst_address + ((modulusSizeByte + 7UL) / 4UL));
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+ }
+
+ else
+ {
+ for (offset = 0; offset < (operand_size - 2UL); offset += 2UL)
+ {
+ CCB_Memcpy_u8_to_u64(&PKA->RAM[dst_address + offset],
+ &src[(modulusSizeByte) - ((offset * 4UL) + 1UL)]);
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+ }
+
+ RAM_PARAM_END(PKA->RAM, dst_address
+ + ((modulusSizeByte + 3UL) / 4UL));
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the PKA
+ * @param hccb CCB handle
+ * @param Operation PKA Operation
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef Protect_PKA_Init(CCB_HandleTypeDef *hccb, uint32_t Operation)
+{
+ /* Reset the control register and enable the PKA */
+ PKA->CR = PKA_CR_EN;
+
+ /* Wait the INITOK flag Setting */
+ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_INITOK, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Reset any pending flag */
+ SET_BIT(PKA->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC);
+
+ /* Set the mode and deactivate the interrupts */
+ if ((Operation == CCB_ECDSA_SIGN_CPU_BLOB_CREATION)
+ || (Operation == CCB_ECDSA_SIGN_RNG_BLOB_CREATION)
+ || (Operation == CCB_ECDSA_SIGN_BLOB_USE))
+ {
+ MODIFY_REG(PKA->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE
+ | PKA_CR_OPERRIE, CCB_PKA_ECDSA_SIGNATURE_MODE << PKA_CR_MODE_Pos);
+ }
+
+ else if ((Operation == CCB_ECC_SCALAR_MUL_CPU_BLOB_CREATION)
+ || (Operation == CCB_ECC_SCALAR_MUL_RNG_BLOB_CREATION)
+ || (Operation == CCB_ECC_SCALAR_MUL_BLOB_USE))
+ {
+ MODIFY_REG(PKA->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE
+ | PKA_CR_OPERRIE, CCB_PKA_ECC_MUL_MODE << PKA_CR_MODE_Pos);
+ }
+
+ else if ((Operation == CCB_MODULAR_EXP_CPU_BLOB_CREATION)
+ || (Operation == CCB_MODULAR_EXP_BLOB_USE))
+ {
+ MODIFY_REG(PKA->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE
+ | PKA_CR_OPERRIE, CCB_PKA_MODE_MODULAR_EXP_PROTECT << PKA_CR_MODE_Pos);
+ }
+ else
+ {
+ /* do nothing */
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Unprotected PKA Initialization
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef Unprotected_PKA_Init(void)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Reset the control register and enable the PKA (wait the end of PKA RAM erase) */
+ while ((PKA->CR & PKA_CR_EN) != PKA_CR_EN)
+ {
+ PKA->CR = PKA_CR_EN;
+
+ /* Check the Timeout */
+ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE)
+ {
+ /* Set timeout status */
+ break;
+ }
+ }
+ /* Wait the INITOK flag Setting */
+ if (Unprotect_PKA_WaitFLAG(PKA_SR_INITOK, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Reset any pending flag */
+ SET_BIT(PKA->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the RNG
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CCB_RNG_Init(void)
+{
+ uint32_t tickstart;
+
+ /* Disable RNG */
+ RNG->CR &= ~RNG_CR_RNGEN;
+
+ /* Clock Error Detection Configuration when CONDRT bit is set to 1 */
+ MODIFY_REG(RNG->CR, RNG_CR_CONDRST, RNG_CR_CONDRST);
+#if defined(RNG_CR_NIST_VALUE)
+ /* Recommended value for NIST compliance, refer to application note AN4230 */
+ WRITE_REG(RNG->CR, RNG_CR_NIST_VALUE | RNG_CR_CONDRST);
+#endif /* defined(RNG_CR_NIST_VALUE) */
+#if defined(RNG_HTCR_NIST_VALUE)
+ /* Recommended value for NIST compliance, refer to application note AN4230 */
+ WRITE_REG(RNG->HTCR, RNG_HTCR_NIST_VALUE);
+#endif /* defined(RNG_HTCR_NIST_VALUE) */
+#if defined(RNG_NSCR_NIST_VALUE)
+ WRITE_REG(RNG->NSCR, RNG_NSCR_NIST_VALUE);
+#endif /* defined(RNG_NSCR_NIST_VALUE) */
+
+ /* Writing bit CONDRST=0 */
+ CLEAR_BIT(RNG->CR, RNG_CR_CONDRST);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for conditioning reset process to be completed */
+ while (HAL_IS_BIT_SET(RNG->CR, RNG_CR_CONDRST))
+ {
+ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (HAL_IS_BIT_SET(RNG->CR, RNG_CR_CONDRST))
+ {
+ /* Set state and return error */
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Enable the RNG Peripheral */
+ RNG->CR |= RNG_CR_RNGEN;
+
+ /* verify that no seed error */
+ if ((RNG->SR & (RNG_SR_SEIS)) != (uint32_t)RESET)
+ {
+ /* Set state and return error */
+ return HAL_ERROR;
+ }
+
+ /* Check if data register contains valid random data */
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Wait CCB wrapping key configuration
+ * @param hccb CCB handle
+ * @param Operation Operation
+ * @param pWrappingKey pointer to the wrapping key structure
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef WrappingKeyConfiguration(CCB_HandleTypeDef *hccb, uint32_t Operation,
+ CCB_WrappingKeyTypeDef *pWrappingKey)
+{
+ uint32_t tmp;
+
+ switch (pWrappingKey->WrappingKeyType)
+ {
+ case HAL_CCB_USER_KEY_WRAPPED:
+
+ if (Protect_SAES_UnwrapKey(hccb, pWrappingKey, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ if ((Operation == CCB_ECDSA_SIGN_CPU_BLOB_CREATION) || (Operation == CCB_ECDSA_SIGN_RNG_BLOB_CREATION)
+ || (Operation == CCB_ECC_SCALAR_MUL_CPU_BLOB_CREATION)
+ || (Operation == CCB_ECC_SCALAR_MUL_RNG_BLOB_CREATION)
+ || (Operation == CCB_MODULAR_EXP_CPU_BLOB_CREATION))
+ {
+ /* SAES: GCMPH = 0x0 (initial phase) as event that trig OPSTEP 0x1 --> 0x2 */
+ WRITE_REG(SAES->CR, AES_CR_KEYSIZE | AES_CR_CHMOD_0 | AES_CR_CHMOD_1);
+ }
+
+ else if ((Operation == CCB_ECDSA_SIGN_BLOB_USE) || (Operation == CCB_ECC_SCALAR_MUL_BLOB_USE)
+ || (Operation == CCB_MODULAR_EXP_BLOB_USE))
+ {
+ /* SAES: GCMPH = 0x0 (initial phase) as event that trig OPSTEP 0x1 --> 0x12 */
+ WRITE_REG(SAES->CR, AES_CR_KEYSIZE | AES_CR_CHMOD_0
+ | AES_CR_CHMOD_1 | AES_CR_MODE_1);
+ }
+
+ else
+ {
+ /* do nothing */
+ }
+ break;
+
+ case HAL_CCB_USER_KEY_HW:
+
+ if ((Operation == CCB_ECDSA_SIGN_CPU_BLOB_CREATION) || (Operation == CCB_ECDSA_SIGN_RNG_BLOB_CREATION)
+ || (Operation == CCB_ECC_SCALAR_MUL_CPU_BLOB_CREATION)
+ || (Operation == CCB_ECC_SCALAR_MUL_RNG_BLOB_CREATION)
+ || (Operation == CCB_MODULAR_EXP_CPU_BLOB_CREATION))
+ {
+ /* SAES: GCMPH = 0x0 (initial phase) as event that trig OPSTEP 0x1 --> 0x2 */
+ WRITE_REG(SAES->CR, AES_CR_KEYSEL_0 | AES_CR_KEYSIZE | AES_CR_CHMOD_0
+ | AES_CR_CHMOD_1);
+ }
+
+ else if ((Operation == CCB_ECDSA_SIGN_BLOB_USE) || (Operation == CCB_ECC_SCALAR_MUL_BLOB_USE)
+ || (Operation == CCB_MODULAR_EXP_BLOB_USE))
+ {
+ /* SAES: GCMPH = 0x0 (initial phase) as event that trig OPSTEP 0x1 --> 0x12 */
+ WRITE_REG(SAES->CR, AES_CR_KEYSEL_0 | AES_CR_KEYSIZE | AES_CR_CHMOD_0
+ | AES_CR_CHMOD_1 | AES_CR_MODE_1);
+ }
+
+ else
+ {
+ /* Do nothing */
+ }
+
+ /* Wait for Key valid to be set */
+ if (Protect_SAES_WaitFLAG(hccb, AES_SR_KEYVALID, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ else
+ {
+ /* do nothing */
+ }
+ break;
+
+ case HAL_CCB_USER_KEY_HSW:
+
+ if ((Operation == CCB_ECDSA_SIGN_CPU_BLOB_CREATION) || (Operation == CCB_ECDSA_SIGN_RNG_BLOB_CREATION)
+ || (Operation == CCB_ECC_SCALAR_MUL_CPU_BLOB_CREATION)
+ || (Operation == CCB_ECC_SCALAR_MUL_RNG_BLOB_CREATION)
+ || (Operation == CCB_MODULAR_EXP_CPU_BLOB_CREATION))
+ {
+ /* SAES: GCMPH = 0x0 (initial phase) as event that trig OPSTEP 0x1 --> 0x2 */
+ WRITE_REG(SAES->CR, AES_CR_KEYSEL_0 | AES_CR_KEYSIZE | AES_CR_CHMOD_0
+ | AES_CR_CHMOD_1);
+ }
+
+ else if ((Operation == CCB_ECDSA_SIGN_BLOB_USE) || (Operation == CCB_ECC_SCALAR_MUL_BLOB_USE)
+ || (Operation == CCB_MODULAR_EXP_BLOB_USE))
+ {
+ /* SAES: GCMPH = 0x0 (initial phase) as event that trig OPSTEP 0x1 --> 0x12 */
+ WRITE_REG(SAES->CR, AES_CR_KEYSEL_0 | AES_CR_KEYSIZE | AES_CR_CHMOD_0 |
+ AES_CR_CHMOD_1 | AES_CR_MODE_1);
+ }
+
+ else
+ {
+ /* Do nothing */
+ }
+
+ /* Wait for Key valid to be set */
+ if (Protect_SAES_WaitFLAG(hccb, AES_SR_KEYVALID, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ else
+ {
+ /* do nothing */
+ }
+
+ /*we need to read BKP register from TAMP to transfer SW Key to the SAES where
+ it will be XOR with HW key, new key in SAES register*/
+ for (uint32_t k = 0UL; k < 8UL; k++)
+ {
+ /* Determine address of the specified Backup register */
+ tmp = (uint32_t)(&(TAMP->BKP0R));
+ tmp += (k * 4UL);
+
+ /* Read the data from the specified register */
+ if ((*(__IO uint32_t *)tmp) != 0UL)
+ {
+ /* Set state, error code and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ hccb->ErrorCode = HAL_CCB_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+ }
+ break;
+
+ default :
+ return HAL_ERROR;
+ break;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Unwrap SAES key
+ * @param hccb CCB handle
+ * @param pWrappingKey pointer to the wrapping key structure
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef Protect_SAES_UnwrapKey(CCB_HandleTypeDef *hccb, const CCB_WrappingKeyTypeDef *pWrappingKey,
+ uint32_t Timeout)
+{
+ uint32_t in_count = 0UL;
+ uint32_t tickstart = HAL_GetTick() ;
+
+ if (pWrappingKey->AES_Algorithm != CCB_AES_ECB)
+ {
+ WRITE_REG(SAES->CR, AES_CR_KEYSEL_0 | AES_CR_KMOD_0 | AES_CR_KEYSIZE | AES_CR_CHMOD_0);
+ }
+ else
+ {
+ WRITE_REG(SAES->CR, AES_CR_KEYSEL_0 | AES_CR_KMOD_0 | AES_CR_KEYSIZE);
+ }
+
+ /* Wait for Key valid to be set */
+ if (Protect_SAES_WaitFLAG(hccb, AES_SR_KEYVALID, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the SAES peripheral */
+ SAES->CR &= ~AES_CR_EN;
+
+ /* wait for key valid */
+ while (HAL_IS_BIT_CLR(SAES->SR, AES_SR_KEYVALID))
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ SAES->CR &= ~AES_CR_EN;
+
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Set the operating mode*/
+ MODIFY_REG(SAES->CR, AES_CR_KMOD, AES_CR_KMOD_0);
+
+ /* key preparation for decryption, operating mode 2*/
+ MODIFY_REG(SAES->CR, AES_CR_MODE, AES_CR_MODE_0);
+
+ /* Enable SAES */
+ SAES->CR |= AES_CR_EN;
+
+ /* wait CCF in SAES */
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(SAES->CR, AES_CR_MODE, AES_CR_MODE_1);
+
+ if (pWrappingKey->AES_Algorithm != CCB_AES_ECB)
+ {
+ /* Set the Initialization Vector */
+ SAES->IVR3 = *(uint32_t *)(pWrappingKey->pInitVect);
+ SAES->IVR2 = *(uint32_t *)(pWrappingKey->pInitVect + 1U);
+ SAES->IVR1 = *(uint32_t *)(pWrappingKey->pInitVect + 2U);
+ SAES->IVR0 = *(uint32_t *)(pWrappingKey->pInitVect + 3U);
+ }
+ /* Enable CRYP */
+ SAES->CR |= AES_CR_EN;
+
+ /* Set the phase */
+ while (in_count < 8UL) /* symmetric key size is always 256 */
+ {
+ /* Write four times to input the key to encrypt */
+ SAES->DINR = pWrappingKey->pUserWrappedWrappingKey[in_count];
+ in_count++;
+ SAES->DINR = pWrappingKey->pUserWrappedWrappingKey[in_count];
+ in_count++;
+ SAES->DINR = pWrappingKey->pUserWrappedWrappingKey[in_count];
+ in_count++;
+ SAES->DINR = pWrappingKey->pUserWrappedWrappingKey[in_count];
+ in_count++;
+
+ /* wait CCF in SAES */
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Disable the SAES */
+ SAES->CR &= ~AES_CR_EN;
+ SAES->ICR |= 0x0EUL;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Get optimal number of bits inside an array of u8
+ * @param byteNumber Number of u8 inside the array
+ * @param msb Most significant uint8_t of the array
+ */
+static uint32_t GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb)
+{
+ uint32_t position;
+
+ position = 32UL - __CLZ(msb);
+
+ return (((byteNumber - 1UL) * 8UL) + position);
+}
+
+/**
+ * @brief Copy uint32_t array to uint8_t array to fit PKA number representation.
+ * @param dst Pointer to destination
+ * @param src Pointer to source
+ * @param n Number of uint8_t to copy
+ * @retval None.
+ */
+static void CCB_Memcpy_u32_to_u8(uint8_t dst[], __IO const uint32_t src[], size_t n)
+{
+ uint32_t index_uint32_t = 0UL; /* This index is used outside of the loop */
+
+ for (; index_uint32_t < (n / 4UL); index_uint32_t++)
+ {
+ /* Avoid casting from uint8_t* to uint32_t* by copying 4 uint8_t in a row */
+ /* Apply __REV equivalent */
+ uint32_t index_uint8_t = n - 4UL - (index_uint32_t * 4UL);
+ dst[index_uint8_t + 3UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
+ dst[index_uint8_t + 2UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL);
+ dst[index_uint8_t + 1UL] = (uint8_t)((src[index_uint32_t] & 0x00FF0000U) >> 16UL);
+ dst[index_uint8_t + 0UL] = (uint8_t)((src[index_uint32_t] & 0xFF000000U) >> 24UL);
+ }
+
+ /* Manage the buffers not aligned on uint32_t */
+ if ((n % 4UL) == 1UL)
+ {
+ dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
+ }
+ else if ((n % 4UL) == 2UL)
+ {
+ dst[1UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
+ dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL);
+ }
+ else if ((n % 4UL) == 3UL)
+ {
+ dst[2UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
+ dst[1UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL);
+ dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x00FF0000U) >> 16UL);
+ }
+ else
+ {
+ /* The last element is already handle in the loop */
+ }
+}
+
+/**
+ * @brief Copy uint8_t array to uint32_t array to fit number representation
+ * @param dst Pointer to destination
+ * @param src Pointer to source
+ * @param size Number of uint8_t to copy (must be multiple of 4)
+ * @retval None.
+ */
+static void CCB_Memcpy_u8_to_u32(__IO uint32_t dst[], const uint8_t src[], size_t size)
+{
+ uint32_t index = 0UL;
+
+ if (dst != NULL)
+ {
+ if (src != NULL)
+ {
+ for (; index < (size / 4UL); index++)
+ {
+ /* Apply the equivalent of __REV from uint8_t to uint32_t */
+ dst[index] = ((uint32_t)src[(size - (index * 4UL) - 1UL)]) \
+ | ((uint32_t)src[(size - (index * 4UL) - 2UL)] << 8UL) \
+ | ((uint32_t)src[(size - (index * 4UL) - 3UL)] << 16UL) \
+ | ((uint32_t)src[(size - (index * 4UL) - 4UL)] << 24UL);
+ }
+
+ /* Manage the buffers not aligned on uint32_t */
+ if ((size % 4UL) == 1UL)
+ {
+ dst[index] = (uint32_t)src[(size - (index * 4UL) - 1UL)];
+ }
+ else if ((size % 4UL) == 2UL)
+ {
+ dst[index] = ((uint32_t)src[(size - (index * 4UL) - 1UL)]) \
+ | ((uint32_t)src[(size - (index * 4UL) - 2UL)] << 8UL);
+ }
+ else if ((size % 4UL) == 3UL)
+ {
+ dst[index] = ((uint32_t)src[(size - (index * 4UL) - 1UL)]) \
+ | ((uint32_t)src[(size - (index * 4UL) - 2UL)] << 8UL) \
+ | ((uint32_t)src[(size - (index * 4UL) - 3UL)] << 16UL);
+ }
+ else
+ {
+ /* The last element is already handle in the loop */
+ }
+ }
+ }
+}
+
+/**
+ * @brief Copy uint32_t array to uint32_t array.
+ * @param dst Pointer to destination
+ * @param src Pointer to source
+ * @param n Number of u32 to be handled
+ * @retval None.
+ */
+void CCB_Memcpy_u32_to_u32(__IO uint32_t dst[], __IO const uint32_t src[], size_t n)
+{
+ /* For each element in the array */
+ for (uint32_t index = 0UL; index < n; index++)
+ {
+ /* Copy the content */
+ dst[index] = src[index];
+ }
+}
+
+/**
+ * @brief Copy uint8_t array to uint64_t array to fit number representation
+ * @param dst Pointer to destination
+ * @param src Pointer to source
+ * @retval None.
+ */
+static void CCB_Memcpy_u8_to_u64(__IO uint32_t dst[], const uint8_t src[])
+{
+ if ((dst != NULL) && (src != NULL))
+ {
+ /* Apply the equivalent of __REV from uint8_t to uint32_t */
+ dst[0] = ((uint32_t)src[0]) | ((uint32_t)src[-1] << 8UL) | ((uint32_t)src[-2] << 16UL)
+ | ((uint32_t)src[-3] << 24UL);
+ dst[1] = ((uint32_t)src[-4]) | ((uint32_t)src[-5] << 8UL) | ((uint32_t)src[-6] << 16UL)
+ | ((uint32_t)src[-7] << 24UL);
+ }
+}
+
+/**
+ * @brief Copy uint8_t array to uint64_t array to fit number representation
+ * @param dst Pointer to destination
+ * @param src Pointer to source
+ * @param size Pointer to number of uint8_t to copy
+ * @retval None.
+ */
+static void CCB_Memcpy_Not_Align(__IO uint32_t dst[], const uint8_t src[], size_t size)
+{
+ /* Manage the buffers not aligned on uint32_t */
+ if ((size % 8UL) == 1UL)
+ {
+ dst[0] = ((uint32_t)src[0]);
+ dst[1] = 0;
+ }
+ else if ((size % 8UL) == 2UL)
+ {
+ dst[0] = ((uint32_t)src[0]) | ((uint32_t)src[-1] << 8UL);;
+ dst[1] = 0UL;
+ }
+ else if ((size % 8UL) == 3UL)
+ {
+ dst[0] = ((uint32_t)src[0]) | ((uint32_t)src[-1] << 8UL) | ((uint32_t)src[-2] << 16UL);
+ dst[1] = 0UL;
+ }
+
+ else if ((size % 8UL) == 4UL)
+ {
+ dst[0] = ((uint32_t)src[0]) | ((uint32_t)src[-1] << 8UL) | ((uint32_t)src[-2] << 16UL)
+ | ((uint32_t)src[-3] << 24UL);
+ dst[1] = 0UL;
+ }
+
+ else if ((size % 8UL) == 5UL)
+ {
+ dst[0] = ((uint32_t)src[0]) | ((uint32_t)src[-1] << 8UL) | ((uint32_t)src[-2] << 16UL)
+ | ((uint32_t)src[-3] << 24UL);
+ dst[1] = ((uint32_t)src[-4]);
+ }
+ else if ((size % 8UL) == 6UL)
+ {
+ dst[0] = ((uint32_t)src[0]) | ((uint32_t)src[-1] << 8UL) | ((uint32_t)src[-2] << 16UL)
+ | ((uint32_t)src[-3] << 24UL);
+ dst[1] = ((uint32_t)src[-4]) | ((uint32_t)src[-5] << 8UL);
+ }
+ else if ((size % 8UL) == 7UL)
+ {
+ dst[0] = ((uint32_t)src[0]) | ((uint32_t)src[-1] << 8UL) | ((uint32_t)src[-2] << 16UL)
+ | ((uint32_t)src[-3] << 24UL);
+ dst[1] = ((uint32_t)src[-4]) | ((uint32_t)src[-5] << 8UL) | ((uint32_t)src[-6] << 16UL);
+ }
+ else
+ {
+ /* The last element is already handle in the loop */
+ }
+
+}
+
+/**
+ * @brief Get cipher key size
+ * @param pCurveParam to Curve Parameters
+ * @retval cipher key size.
+ */
+static uint32_t CCB_get_cipherkey_size(CCB_ECDSACurveParamTypeDef *pCurveParam)
+{
+ uint32_t operand_size = 2U * ((((pCurveParam->modulusSizeByte) + 7U) / 8U) + 1U);
+
+ if ((operand_size % 4U) != 0U)
+ {
+ return (operand_size - 2U);
+ }
+ else
+ {
+ return operand_size;
+ }
+
+}
+
+/**
+ * @brief Wrap Symmetric Key.
+ * @param hccb CCB handle.
+ * @param pClearAESKey pointer to the clear AES Key.
+ * @param operation operation.
+ * @param pWrappingKey pointer to the Wrapping Key structure.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef CCB_WrapSymmetricKey(CCB_HandleTypeDef *hccb, const uint32_t *pClearAESKey, uint32_t operation,
+ CCB_WrappingKeyTypeDef *pWrappingKey)
+{
+
+ uint32_t i;
+ uint32_t cryp_in_count = 0UL;
+ uint32_t cryp_out_count = 0UL;
+ const uint32_t *pcryp_in_buff = pClearAESKey;
+ uint32_t *pcryp_out_buff = pWrappingKey->pUserWrappedWrappingKey;
+
+ if (hccb->State == HAL_CCB_STATE_READY)
+ {
+
+ /* Set Operation in CCB */
+ MODIFY_REG(CCB->CR, CCB_CR_CCOP, operation);
+
+ /* Wait until OPSTEP is set to 0x01 */
+ if (CCB_WaitOperStep(hccb, 0x01, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Initialize RNG */
+ if (CCB_RNG_Init() != HAL_OK)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Initialize SAES */
+ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* Disable the SAES peripheral clock */
+ SAES->CR &= ~AES_CR_EN;
+
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Update the state */
+ hccb->State = HAL_CCB_STATE_BUSY;
+
+ if (pWrappingKey->AES_Algorithm != CCB_AES_ECB)
+ {
+ WRITE_REG(SAES->CR, AES_CR_KEYSEL_0 | AES_CR_KMOD_0 | AES_CR_KEYSIZE | AES_CR_CHMOD_0);
+ }
+
+ else
+ {
+ WRITE_REG(SAES->CR, AES_CR_KEYSEL_0 | AES_CR_KMOD_0 | AES_CR_KEYSIZE);
+ }
+
+ /* Wait for Key valid to be set */
+ if (Protect_SAES_WaitFLAG(hccb, AES_SR_KEYVALID, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the CRYP peripheral clock */
+ SAES->CR &= ~AES_CR_EN;
+
+ /* Set the operating mode*/
+ MODIFY_REG(SAES->CR, AES_CR_KMOD, AES_CR_KMOD_0);
+
+ /* Encryption operating mode(Mode 0)*/
+ MODIFY_REG(SAES->CR, AES_CR_MODE, 0x0UL); /*!< Encryption mode */
+
+ if (pWrappingKey->AES_Algorithm != CCB_AES_ECB)
+ {
+ /* Set the Initialization Vector */
+ SAES->IVR3 = *(uint32_t *)(pWrappingKey->pInitVect);
+ SAES->IVR2 = *(uint32_t *)(pWrappingKey->pInitVect + 1U);
+ SAES->IVR1 = *(uint32_t *)(pWrappingKey->pInitVect + 2U);
+ SAES->IVR0 = *(uint32_t *)(pWrappingKey->pInitVect + 3U);
+ }
+
+ /* Enable CRYP */
+ SAES->CR |= AES_CR_EN;
+
+ while (cryp_in_count < CCB_SIZE_SKEY_INWORD)
+ {
+ for (i = 0UL; i < 4UL; i++)
+ {
+ SAES->DINR = pcryp_in_buff[cryp_in_count];
+ cryp_in_count++;
+ }
+
+ /* Wait for CCF flag to be raised */
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Clear CCF Flag */
+ SET_BIT(SAES->ICR, AES_ICR_CCF);
+
+ /* Read the output block from the output FIFO and put them in temporary buffer then
+ get CrypOutBuff from temporary buffer */
+ for (i = 0UL; i < 4UL; i++)
+ {
+ pcryp_out_buff[cryp_out_count] = SAES->DOUTR;
+ cryp_out_count++;
+ }
+ }
+ }
+ else
+ {
+ /* Set state, error code and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ hccb->ErrorCode = HAL_CCB_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* CCB IPRST set */
+ SET_BIT(hccb->Instance->CR, CCB_CR_IPRST);
+
+ /* CCB is busy while CCB IPRST is in progress */
+ if (CCB_WaitFLAG(hccb, CCB_SR_BUSY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* clear CCB IPRST */
+ CLEAR_BIT(hccb->Instance->CR, CCB_CR_IPRST);
+
+ /* Update the CCB state */
+ hccb->State = HAL_CCB_STATE_READY;
+
+ /* Return HAL OK */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initial phase processing when blob creation
+ * @param hccb CCB handle
+ * @param pIV pointer to the initil vector
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CCB_BlobCreation_InitialPhase(CCB_HandleTypeDef *hccb, uint32_t *pIV)
+{
+ /* Load IVs from RNG to SAES */
+ SAES->IVR0 = CCB_IV0_VALUE; /* SAES_IVR0 that must be equal to 0x2 */
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* For IV1, IV2 and IV3, random generated values are loaded from RNG to SAES by CCB */
+ SAES->IVR1 = CCB_FAKE_VALUE;
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ SAES->IVR2 = CCB_FAKE_VALUE;
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ SAES->IVR3 = CCB_FAKE_VALUE;
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* if an error occurs, RNGERRF flag is set in PKA */
+ if (HAL_CCB_GET_PKA_FLAG(PKA_SR_RNGERRF) == SET)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ else
+ {
+ /* Read back IVs from SAES */
+ pIV[3] = SAES->IVR3;
+ pIV[2] = SAES->IVR2;
+ pIV[1] = SAES->IVR1;
+ pIV[0] = SAES->IVR0;
+ }
+
+ /* Set EN in SAES_CR*/
+ SAES->CR |= AES_CR_EN;
+
+ /* Wait until CCF is SET in SAES_ISR (end of GCM init) */
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set SAES GCMPH Header phase and trig OPSTEP transition 0x2 --> 0x3 */
+ MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_0 | AES_CR_EN);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initial phase processing when blob use
+ * @param hccb CCB handle
+ * @param pIV pointer to the initil vector
+ * @param pTag pointer to the Tag
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CCB_BlobUse_InitialPhase(CCB_HandleTypeDef *hccb, const uint32_t *pIV, uint32_t *pTag)
+{
+ uint16_t count;
+
+ /* Set IVs from created Blob */
+ SAES->IVR0 = pIV[0];
+ SAES->IVR1 = pIV[1];
+ SAES->IVR2 = pIV[2];
+ SAES->IVR3 = pIV[3];
+
+ /* Set EN in SAES_CR*/
+ SAES->CR |= AES_CR_EN;
+
+ /* Wait until CCF is SET in SAES_ISR (end of GCM init) */
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Write reference tag in CCB */
+ for (count = 0; count < CCB_BLOCK_SIZE; count++)
+ {
+ WRITE_REG(hccb->Instance->REFTAGR[count], pTag[count]);
+ }
+
+ /* Set SAES GCMPH Header phase and trig OPSTEP transition 0x12 --> 0x13 */
+ MODIFY_REG(SAES->CR, AES_CR_GCMPH | AES_CR_EN,
+ AES_CR_GCMPH_0 | AES_CR_EN);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Final phase processing when blob creation
+ * @param hccb CCB handle
+ * @param Operation Operation
+ * @param pTag pointer to the Tag
+ * @param sizeparam size of parameters
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CCB_BlobCreation_FinalPhase(CCB_HandleTypeDef *hccb, uint32_t Operation, uint32_t *pTag,
+ uint32_t sizeparam)
+{
+ uint32_t last_block[4] = {0};
+ uint16_t count;
+ uint32_t operand_size;
+ uint32_t cipherkey_size;
+
+ /* set operand size in 32bits */
+ operand_size = 2UL * ((uint32_t)(((sizeparam) + 7UL) / 8UL) + 1UL);
+ if ((operand_size % 4UL) != 0UL)
+ {
+ cipherkey_size = operand_size - 2UL;
+ }
+ else
+ {
+ cipherkey_size = operand_size;
+ }
+ /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */
+ HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC);
+
+ /* Preparing last Block */
+ if (Operation == CCB_MODULAR_EXP_CPU_BLOB_CREATION)
+ {
+ /* bitsize of exp length, modulus n length and modulus (address and data)*/
+ last_block[1] = ((64UL * 2UL) + (operand_size * 32UL)) * 2UL;
+
+ /* ciphred data size*/
+ last_block[3] = cipherkey_size * 32UL;
+ }
+
+ else if ((Operation == CCB_ECDSA_SIGN_CPU_BLOB_CREATION) || (Operation == CCB_ECDSA_SIGN_RNG_BLOB_CREATION))
+ {
+ /* bitsize of |a|, b, p, n, Gx and Gy --> sizeparam*8*6*2 (address and data); n length,
+ plength and a sign --> 64*3*2 (address and data) */
+ last_block[1] = (((operand_size * 32UL) * 6UL) + (3UL * 64UL)) * 2UL;
+
+ /* 1 ciphred data with 256 size*/
+ last_block[3] = cipherkey_size * 32UL;
+ }
+ else
+ {
+ /* bitsize of |a|, b, p, n, --> sizeparam*8*4*2 (address and data); n length,
+ plength and a sign --> 64*3*2 (address and data) */
+
+ last_block[1] = (((operand_size * 32UL) * 4UL) + (3UL * 64UL)) * 2UL;
+
+ /* 1 ciphred data with 256 size*/
+ last_block[3] = cipherkey_size * 32UL;
+ }
+
+ for (count = 0; count < CCB_BLOCK_SIZE; count++)
+ {
+ SAES->DINR = last_block[count];
+ }
+
+ /* Wait until CCF flag is SET in SAES */
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Read Authentif Tag */
+ for (count = 0U; count < CCB_BLOCK_SIZE; count++)
+ {
+ pTag[count] = SAES->DOUTR;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Final phase processing when blob use
+ * @param hccb CCB handle
+ * @param Operation Operation
+ * @param sizeparam size of parameters
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CCB_BlobUse_FinalPhase(CCB_HandleTypeDef *hccb, uint32_t Operation, uint32_t sizeparam)
+{
+ uint32_t last_block[4] = {0};
+ uint16_t count;
+ uint32_t operand_size;
+ uint32_t cipherkey_size;
+
+ /* set operand size in 32bits */
+ operand_size = 2UL * ((uint32_t)(((sizeparam) + 7UL) / 8UL) + 1UL);
+ if ((operand_size % 4UL) != 0UL)
+ {
+ cipherkey_size = operand_size - 2UL;
+ }
+ else
+ {
+ cipherkey_size = operand_size;
+ }
+
+ /* Set SAES GCMPH final phase */
+ MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_0 | AES_CR_GCMPH_1);
+
+ /* Preparing last Block */
+ if (Operation == CCB_MODULAR_EXP_BLOB_USE)
+ {
+ /* bitsize of exp length, modulus n length and modulus (address and data)*/
+ last_block[1] = ((64UL * 2UL) + (operand_size * 32UL)) * 2UL;
+
+ /* ciphred data size*/
+ last_block[3] = cipherkey_size * 32UL;
+ }
+
+ else if (Operation == CCB_ECDSA_SIGN_BLOB_USE)
+ {
+ /* bitsize of |a|, b, p, n, Gx and Gy --> sizeparam*8*6*2 (address and data); n length,
+ plength and a sign --> 64*3*2 (address and data) */
+ last_block[1] = (((operand_size * 32UL) * 6UL) + (3UL * 64UL)) * 2UL;
+
+ /* 1 ciphred data with 256 size*/
+ last_block[3] = cipherkey_size * 32UL;
+ }
+ else
+ {
+ /* bitsize of |a|, b, p, n, --> sizeparam*8*4*2 (address and data); n length,
+ plength and a sign --> 64*3*2 (address and data) */
+
+ last_block[1] = (((operand_size * 32UL) * 4UL) + (3UL * 64UL)) * 2UL;
+
+ /* 1 ciphred data with 256 size*/
+ last_block[3] = cipherkey_size * 32UL;
+ }
+
+ for (count = 0U; count < CCB_BLOCK_SIZE; count++)
+ {
+ SAES->DINR = last_block[count];
+ }
+
+ /* Wait until CCF flag is SET in SAES */
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Read Authentif Tag and check integrity of Blob as event that trig OPSTEP transition 0x17 --> 0x18 */
+ for (count = 0U; count < CCB_BLOCK_SIZE; count++)
+ {
+ if ((SAES->DOUTR) != 0UL)
+ {
+ /* Set state, error code and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ hccb->ErrorCode = HAL_CCB_ERROR_OPERATION;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Blob Usage: ECDSA Signature Creation.
+ * @param hccb CCB handle.
+ * @param pCurveParam pointer to the Curve parameters.
+ * @param pClearPrivateKey pointer to the clear private key.
+ * @param pWrappingKey pointer to the Wrapping Key structure.
+ * @param pIV pointer to the IV.
+ * @param pTag pointer to the Tag.
+ * @param pWarappedKey pointer to the Warapped Key.
+ * @param CCB_Operation is the CCB Operations.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef CCB_ECDSA_SignBlobCreation(CCB_HandleTypeDef *hccb, CCB_ECDSACurveParamTypeDef *pCurveParam,
+ const uint8_t *pClearPrivateKey,
+ CCB_WrappingKeyTypeDef *pWrappingKey, uint32_t *pIV,
+ uint32_t *pTag, uint32_t *pWarappedKey, uint8_t CCB_Operation)
+{
+ uint16_t count;
+ uint32_t countBlock = 0UL;
+ uint32_t offset;
+ uint32_t operand_size;
+ uint32_t cipherkey_size;
+
+ /* Set Operation in CCB */
+ MODIFY_REG(CCB->CR, CCB_CR_CCOP, CCB_Operation);
+
+ /* Wait until OPSTEP is set to 0x01 */
+ if (CCB_WaitOperStep(hccb, 0x01, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Initialize RNG */
+ if (CCB_RNG_Init() != HAL_OK)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Initialize PKA */
+ if (Protect_PKA_Init(hccb, CCB_Operation) != HAL_OK)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Initialize SAES */
+ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* Disable the SAES peripheral clock */
+ SAES->CR &= ~AES_CR_EN;
+
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Update the state */
+ hccb->State = HAL_CCB_STATE_BUSY;
+
+ /* Wrapping Key configuration */
+ if (WrappingKeyConfiguration(hccb, CCB_Operation, pWrappingKey) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x02 */
+ if (CCB_WaitOperStep(hccb, 0x02, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Update the state */
+ hccb->State = HAL_CCB_STATE_BUSY;
+
+ /* set operand size (in word 32bits)*/
+
+ operand_size = 2UL * ((uint32_t)(((pCurveParam->modulusSizeByte) + 7UL) / 8UL) + 1UL);
+
+ if ((operand_size % 4UL) != 0UL)
+ {
+ cipherkey_size = operand_size - 2UL;
+ }
+ else
+ {
+ cipherkey_size = operand_size;
+ }
+ /* Initial Phase processing */
+ if (CCB_BlobCreation_InitialPhase(hccb, pIV) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x03 */
+ if (CCB_WaitOperStep(hccb, 0x03, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Set ECDSA parameters */
+ if (CCB_ECDSASign_SetPram(hccb, pCurveParam) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Set SAES GCMPH Payload phase and trig OPSTEP that trig OPSTEP transition 0x3 --> 0x4 */
+ MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_1);
+
+ if (CCB_Operation == CCB_ECDSA_SIGN_CPU_BLOB_CREATION)
+ {
+ /* Wait until OPSTEP is set to 0x04 */
+ if (CCB_WaitOperStep(hccb, 0x04, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */
+ HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC);
+
+ /* Write private Key d by CPU (user key) */
+ if ((pCurveParam->modulusSizeByte % 8UL) != 0UL)
+ {
+ for (offset = 0UL; offset < (operand_size - 4UL); offset += 2UL)
+ {
+ CCB_Memcpy_u8_to_u64(&PKA->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset],
+ &pClearPrivateKey[(pCurveParam->modulusSizeByte) - ((offset * 4UL) + 1UL)]);
+ }
+
+ CCB_Memcpy_Not_Align(&PKA->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset],
+ &pClearPrivateKey[(pCurveParam->modulusSizeByte) - ((offset * 4UL) + 1UL)],
+ pCurveParam->modulusSizeByte % 8UL);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset + 2UL);
+ }
+ else
+ {
+ for (offset = 0UL; offset < (operand_size - 2UL); offset += 2UL)
+ {
+ CCB_Memcpy_u8_to_u64(&PKA->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset],
+ &pClearPrivateKey[(pCurveParam->modulusSizeByte) - ((offset * 4UL) + 1UL)]);
+ }
+
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset);
+ }
+ /* Wait until DATAOKF flag is SET in PKA and trig OPSTEP transition 0x4 --> 0x8 */
+ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_DATAOKF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+ }
+ else if (CCB_Operation == CCB_ECDSA_SIGN_RNG_BLOB_CREATION)
+ {
+ /* Wait until OPSTEP is set to 0x6 */
+ if (CCB_WaitOperStep(hccb, 0x06, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */
+ HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC);
+
+ /* Write private d Key from RNG */
+
+ for (offset = 0UL; offset < (operand_size - 2UL); offset++)
+ {
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+ PKA->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset] = CCB_FAKE_VALUE;
+ }
+
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D
+ + offset);
+
+ /* Check RNG Error Flag in PKA */
+ if (HAL_CCB_GET_PKA_FLAG(PKA_SR_RNGERRF) != RESET)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Wait until RNGOKF flag is SET in PKA and trig OPSTEP transition 0x6 --> 0x8 */
+ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_RNGOKF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Nothing To Do */
+ }
+
+ /* Wait until OPSTEP is set to 0x08 */
+ if (CCB_WaitOperStep(hccb, 0x08, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */
+ HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC);
+
+ /* Read clear-text private key d for encryption */
+ for (offset = 0; offset < cipherkey_size; offset++)
+ {
+ PKA->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + offset] = CCB_MAGIC_VALUE;
+
+ if ((offset % 4UL) == 3UL)
+ {
+ /* Wait until CCF flag is SET in SAES*/
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Read ciphered private Key d */
+ for (count = 0U; count < CCB_BLOCK_SIZE; count++)
+ {
+ pWarappedKey[cipherkey_size - (countBlock + count + 1UL)]
+ = READ_REG(SAES->DOUTR);
+ }
+ countBlock += 4UL;
+ }
+ }
+
+ /* Wait for Galois Filter End of Computation */
+ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+ if ((operand_size % 4UL) != 0UL)
+ {
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D
+ + cipherkey_size);
+ }
+ /* Wait until DATAOKF flag is SET in PKA and trig OPSTEP transition 0x08 --> 0x09 */
+ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_DATAOKF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Set SAES GCMPH final phase */
+ MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_0 | AES_CR_GCMPH_1);
+
+ /* Wait until OPSTEP is set to 0x0A */
+ if (CCB_WaitOperStep(hccb, 0x0A, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Final phase processing */
+ if (CCB_BlobCreation_FinalPhase(hccb, CCB_Operation, pTag,
+ pCurveParam->modulusSizeByte) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+
+ /* CCB IPRST set */
+ SET_BIT(hccb->Instance->CR, CCB_CR_IPRST);
+
+ /* CCB is busy while CCB IPRST is in progress */
+ if (CCB_WaitFLAG(hccb, CCB_SR_BUSY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return timeout*/
+ return HAL_TIMEOUT;
+ }
+
+ /* clear CCB IPRST */
+ CLEAR_BIT(hccb->Instance->CR, CCB_CR_IPRST);
+
+ /* Update the CCB state */
+ hccb->State = HAL_CCB_STATE_READY;
+
+ /* Return HAL OK */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Blob Creation: ECC generate (by RNG) and wrap the private Key (no user input).
+ * @param hccb CCB handle.
+ * @param pCurveParam pointer to the Curve parameters.
+ * @param pClearPrivateKey pointer to the related wrapped Private Key Blob.
+ * @param pWrappingKey pointer to the Wrapping Key structure.
+ * @param WarappedKey pointer to the related wrapped Private Key Blob.
+ * @param CCB_Operation is the CCB Operations.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef CCB_ECC_ScalarMulBlobCreation(CCB_HandleTypeDef *hccb,
+ CCB_ECCMulCurveParamTypeDef *pCurveParam,
+ const uint8_t *pClearPrivateKey,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ uint32_t *IV, uint32_t *Tag, uint32_t *WarappedKey,
+ uint8_t CCB_Operation)
+{
+ uint16_t count;
+ uint32_t countBlock = 0UL;
+ uint32_t offset;
+ uint32_t operand_size;
+ uint32_t cipherkey_size;
+
+ if (hccb->State == HAL_CCB_STATE_READY)
+ {
+ /* Set Operation in CCB */
+ MODIFY_REG(CCB->CR, CCB_CR_CCOP, CCB_Operation);
+
+ /* Wait until OPSTEP is set to 0x01 */
+ if (CCB_WaitOperStep(hccb, 0x01, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Initialize RNG */
+ if (CCB_RNG_Init() != HAL_OK)
+ {
+ /* return state and error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Initialize PKA */
+ if (Protect_PKA_Init(hccb, CCB_Operation) != HAL_OK)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Initialize SAES */
+ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* Disable the SAES peripheral clock */
+ SAES->CR &= ~AES_CR_EN;
+
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Update the state */
+ hccb->State = HAL_CCB_STATE_BUSY;
+
+ /* Wrapping Key configuration */
+ if (WrappingKeyConfiguration(hccb, CCB_Operation, pWrappingKey) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x02 */
+ if (CCB_WaitOperStep(hccb, 0x02, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Update the state */
+ hccb->State = HAL_CCB_STATE_BUSY;
+
+ /* set operand size */
+ operand_size = 2UL * ((uint32_t)(((pCurveParam->primeOrderSizeByte) + 7UL) / 8UL) + 1UL);
+ if ((operand_size % 4UL) != 0UL)
+ {
+ cipherkey_size = operand_size - 2UL;
+ }
+ else
+ {
+ cipherkey_size = operand_size;
+ }
+
+ /* Initial Phase processing */
+ if (CCB_BlobCreation_InitialPhase(hccb, IV) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x03 */
+ if (CCB_WaitOperStep(hccb, 0x03, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Set ECC Scalar multiplications parameters */
+ if (CCB_ECCMul_SetPram(hccb, pCurveParam) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Set SAES GCMPH Payload phase and trig OPSTEP that trig OPSTEP transition 0x3 --> 0x4 */
+ MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_1);
+
+ /* Wait until OPSTEP is set to 0x04 */
+ if (CCB_WaitOperStep(hccb, 0x04, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */
+ HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC);
+
+ if (CCB_Operation == CCB_ECC_SCALAR_MUL_CPU_BLOB_CREATION)
+ {
+
+ /* Write clear scalar k by CPU */
+ if ((pCurveParam->modulusSizeByte % 8UL) != 0UL)
+ {
+ for (offset = 0UL; offset < (operand_size - 4UL); offset += 2UL)
+ {
+ CCB_Memcpy_u8_to_u64(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_K + offset],
+ &pClearPrivateKey[(pCurveParam->modulusSizeByte) - ((offset * 4UL) + 1UL)]);
+ }
+
+ CCB_Memcpy_Not_Align(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_K + offset],
+ &pClearPrivateKey[(pCurveParam->modulusSizeByte) - ((offset * 4UL) + 1UL)],
+ pCurveParam->modulusSizeByte % 8UL);
+ RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_K + offset + 2UL);
+ }
+ else
+ {
+ for (offset = 0UL; offset < (operand_size - 2UL); offset += 2UL)
+ {
+ CCB_Memcpy_u8_to_u64(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_K + offset],
+ &pClearPrivateKey[(pCurveParam->modulusSizeByte) - ((offset * 4UL) + 1UL)]);
+ }
+
+ RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_K + offset);
+ }
+ /* Wait until DATAOKF flag is SET in PKA and trig OPSTEP transition 0x4 --> 0x8 */
+ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_DATAOKF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+ }
+ else if (CCB_Operation == CCB_ECC_SCALAR_MUL_RNG_BLOB_CREATION)
+ {
+ /* Write scalar k when RNG */
+ for (offset = 0UL; offset < (operand_size - 2UL); offset++)
+ {
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+ PKA->RAM[PKA_ECC_SCALAR_MUL_IN_K + offset] = CCB_FAKE_VALUE;
+ }
+ RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_K + offset);
+
+ /* PKA: Check RNG Error Flag */
+ if (HAL_CCB_GET_PKA_FLAG(PKA_SR_RNGERRF) != RESET)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Wait until RNGOKF flag is SET in PKA and trig OPSTEP transition 0x6 --> 0x8 */
+ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_RNGOKF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Nothing To Do */
+ }
+
+ /* Wait until OPSTEP is set to 0x08 */
+ if (CCB_WaitOperStep(hccb, 0x08, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */
+ HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC);
+
+ /* Read clear-text scalar K for encryption */
+ for (offset = 0; offset < cipherkey_size; offset++)
+ {
+
+ PKA->RAM[PKA_ECC_SCALAR_MUL_IN_K + offset] = CCB_MAGIC_VALUE;
+
+ if ((offset % 4UL) == 3UL)
+ {
+ /* Wait until CCF flag is SET in SAES*/
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Read ciphered scalar k */
+ for (count = 0U; count < CCB_BLOCK_SIZE; count++)
+ {
+ WarappedKey[cipherkey_size - (countBlock + count + 1U)]
+ = READ_REG(SAES->DOUTR);
+ }
+ countBlock += 4UL;
+ }
+ }
+
+ /* Wait for Galois Filter End of Computation */
+ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ if ((operand_size % 4UL) != 0UL)
+ {
+ RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_K
+ + cipherkey_size);
+ }
+
+ /* Wait until DATAOKF flag is SET in PKA and trig OPSTEP transition 0x8 --> 0xA */
+ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_DATAOKF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Set SAES GCMPH final phase */
+ MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_0 | AES_CR_GCMPH_1);
+
+ /* Wait until OPSTEP is set to 0x0A */
+ if (CCB_WaitOperStep(hccb, 0x0A, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Final phase processing */
+ if (CCB_BlobCreation_FinalPhase(hccb, CCB_Operation, Tag,
+ pCurveParam->modulusSizeByte) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+
+ /* CCB IPRST set */
+ SET_BIT(hccb->Instance->CR, CCB_CR_IPRST);
+
+ /* CCB is busy while CCB IPRST is in progress */
+ if (CCB_WaitFLAG(hccb, CCB_SR_BUSY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* clear CCB IPRST */
+ CLEAR_BIT(hccb->Instance->CR, CCB_CR_IPRST);
+
+ /* Update the CCB state */
+ hccb->State = HAL_CCB_STATE_READY;
+ }
+
+ else
+ {
+ /* Set state, error code and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ hccb->ErrorCode = HAL_CCB_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Return HAL OK */
+ return HAL_OK;
+}
+
+/**
+ * @brief Blob Usage: ECC Compute Scalar Multiplication.
+ * @param hccb CCB handle.
+ * @param pCurveParam pointer to the Curve parameters.
+ * @param pWrappingKey pointer to the Wrapping Key structure.
+ * @param pIV pointer to the IV.
+ * @param pTag pointer to the Tag.
+ * @param pWarappedKey pointer to the Warapped Key.
+ * @param pInputPoint pointer to the input point structure.
+ * @param pOutputPoint pointer to the output point.
+ * @param pPublicKey pointer to the input public key for check.
+ * @param VerifOperation allows to compare the OutputPoint with the Publickey.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef CCB_ECC_ComputeScalarMul(CCB_HandleTypeDef *hccb, CCB_ECCMulCurveParamTypeDef *pCurveParam,
+ CCB_WrappingKeyTypeDef *pWrappingKey,
+ uint32_t *pIV, uint32_t *pTag, uint32_t *pWarappedKey,
+ CCB_ECCMulPointTypeDef *pInputPoint,
+ CCB_ECCMulPointTypeDef *pOutputPoint,
+ const uint32_t *pPublicKey,
+ uint8_t VerifOperation)
+{
+ __IO uint16_t f_count;
+ uint16_t random1 = 0;
+ uint16_t random2 = 0;
+ uint16_t random3 = 0;
+ uint16_t count_ram;
+ uint32_t count_block = 0UL;
+ uint32_t offset;
+ uint32_t operand_size;
+ uint32_t cipherkey_size;
+ uint32_t tickstart;
+
+ /* Set Operation in CCB */
+ MODIFY_REG(CCB->CR, CCB_CR_CCOP, CCB_ECC_SCALAR_MUL_BLOB_USE);
+
+ /* Wait until OPSTEP is set to 0x01 */
+ if (CCB_WaitOperStep(hccb, 0x01, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Initialize RNG */
+ if (CCB_RNG_Init() != HAL_OK)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ tickstart = HAL_GetTick();
+
+ while (random1 == 0U)
+ {
+ random1 = (uint16_t)(RNG->DR & 0x3FFU);
+ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE)
+ {
+ /* Set state and return error */
+ return HAL_ERROR;
+ }
+ }
+
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ tickstart = HAL_GetTick();
+
+ while (random2 == 0U)
+ {
+ random2 = (uint16_t)(RNG->DR & 0x3FFU);
+ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE)
+ {
+ /* Set state and return error */
+ return HAL_ERROR;
+ }
+ }
+
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ tickstart = HAL_GetTick();
+
+ while (random3 == 0U)
+ {
+ random3 = (uint16_t)(RNG->DR & 0x3FFU);
+ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE)
+ {
+ /* Set state and return error */
+ return HAL_ERROR;
+ }
+ }
+
+ /* Initialize PKA */
+ if (Protect_PKA_Init(hccb, CCB_ECC_SCALAR_MUL_BLOB_USE) != HAL_OK)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+
+ if (VerifOperation == CCB_VERIF_OPERATION_DISABLED)
+ {
+ /* Write Customized point coordinate */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ], pInputPoint->pPointX,
+ pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ], pInputPoint->pPointY,
+ pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+ }
+ else if (VerifOperation == CCB_VERIF_OPERATION_ENABLED)
+ {
+ /* Write point G coordinate */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ], pCurveParam->pPointX,
+ pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ], pCurveParam->pPointY,
+ pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ /* Initialize SAES */
+ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* Disable the SAES peripheral */
+ SAES->CR &= ~AES_CR_EN;
+
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Update the state */
+ hccb->State = HAL_CCB_STATE_BUSY;
+
+ /* Wrapping Key configuration */
+ if (WrappingKeyConfiguration(hccb, CCB_ECC_SCALAR_MUL_BLOB_USE, pWrappingKey) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x012 */
+ if (CCB_WaitOperStep(hccb, 0x012, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Update the state */
+ hccb->State = HAL_CCB_STATE_BUSY;
+
+ /* set 32bits word number and operand size*/
+
+ operand_size = 2UL * ((uint32_t)(((pCurveParam->primeOrderSizeByte) + 7UL) / 8UL) + 1UL);
+
+ if ((operand_size % 4UL) != 0UL)
+ {
+ cipherkey_size = operand_size - 2UL;
+ }
+ else
+ {
+ cipherkey_size = operand_size;
+ }
+
+ /* Initial Phase Processing */
+ if (CCB_BlobUse_InitialPhase(hccb, pIV, pTag) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x13 */
+ if (CCB_WaitOperStep(hccb, 0x13, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+ if (VerifOperation == CCB_COMPUTE_PUBLIC_KEY)
+ {
+ /* Set parameters */
+ if (CCB_ECDSASign_SetPram(hccb, pCurveParam) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Set parameters */
+ if (CCB_ECCMul_SetPram(hccb, pCurveParam) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+ }
+
+ /* Set SAES GCMPH Payload phase and trig OPSTEP that trig OPSTEP transition 0x13 --> 0x14 */
+ MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_1);
+
+ /* Wait until OPSTEP is set to 0x14 */
+ if (CCB_WaitOperStep(hccb, 0x14, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ for (offset = 0UL; offset < cipherkey_size; offset++)
+ {
+ /* Write Wrapped scalar k in PKA RAM */
+ WRITE_REG(SAES->DINR, pWarappedKey[cipherkey_size - (offset + 1UL)]);
+
+ if ((offset % 4UL) == 0x3UL)
+ {
+ /* Wait until CCF flag is SET in SAES */
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Write Unrapped scalar k in PKA RAM */
+ for (count_ram = 0U; count_ram < 4U; count_ram++)
+ {
+ PKA->RAM[PKA_ECDSA_SIGN_IN_K + (count_block + count_ram)] = CCB_MAGIC_VALUE;
+ }
+ count_block += 4UL;
+ }
+ }
+ if ((operand_size % 4UL) != 0UL)
+ {
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_K
+ + cipherkey_size);
+ }
+
+ /* Wait until OPSTEP is set to 0x17 */
+ if (CCB_WaitOperStep(hccb, 0x17, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+ if (VerifOperation == CCB_COMPUTE_PUBLIC_KEY)
+ {
+ /* Final phase processing */
+ if (CCB_BlobUse_FinalPhase(hccb, CCB_ECDSA_SIGN_BLOB_USE, pCurveParam->modulusSizeByte) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Final phase processing */
+ if (CCB_BlobUse_FinalPhase(hccb, CCB_ECC_SCALAR_MUL_BLOB_USE, pCurveParam->modulusSizeByte) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+ }
+
+ /* Wait until OPSTEP is set to 0x18 */
+ if (CCB_WaitOperStep(hccb, 0x18, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* SET PKA START operation bit and trig OPSTEP transition 0x18 --> 0x19 */
+ SET_BIT(PKA->CR, PKA_CR_START);
+
+ /* Wait until OPSTEP is set to 0x19 */
+ if (CCB_WaitOperStep(hccb, 0x19, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until end of operation flag is SET in PKA and trig OPSTEP transition 0x19 --> 0x1A */
+ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_PROCENDF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x1A */
+ if (CCB_WaitOperStep(hccb, 0x1A, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Check PKA Operation error result */
+ if ((PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_ERROR]) != CCB_PKA_ERROR_OPERATION_NONE)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ if (VerifOperation == CCB_VERIF_OPERATION_DISABLED)
+ {
+ /* P coordinate x */
+ CCB_Memcpy_u32_to_u8(pOutputPoint->pPointX, &PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X],
+ pCurveParam->modulusSizeByte);
+
+ /* P coordinate y */
+ CCB_Memcpy_u32_to_u8(pOutputPoint->pPointY, &PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y],
+ pCurveParam->modulusSizeByte);
+ }
+ else if (VerifOperation == CCB_COMPUTE_PUBLIC_KEY)
+ {
+ /* P coordinate x */
+ CCB_Memcpy_u32_to_u8(pOutputPoint->pPointX, &PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X],
+ pCurveParam->modulusSizeByte);
+
+ /* P coordinate y */
+ CCB_Memcpy_u32_to_u8(pOutputPoint->pPointY, &PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y],
+ pCurveParam->modulusSizeByte);
+ }
+ else /* (VerifOperation == CCB_VERIF_OPERATION_ENABLED) */
+ {
+ f_count = 0;
+ while (f_count < random1)
+ {
+ f_count++;
+ }
+
+ /* P coordinate x */
+ for (offset = 0UL; offset < ((pCurveParam->modulusSizeByte + 3UL) / 4UL); offset++)
+ {
+ /* Check public key coordinate x and improve robustness against intrusion (intentional) */
+ if (((PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + offset] != pPublicKey[offset]) ||
+ (f_count != random1) || (f_count == 0U)))
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+ }
+
+ /* P coordinate y */
+
+ for (offset = 0UL; offset < ((pCurveParam->modulusSizeByte + 3UL) / 4UL); offset++)
+ {
+ /* Check public key coordinate y and improve robustness against intrusion (intentional) */
+ if (((PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + offset] != pPublicKey[offset + 20U]) ||
+ (f_count != random1) || (f_count == 0U)))
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+ }
+
+ f_count = 0;
+ while (f_count < random2)
+ {
+ f_count++;
+ }
+
+ /* P coordinate x */
+ for (offset = 0UL; offset < ((pCurveParam->modulusSizeByte + 3UL) / 4UL); offset++)
+ {
+ /* Check public key coordinate x and improve robustness against intrusion (intentional) */
+ if (((PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + offset] != pPublicKey[offset]) ||
+ (f_count != random2) || (f_count == 0U)))
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+ }
+
+ /* P coordinate y */
+
+ for (offset = 0UL; offset < ((pCurveParam->modulusSizeByte + 3UL) / 4UL); offset++)
+ {
+ /* Check public key coordinate y and improve robustness against intrusion (intentional) */
+ if (((PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + offset] != pPublicKey[offset + 20U]) ||
+ (f_count != random2) || (f_count == 0U)))
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+ }
+
+ f_count = 0;
+ while (f_count < random3)
+ {
+ f_count++;
+ }
+
+ /* P coordinate x */
+ for (offset = 0UL; offset < ((pCurveParam->modulusSizeByte + 3UL) / 4UL); offset++)
+ {
+ /* Check public key coordinate x and improve robustness against intrusion (intentional) */
+ if (((PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X + offset] != pPublicKey[offset]) ||
+ (f_count != random3) || (f_count == 0U)))
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+ }
+
+ /* P coordinate y */
+
+ for (offset = 0UL; offset < ((pCurveParam->modulusSizeByte + 3UL) / 4UL); offset++)
+ {
+ /* Check public key coordinate y and improve robustness against intrusion (intentional) */
+ if (((PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y + offset] != pPublicKey[offset + 20U]) ||
+ (f_count != random3) || (f_count == 0U)))
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+ }
+ }
+
+ /* CCB IPRST set */
+ SET_BIT(hccb->Instance->CR, CCB_CR_IPRST);
+
+ /* CCB is busy while CCB IPRST is in progress */
+ if (CCB_WaitFLAG(hccb, CCB_SR_BUSY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* clear CCB IPRST */
+ CLEAR_BIT(hccb->Instance->CR, CCB_CR_IPRST);
+
+ /* Update the CCB state */
+ hccb->State = HAL_CCB_STATE_READY;
+
+ /* Return HAL OK */
+ return HAL_OK;
+}
+
+/**
+ * @brief Blob Creation: RSA Wrap the private Key (input from user).
+ * @param hccb CCB handle.
+ * @param pParam pointer to the modular exponatiation parameters.
+ * @param pRSAClearPrivateKey pointer to the clear Private Key.
+ * @param pWrappingKey pointer to the Wrapping Key structure.
+ * @param pWrappedExp pointer to the related wrapped Private Key Blob.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef CCB_RSA_ExpBlobCreation(CCB_HandleTypeDef *hccb, CCB_RSAParamTypeDef *pParam,
+ const CCB_RSAClearKeyTypeDef *pRSAClearPrivateKey,
+ CCB_WrappingKeyTypeDef *pWrappingKey, uint32_t *pIV,
+ uint32_t *pTag, uint32_t *pWrappedExp, uint32_t *pWrappedPhi)
+{
+ uint16_t count;
+ uint32_t countBlock = 0UL;
+ uint32_t offset;
+ uint32_t operand_size;
+ uint32_t cipherkey_size;
+
+ /* Set Operation in CCB */
+ MODIFY_REG(CCB->CR, CCB_CR_CCOP, CCB_MODULAR_EXP_CPU_BLOB_CREATION);
+
+ /* Wait until OPSTEP is set to 0x01 */
+ if (CCB_WaitOperStep(hccb, 0x01, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Initialize RNG */
+ if (CCB_RNG_Init() != HAL_OK)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Initialize PKA */
+ if (Protect_PKA_Init(hccb, CCB_MODULAR_EXP_CPU_BLOB_CREATION) != HAL_OK)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Initialize SAES */
+ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* Disable the SAES peripheral clock */
+ SAES->CR &= ~AES_CR_EN;
+
+ /* Set state, error code and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Update the state */
+ hccb->State = HAL_CCB_STATE_BUSY;
+
+ /* Wrapping Key configuration */
+ if (WrappingKeyConfiguration(hccb, CCB_MODULAR_EXP_CPU_BLOB_CREATION, pWrappingKey) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x02 */
+ if (CCB_WaitOperStep(hccb, 0x02, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Update the state */
+ hccb->State = HAL_CCB_STATE_BUSY;
+
+ /* set operand size */
+ operand_size = 2UL * ((uint32_t)(((pParam->modulusSizeByte) + 7UL) / 8UL) + 1UL);
+ if ((operand_size % 4UL) != 0UL)
+ {
+ cipherkey_size = operand_size - 2UL;
+ }
+ else
+ {
+ cipherkey_size = operand_size;
+ }
+
+ /* Initial Phase processing */
+ if (CCB_BlobCreation_InitialPhase(hccb, pIV) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x03 */
+ if (CCB_WaitOperStep(hccb, 0x03, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Set RSA Modular Exponentiation parameters */
+ if (CCB_RSAModExp_SetPram(hccb, pParam) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Set SAES GCMPH Payload phase and trig OPSTEP that trig OPSTEP transition 0x3 --> 0x4 */
+ MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_1);
+
+ /* Wait until OPSTEP is set to 0x04 */
+ if (CCB_WaitOperStep(hccb, 0x04, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */
+ HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC);
+
+ /* Write clear-text exponent e */
+ if ((pParam->modulusSizeByte % 8UL) != 0UL)
+ {
+ for (offset = 0UL; offset < (operand_size - 4UL); offset += 2UL)
+ {
+ CCB_Memcpy_u8_to_u64(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + offset],
+ &pRSAClearPrivateKey->pExp[(pParam->modulusSizeByte) - ((offset * 4UL) + 1UL)]);
+ }
+
+ CCB_Memcpy_Not_Align(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + offset],
+ &pRSAClearPrivateKey->pExp[(pParam->modulusSizeByte) - ((offset * 4UL) + 1UL)],
+ pParam->modulusSizeByte % 8UL);
+ RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + offset + 2UL);
+ }
+ else
+ {
+ for (offset = 0; offset < (operand_size - 2UL); offset += 2UL)
+ {
+ CCB_Memcpy_u8_to_u64(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + offset],
+ &pRSAClearPrivateKey->pExp[(pParam->modulusSizeByte) - ((offset * 4UL) + 1UL)]);
+ }
+
+ RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT
+ + offset);
+ }
+
+
+ /* Wait until DATAOKF flag is SET in PKA and trig OPSTEP transition 0x4 --> 0x5 */
+ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_DATAOKF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x05 */
+ if (CCB_WaitOperStep(hccb, 0x05, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */
+ HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC);
+
+ /* Write clear-text phi */
+ if ((pParam->modulusSizeByte % 8UL) != 0UL)
+ {
+ for (offset = 0; offset < (operand_size - 4UL); offset += 2UL)
+ {
+ CCB_Memcpy_u8_to_u64(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI + offset],
+ &pRSAClearPrivateKey->pPhi[(pParam->modulusSizeByte) - ((offset * 4UL) + 1UL)]);
+ }
+
+ CCB_Memcpy_Not_Align(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI + offset],
+ &pRSAClearPrivateKey->pPhi[(pParam->modulusSizeByte) - ((offset * 4UL) + 1UL)],
+ pParam->modulusSizeByte % 8UL);
+ RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + offset + 2UL);
+ }
+ else
+ {
+ for (offset = 0; offset < (operand_size - 2UL); offset += 2UL)
+ {
+ CCB_Memcpy_u8_to_u64(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI + offset],
+ &pRSAClearPrivateKey->pPhi[(pParam->modulusSizeByte) - ((offset * 4UL) + 1UL)]);
+ }
+
+ RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + offset);
+ }
+
+ /* Wait until DATAOKF flag is SET in PKA and trig OPSTEP transition 0x5 --> 0x8: */
+ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_DATAOKF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x08 */
+ if (CCB_WaitOperStep(hccb, 0x08, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */
+ HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC);
+
+ /* Read clear exponent e for encryption */
+ for (offset = 0UL; offset < cipherkey_size; offset++)
+ {
+
+ PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + offset] = CCB_MAGIC_VALUE;
+
+ if ((offset % 4UL) == 3UL)
+ {
+ /* Wait until CCF flag is SET in SAES*/
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Read ciphered exponent e */
+ for (count = 0U; count < CCB_BLOCK_SIZE; count++)
+ {
+ pWrappedExp[cipherkey_size - (countBlock + count + 1UL)]
+ = READ_REG(SAES->DOUTR);
+ }
+ countBlock += 4UL;
+ }
+ }
+
+ /* Wait for Galois Filter End of Computation */
+ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ if ((operand_size % 4UL) != 0UL)
+ {
+ RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT
+ + cipherkey_size);
+ }
+
+ /* Wait until DATAOKF flag is SET in PKA and trig OPSTEP transition 0x8 --> 0x9 */
+ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_DATAOKF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x09 */
+ if (CCB_WaitOperStep(hccb, 0x09, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */
+ HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC);
+
+ countBlock = 0U;
+
+ /* Read clear phi for encryption */
+ for (offset = 0; offset < cipherkey_size; offset++)
+ {
+
+ PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI + offset] = CCB_MAGIC_VALUE;
+
+ if ((offset % 4UL) == 3UL)
+ {
+ /* Wait until CCF flag is SET in SAES*/
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Read ciphered phi */
+ for (count = 0U; count < CCB_BLOCK_SIZE; count++)
+ {
+ pWrappedPhi[cipherkey_size - (countBlock + count + 1UL)]
+ = READ_REG(SAES->DOUTR);
+ }
+ countBlock += 4UL;
+ }
+ }
+
+ /* Wait for Galois Filter End of Computation */
+ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ if ((operand_size % 4UL) != 0UL)
+ {
+ RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI
+ + cipherkey_size);
+ }
+
+ /* Wait until DATAOKF flag is SET in PKA and trig OPSTEP transition 0x9 --> 0xA */
+ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_DATAOKF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Set SAES GCMPH final phase */
+ MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_0 | AES_CR_GCMPH_1);
+
+ /* Wait until OPSTEP is set to 0x0A */
+ if (CCB_WaitOperStep(hccb, 0x0A, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Final phase processing */
+ if (CCB_BlobCreation_FinalPhase(hccb, CCB_MODULAR_EXP_CPU_BLOB_CREATION, pTag,
+ pParam->modulusSizeByte) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* CCB IPRST set */
+ SET_BIT(hccb->Instance->CR, CCB_CR_IPRST);
+
+ /* CCB is busy while CCB IPRST is in progress */
+ if (CCB_WaitFLAG(hccb, CCB_SR_BUSY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* clear CCB IPRST */
+ CLEAR_BIT(hccb->Instance->CR, CCB_CR_IPRST);
+
+ /* Update the CCB state */
+ hccb->State = HAL_CCB_STATE_READY;
+
+ /* Return HAL OK */
+ return HAL_OK;
+}
+
+/**
+ * @brief Blob Usage: RSA Compute Modular exponentiation.
+ * @param hccb CCB handle.
+ * @param pParam pointer to the modular exponatiation parameters.
+ * @param pWrappingKey pointer to the Wrapping Key structure.
+ * @param pOperand pointer to the operand.
+ * @param pWrappedExp pointer to the related wrapped Private Key Blob.
+ * @param pModularExp pointer to the output operation.
+ * @param pReferenceModularExp pointer to the ReferenceModularExp computed in modular exponentiation Blob creation
+ * @param VerifOperation pointer to the VerifOperation.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef CCB_RSA_ComputeModularExp(CCB_HandleTypeDef *hccb, CCB_RSAParamTypeDef *pParam,
+ CCB_WrappingKeyTypeDef *pWrappingKey, uint32_t *pIV,
+ uint32_t *pTag, uint32_t *pWrappedExp, uint32_t *pWrappedPhi,
+ const uint8_t *pOperand, uint8_t *pModularExp,
+ const uint32_t *pReferenceModularExp, uint8_t VerifOperation)
+{
+ __IO uint16_t f_count;
+ uint16_t random1 = 0;
+ uint16_t random2 = 0;
+ uint16_t random3 = 0;
+ uint16_t count_ram;
+ uint32_t count_block = 0UL;
+ uint32_t offset;
+ uint32_t operand_size;
+ uint32_t cipherkey_size;
+ uint32_t tickstart;
+
+ /* Set Operation in CCB */
+ MODIFY_REG(CCB->CR, CCB_CR_CCOP, CCB_MODULAR_EXP_BLOB_USE);
+
+ /* Wait until OPSTEP is set to 0x01 */
+ if (CCB_WaitOperStep(hccb, 0x01, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Initialize RNG */
+ if (CCB_RNG_Init() != HAL_OK)
+ {
+ /* Set State and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ tickstart = HAL_GetTick();
+
+ while (random1 == 0U)
+ {
+ random1 = (uint16_t)(RNG->DR & 0x3FFU);
+ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE)
+ {
+ /* Set state and return error */
+ return HAL_ERROR;
+ }
+ }
+
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ tickstart = HAL_GetTick();
+
+ while (random2 == 0U)
+ {
+ random2 = (uint16_t)(RNG->DR & 0x3FFU);
+ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE)
+ {
+ /* Set state and return error */
+ return HAL_ERROR;
+ }
+ }
+
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ tickstart = HAL_GetTick();
+
+ while (random3 == 0U)
+ {
+ random3 = (uint16_t)(RNG->DR & 0x3FFU);
+ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE)
+ {
+ /* Set state and return error */
+ return HAL_ERROR;
+ }
+ }
+
+ /* Initialize PKA */
+ if (Protect_PKA_Init(hccb, CCB_MODULAR_EXP_BLOB_USE) != HAL_OK)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Initialize SAES */
+ if (Protect_SAES_WaitFLAG(hccb, AES_SR_BUSY, RESET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* Disable the SAES peripheral */
+ SAES->CR &= ~AES_CR_EN;
+
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Update the state */
+ hccb->State = HAL_CCB_STATE_BUSY;
+
+ /* Wrapping Key configuration */
+ if (WrappingKeyConfiguration(hccb, CCB_MODULAR_EXP_BLOB_USE, pWrappingKey) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x012 */
+ if (CCB_WaitOperStep(hccb, 0x012, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Update the state */
+ hccb->State = HAL_CCB_STATE_BUSY;
+
+ /* set 32bits word number of encrypted exponent e and encrypted phi*/
+ /* set operand size */
+
+ operand_size = 2UL * ((uint32_t)(((pParam->modulusSizeByte) + 7UL) / 8UL) + 1UL);
+ if ((operand_size % 4UL) != 0UL)
+ {
+ cipherkey_size = operand_size - 2UL;
+ }
+
+ else
+ {
+ cipherkey_size = operand_size;
+ }
+
+ /* Set Operand A - base of exponentiation */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ], pOperand, pParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE + ((pParam->modulusSizeByte + 3UL)));
+
+ /* Initial Phase Processing */
+ if (CCB_BlobUse_InitialPhase(hccb, pIV, pTag) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x13 */
+ if (CCB_WaitOperStep(hccb, 0x13, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Set RSA Modular Exponentiation parameters */
+ if (CCB_RSAModExp_SetPram(hccb, pParam) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Set SAES GCMPH Payload phase and trig OPSTEP that trig OPSTEP transition 0x13 --> 0x14 */
+ MODIFY_REG(SAES->CR, AES_CR_GCMPH, AES_CR_GCMPH_1);
+
+ /* Wait until OPSTEP is set to 0x14 */
+ if (CCB_WaitOperStep(hccb, 0x14, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Write encrypted exponent e in DINR of SAES */
+ for (offset = 0UL; offset < cipherkey_size; offset++)
+ {
+ WRITE_REG(SAES->DINR, pWrappedExp[cipherkey_size - (offset + 1U)]);
+
+ if ((offset % 4UL) == 0x3UL)
+ {
+ /* Wait until CCF flag is SET in SAES */
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Write key in PKA RAM */
+ for (count_ram = 0U; count_ram < 4U; count_ram++)
+ {
+ PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + (count_block + count_ram)] = CCB_MAGIC_VALUE;
+ }
+ count_block += 4UL;
+ }
+ }
+
+ if ((operand_size % 4UL) != 0UL)
+ {
+ RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + cipherkey_size);
+ }
+
+ /* Wait until DATAOKF flag is SET in PKA and trig OPSTEP transition 0x14 --> 0x15 */
+ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_DATAOKF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ if (CCB_WaitOperStep(hccb, 0x15, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Clear the CMF flag and the chaining mode status bits in 8 to 15 in PKA_SR */
+ HAL_CCB_CLEAR_PKA_FLAG(PKA_CLRFR_CMFC);
+
+ count_block = 0UL;
+ /* Write encrypted phi in DINR of SAES */
+
+ for (offset = 0UL; offset < cipherkey_size; offset++)
+ {
+ WRITE_REG(SAES->DINR, pWrappedPhi[cipherkey_size - (offset + 1UL)]);
+
+ if ((offset % 4UL) == 0x3UL)
+ {
+ /* Wait until CCF flag is SET in SAES */
+ if (Protect_SAES_WaitFLAG(hccb, AES_ISR_CCF, SET, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Write key in PKA RAM */
+ for (count_ram = 0U; count_ram < 4U; count_ram++)
+ {
+ PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI + (count_block + count_ram)] = CCB_MAGIC_VALUE;
+ }
+ count_block += 4UL;
+ }
+ }
+
+ if ((operand_size % 4UL) != 0UL)
+ {
+ RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + cipherkey_size);
+ }
+
+ /* Wait until DATAOKF flag is SET in PKA and trig OPSTEP transition 0x15 --> 0x17 */
+ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_DATAOKF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x17 */
+ if (CCB_WaitOperStep(hccb, 0x17, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Final phase processing */
+ if (CCB_BlobUse_FinalPhase(hccb, CCB_MODULAR_EXP_BLOB_USE, pParam->modulusSizeByte) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x18 */
+ if (CCB_WaitOperStep(hccb, 0x18, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* SET PKA START operation bit and trig OPSTEP transition 0x18 --> 0x19 */
+ SET_BIT(PKA->CR, PKA_CR_START);
+
+ /* Wait until OPSTEP is set to 0x19 */
+ if (CCB_WaitOperStep(hccb, 0x19, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until end of operation flag is SET in PKA and trig OPSTEP transition 0x19 --> 0x1A */
+ if (Protect_PKA_WaitFLAG(hccb, PKA_SR_PROCENDF, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Wait until OPSTEP is set to 0x1A */
+ if (CCB_WaitOperStep(hccb, 0x1A, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ /* Check PKA Operation error result */
+ if ((PKA->RAM[PKA_MODULAR_EXP_OUT_ERROR]) != CCB_PKA_ERROR_OPERATION_NONE)
+ {
+ /* Set state and return error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ if (VerifOperation == CCB_VERIF_OPERATION_DISABLED)
+ {
+ /* Read result output */
+ CCB_Memcpy_u32_to_u8(pModularExp, &PKA->RAM[PKA_MODULAR_EXP_OUT_RESULT], pParam->modulusSizeByte);
+ }
+ else /* CCB_VERIF_OPERATION_ENABLED */
+ {
+ f_count = 0;
+ while (f_count < random1)
+ {
+ f_count++;
+ }
+
+ for (offset = 0UL; offset < ((pParam->modulusSizeByte + 3UL) / 4UL); offset++)
+ {
+ /* Check Modular Exponentiation and improve robustness against intrusion (intentional) */
+ if (((PKA->RAM[PKA_MODULAR_EXP_OUT_RESULT + offset] != pReferenceModularExp[offset]) || (f_count != random1) ||
+ (f_count == 0U)))
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+
+ }
+
+ f_count = 0;
+ while (f_count < random2)
+ {
+ f_count++;
+ }
+
+ for (offset = 0UL; offset < ((pParam->modulusSizeByte + 3UL) / 4UL); offset++)
+ {
+ /* Check Modular Exponentiation and improve robustness against intrusion (intentional) */
+ if (((PKA->RAM[PKA_MODULAR_EXP_OUT_RESULT + offset] != pReferenceModularExp[offset]) || (f_count != random2) ||
+ (f_count == 0U)))
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+ }
+
+ f_count = 0;
+ while (f_count < random3)
+ {
+ f_count++;
+ }
+
+ for (offset = 0UL; offset < ((pParam->modulusSizeByte + 3UL) / 4UL); offset++)
+ {
+ /* Check Modular Exponentiation and improve robustness against intrusion (intentional) */
+ if (((PKA->RAM[PKA_MODULAR_EXP_OUT_RESULT + offset] != pReferenceModularExp[offset]) || (f_count != random3) ||
+ (f_count == 0U)))
+ {
+ /* Set state, and intrusion error */
+ hccb->State = HAL_CCB_STATE_ERROR;
+ HAL_CCB_IntrusionCallback(hccb);
+ }
+ }
+ }
+
+ /* CCB IPRST set */
+ SET_BIT(hccb->Instance->CR, CCB_CR_IPRST);
+
+ /* CCB is busy while CCB IPRST is in progress */
+ if (CCB_WaitFLAG(hccb, CCB_SR_BUSY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* clear CCB IPRST */
+ CLEAR_BIT(hccb->Instance->CR, CCB_CR_IPRST);
+
+ /* Update the CCB state */
+ hccb->State = HAL_CCB_STATE_READY;
+
+ /* Return HAL OK */
+ return HAL_OK;
+}
+
+/**
+ * @brief Erase the PKA RAM.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef PKA_RAM_Erase(void)
+{
+ uint32_t index;
+ __IO uint8_t random_nbr = 0U;
+ uint32_t tickstart;
+
+ PKA->RAM[CCB_PKA_RAM_SIZE - 1U] = CCB_MAGIC_VALUE;
+
+ /* For each element in the PKA RAM */
+ for (index = 0; index < CCB_PKA_RAM_SIZE; index++)
+ {
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Clear the content */
+ PKA->RAM[index] = RNG->DR;
+ }
+
+ if (PKA->RAM[CCB_PKA_RAM_SIZE - 1U] == CCB_MAGIC_VALUE)
+ {
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ tickstart = HAL_GetTick();
+
+ while (random_nbr == 0U)
+ {
+ random_nbr = (uint8_t)(RNG->DR & 0xFFU);
+ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE)
+ {
+ /* Set state and return error */
+ return HAL_ERROR;
+ }
+ }
+
+ while (random_nbr != 0UL)
+ {
+ random_nbr--;
+ }
+
+ /* For each element in the PKA RAM */
+ for (index = 0; index < CCB_PKA_RAM_SIZE; index++)
+ {
+ if (CCB_RNG_Wait_SET_FLAG(RNG_SR_DRDY, HAL_CCB_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Clear the content */
+ PKA->RAM[index] = RNG->DR;
+ }
+
+ if (PKA->RAM[CCB_PKA_RAM_SIZE - 1U] == CCB_MAGIC_VALUE)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Return HAL OK */
+ return HAL_OK;
+
+}
+
+/**
+ * @brief CCB PKA ECDSA Signature.
+ * @param pCurveParam pointer to the Curve parameters.
+ * @param pClearPrivateKey pointer to the clear private key.
+ * @param pInteger pointer to the integer k.
+ * @param pHash pointer to the input hash.
+ * @param pSignature Pointer to output signature
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef PKA_ECDSASign(CCB_ECDSACurveParamTypeDef *pCurveParam,
+ const uint8_t *pClearPrivateKey, uint8_t *pInteger, uint8_t *pHash,
+ CCB_ECDSASignTypeDef *pSignature)
+{
+ uint32_t tickstart;
+ uint32_t timeout = HAL_CCB_TIMEOUT_DEFAULT_VALUE;
+
+ /* Get the prime order n length */
+ PKA->RAM[PKA_ECDSA_SIGN_IN_ORDER_NB_BITS] = GetOptBitSize_u8(pCurveParam->primeOrderSizeByte,
+ *(pCurveParam->pPrimeOrder));
+
+ /* Get the modulus p length */
+ PKA->RAM[PKA_ECDSA_SIGN_IN_MOD_NB_BITS] = GetOptBitSize_u8(pCurveParam->modulusSizeByte, *(pCurveParam->pModulus));
+
+ /* Get the coefficient a sign */
+ PKA->RAM[PKA_ECDSA_SIGN_IN_A_COEFF_SIGN] = pCurveParam->coefSignA;
+
+ /* Move the input parameters coefficient |a| to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_A_COEFF], pCurveParam->pAbsCoefA, pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_A_COEFF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters coefficient B to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_B_COEFF], pCurveParam->pCoefB, pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_B_COEFF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters modulus value p to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_MOD_GF], pCurveParam->pModulus, pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_MOD_GF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters integer k to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_K], pInteger, pCurveParam->primeOrderSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_K + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters base point G coordinate x to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_X], pCurveParam->pPointX,
+ pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_INITIAL_POINT_X + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters base point G coordinate y to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y], pCurveParam->pPointY,
+ pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters hash of message z to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_HASH_E], pHash, pCurveParam->primeOrderSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_HASH_E + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters private key d to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D], pClearPrivateKey, pCurveParam->primeOrderSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters prime order n to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_SIGN_IN_ORDER_N], pCurveParam->pPrimeOrder,
+ pCurveParam->primeOrderSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_SIGN_IN_ORDER_N + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL));
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* Set the mode and deactivate the interrupts */
+ MODIFY_REG(PKA->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE,
+ CCB_PKA_ECDSA_SIGNATURE_MODE << PKA_CR_MODE_Pos);
+
+ /* Start the computation */
+ PKA->CR |= PKA_CR_START;
+
+ /* Wait for the end of operation or timeout */
+ while ((PKA->SR & PKA_SR_PROCENDF) == 0UL)
+ {
+ if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0UL))
+ {
+ /* Abort any ongoing operation */
+ CLEAR_BIT(PKA->CR, PKA_CR_EN);
+ /* Make ready for the next operation */
+ SET_BIT(PKA->CR, PKA_CR_EN);
+
+ return HAL_TIMEOUT;
+ }
+
+ }
+
+ /* Clear all flags */
+ PKA->CLRFR |= (PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC);
+
+ CCB_Memcpy_u32_to_u8(pSignature->pRSign, &PKA->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], pCurveParam->primeOrderSizeByte);
+ CCB_Memcpy_u32_to_u8(pSignature->pSSign, &PKA->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], pCurveParam->primeOrderSizeByte);
+
+ if (PKA_RAM_Erase() != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Blob Usage: ECC Compute Scalar Multiplication.
+ * @param pCurveParam pointer to the Curve parameters.
+ * @param pClearPrivateKey pointer to the related wrapped Private Key Blob.
+ * @param PublicKey is table of two coordinates X and Y of the publicKey.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef PKA_ECC_ComputeScalarMul(CCB_ECCMulCurveParamTypeDef *pCurveParam,
+ const uint8_t *pClearPrivateKey, uint32_t PublicKey[2][20])
+{
+ uint32_t tickstart;
+ uint32_t timeout = HAL_CCB_TIMEOUT_DEFAULT_VALUE;
+
+ /*********************************************************************************** Set input parameter in PKA RAM */
+ /* Get the prime order n length */
+ PKA->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] = GetOptBitSize_u8(pCurveParam->primeOrderSizeByte,
+ *(pCurveParam->pPrimeOrder));
+
+ /* Get the modulus length */
+ PKA->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = GetOptBitSize_u8(pCurveParam->modulusSizeByte,
+ *(pCurveParam->pModulus));
+
+ /* Get the coefficient a sign */
+ PKA->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = pCurveParam->coefSignA;
+
+ /* Move the input parameters coefficient |a| to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], pCurveParam->pAbsCoefA, pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters coefficient b to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_B_COEFF], pCurveParam->pCoefB, pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters modulus value p to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], pCurveParam->pModulus, pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters scalar multiplier k to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_K], pClearPrivateKey, pCurveParam->primeOrderSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_K + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters Point P coordinate x to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X], pCurveParam->pPointX,
+ pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters Point P coordinate y to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y], pCurveParam->pPointY,
+ pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters curve prime order N to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], pCurveParam->pPrimeOrder,
+ pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+
+ /********************************************************************************************** Start the operation */
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* Set the mode and deactivate the interrupts */
+ MODIFY_REG(PKA->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE,
+ CCB_PKA_ECC_MUL_MODE << PKA_CR_MODE_Pos);
+
+ /* Start the computation */
+ PKA->CR |= PKA_CR_START;
+
+ /* Wait for the end of operation or timeout */
+ while ((PKA->SR & PKA_SR_PROCENDF) == 0UL)
+ {
+ if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0UL))
+ {
+ /* Abort any ongoing operation */
+ CLEAR_BIT(PKA->CR, PKA_CR_EN);
+ /* Make ready for the next operation */
+ SET_BIT(PKA->CR, PKA_CR_EN);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear all flags */
+ PKA->CLRFR |= (PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC);
+ /* get PublicKey result */
+ /* Move the result from appropriate location (with opprand size in 32bit word ) */
+ CCB_Memcpy_u32_to_u32(PublicKey[0], &PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X],
+ ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+ CCB_Memcpy_u32_to_u32(PublicKey[1], &PKA->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y],
+ ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+
+ if (PKA_RAM_Erase() != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Compute CCB Modular exponentiation.
+ * @param pParam pointer to the modular exponatiation parameters.
+ * @param pRSAClearPrivateKey pointer to the clear Private Key.
+ * @param pOp1 Pointer to Operand 1 (Array of size elements).
+ * @param pReferenceModularExp pointer to the ReferenceModularExp computed in modular exponentiation Blob creation.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef PKA_RSA_ComputeModularExp(CCB_RSAParamTypeDef *pParam,
+ const CCB_RSAClearKeyTypeDef *pRSAClearPrivateKey,
+ uint8_t *pOp1, uint32_t *pReferenceModularExp)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Get the number of bit per operand */
+ PKA->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = pParam->modulusSizeByte * 8U;
+
+ /* Get the number of bit of the exponent */
+ PKA->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = pParam->expSizeByte * 8U;
+
+ /* Move the input parameters pOp1 to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE], pOp1, pParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE + ((pParam->modulusSizeByte + 3UL) / 4UL));
+
+ /* Move the exponent to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT], pRSAClearPrivateKey->pExp, pParam->expSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + ((pParam->expSizeByte + 3UL) / 4UL));
+
+ /* Move the modulus to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_MODULUS], pParam->pMod, pParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_MODULUS + ((pParam->modulusSizeByte + 3UL) / 4UL));
+
+ /* Move Phi value to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI], pRSAClearPrivateKey->pPhi, pParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + ((pParam->modulusSizeByte + 3UL) / 4UL));
+
+ /* Set the mode and deactivate the interrupts */
+ MODIFY_REG(PKA->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE,
+ CCB_PKA_MODE_MODULAR_EXP_PROTECT << PKA_CR_MODE_Pos);
+
+ /* Start the computation */
+ PKA->CR |= PKA_CR_START;
+
+ /* Wait for the end of operation or timeout */
+ while ((PKA->SR & PKA_SR_PROCENDF) == 0UL)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if ((HAL_GetTick() - tickstart) > HAL_CCB_TIMEOUT_DEFAULT_VALUE)
+ {
+ /* Abort any ongoing operation */
+ CLEAR_BIT(PKA->CR, PKA_CR_EN);
+ /* Make ready for the next operation */
+ SET_BIT(PKA->CR, PKA_CR_EN);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear all flags */
+ PKA->CLRFR |= (PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC);
+
+ /* Move the result from appropriate location (with opprand size in 32bit word ) */
+ CCB_Memcpy_u32_to_u32(pReferenceModularExp, &PKA->RAM[PKA_MODULAR_EXP_OUT_RESULT],
+ ((pParam->modulusSizeByte + 3UL) / 4UL));
+
+ if (PKA_RAM_Erase() != HAL_OK)
+ {
+ /* return error */
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ @brief Verify the validity of a signature using elliptic curves over prime fields in blocking mode.
+ * @param pCurveParam pointer to the Curve parameters.
+ * @param pPublicKeyOut pointer to the public key.
+ * @param pHash pointer to the hash.
+ * @param pSignature Pointer to input signature
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef PKA_ECDSAVerif(CCB_ECDSACurveParamTypeDef *pCurveParam,
+ CCB_ECCMulPointTypeDef *pPublicKeyOut, const uint8_t *pHash,
+ CCB_ECDSASignTypeDef *pSignature)
+{
+ uint32_t tickstart;
+ uint32_t timeout = HAL_CCB_TIMEOUT_DEFAULT_VALUE;
+
+ /* Set CCB input parameter in PKA RAM */
+ /* Get the prime order n length */
+ PKA->RAM[PKA_ECDSA_VERIF_IN_ORDER_NB_BITS] = GetOptBitSize_u8(pCurveParam->primeOrderSizeByte,
+ *(pCurveParam->pPrimeOrder));
+
+ /* Get the modulus p length */
+ PKA->RAM[PKA_ECDSA_VERIF_IN_MOD_NB_BITS] = GetOptBitSize_u8(pCurveParam->modulusSizeByte, *(pCurveParam->pModulus));
+
+ /* Get the coefficient a sign */
+ PKA->RAM[PKA_ECDSA_VERIF_IN_A_COEFF_SIGN] = pCurveParam->coefSignA;
+
+ /* Move the input parameters coefficient |a| to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_A_COEFF], pCurveParam->pAbsCoefA, pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_A_COEFF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters modulus value p to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_MOD_GF], pCurveParam->pModulus, pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_MOD_GF + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters base point G coordinate x to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_X], pCurveParam->pPointX,
+ pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_INITIAL_POINT_X + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters base point G coordinate y to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y], pCurveParam->pPointY,
+ pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X], pPublicKeyOut->pPointX,
+ pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y], pPublicKeyOut->pPointY,
+ pCurveParam->modulusSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y + ((pCurveParam->modulusSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters signature part r to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_R], pSignature->pRSign, pCurveParam->primeOrderSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_SIGNATURE_R + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters signature part s to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_S], pSignature->pSSign, pCurveParam->primeOrderSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_SIGNATURE_S + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters hash of message z to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_HASH_E], pHash, pCurveParam->primeOrderSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_HASH_E + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL));
+
+ /* Move the input parameters curve prime order n to PKA RAM */
+ CCB_Memcpy_u8_to_u32(&PKA->RAM[PKA_ECDSA_VERIF_IN_ORDER_N], pCurveParam->pPrimeOrder,
+ pCurveParam->primeOrderSizeByte);
+ RAM_PARAM_END(PKA->RAM, PKA_ECDSA_VERIF_IN_ORDER_N + ((pCurveParam->primeOrderSizeByte + 3UL) / 4UL));
+
+
+ /* Set the mode and deactivate the interrupts */
+ MODIFY_REG(PKA->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE,
+ CCB_PKA_MODE_ECDSA_VERIFICATION << PKA_CR_MODE_Pos);
+
+ /* Start the computation */
+ PKA->CR |= PKA_CR_START;
+
+ tickstart = HAL_GetTick();
+ /* Wait for the end of operation or timeout */
+ while ((PKA->SR & PKA_SR_PROCENDF) == 0UL)
+ {
+ if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0UL))
+ {
+ /* Abort any ongoing operation */
+ CLEAR_BIT(PKA->CR, PKA_CR_EN);
+ /* Make ready for the next operation */
+ SET_BIT(PKA->CR, PKA_CR_EN);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear all flags */
+ PKA->CLRFR |= (PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Return the result of the ECDSA verification operation.
+ * @retval 1 if signature is verified, 0 in other case
+ */
+static uint32_t PKA_ECDSAVerif_Result(void)
+{
+ return (PKA->RAM[PKA_ECDSA_VERIF_OUT_RESULT]);
+}
+
+/**
+ * @brief Reset the PKA RAM.
+ * @retval None
+ */
+static void CCB_PKA_RAMReset(void)
+{
+ uint32_t index;
+
+ /* For each element in the PKA RAM */
+ for (index = 0; index < CCB_PKA_RAM_SIZE; index++)
+ {
+ /* Clear the content */
+ PKA->RAM[index] = 0UL;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(CCB) && defined(HAL_CCB_MODULE_ENABLED) */
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_comp.c b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_comp.c
new file mode 100644
index 0000000000..4e01988a77
--- /dev/null
+++ b/system/Drivers/STM32U3xx_HAL_Driver/Src/stm32u3xx_hal_comp.c
@@ -0,0 +1,1061 @@
+/**
+ ******************************************************************************
+ * @file stm32u3xx_hal_comp.c
+ * @author MCD Application Team
+ * @brief COMP HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the COMP peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral control functions
+ * + Peripheral state functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### COMP Peripheral features #####
+ ==============================================================================
+
+ [..]
+ The STM32U3xx device family integrates two analog comparators instances:
+ COMP1, COMP2.
+ (#) Comparators input minus (inverting input) and input plus (non inverting input)
+ can be set to internal references or to GPIO pins
+ (refer to GPIO list in reference manual).
+
+ (#) Comparators output level is available using HAL_COMP_GetOutputLevel()
+ and can be redirected to other peripherals: GPIO pins (in mode
+ alternate functions for comparator), timers.
+ (refer to GPIO list in reference manual).
+
+ (#) The comparators have interrupt capability through the EXTI controller
+ with wake-up from sleep and stop modes.
+
+ (#) Pairs of comparators instances can be combined in window mode
+ (2 consecutive instances odd and even COMP
+
+![ST logo]()
+
+
+Release Notes for
+STM32U3xx HAL Drivers
+Copyright © 2024 STMicroelectronics
+Purpose
+The STM32Cube HAL and LL, an STM32 abstraction layer embedded +software, ensure maximized portability across STM32 portfolio.
+The portable APIs layer provides a generic, multi instanced and +simple set of APIs to interact with the upper layer (application, +libraries and stacks). It is composed of native and extended APIs set. +It is directly built around a generic architecture and allows the +build-upon layers, like the middleware layer, to implement its functions +without knowing in-depth the used STM32 device. This improves the +library code reusability and guarantees an easy portability on other +devices and STM32 families.
+The Low Layer (LL) drivers are part of the STM32Cube firmware HAL +that provides a basic set of optimized and one shot services. The Low +layer drivers, contrary to the HAL ones are not fully portable across +the STM32 families; the availability of some functions depends on the +physical availability of the relative features on the product. The Low +Layer (LL) drivers are designed to offer the following features:
+-
+
- New set of inline functions for direct and atomic register +access +
- One-shot operations that can be used by the HAL drivers or from +application level +
- Full independence from HAL and standalone usage (without HAL +drivers) +
- Full features coverage of all the supported peripherals +
Update History
+
+
+
+
+
+
+Maintenance release
+-
+
- Maintenance Release of STM32CubeU3 HAL/LL Drivers supporting +STM32U375xx/STM32U385xx devices +
Contents
+HAL Drivers updates
+-
+
- HAL CCB driver
+
-
+
- Update related to wrap/unwrap symmetric key algo +
+ - HAL DMA driver
+
-
+
- DMA Callbacks to be initialized to NULL in RESET state +
+ - HAL GPIO driver
+
-
+
- Add pull down capability missing in analog mode +
+ - HAL I3C driver
+
-
+
- Remove extra parenthesis in function HAL_I3C_Tgt_IBIReq +
+ - HAL IWDG driver
+
-
+
- Fix Timeout computation method +
+ - HAL PWR driver
+
-
+
- Fix doxygen comments
+
+
+ - Fix doxygen comments
- HAL SPI driver
+
-
+
- Add protection against wrong transfer size during transmission +
- Check coherence between data size and DMA TX configuration
+
+ - Clear auto suspend flag in HAL_SPI_Receive() +
- Ensure DMA RX aborts after DMA TX in HAL_SPI_Abort_IT() +
- Fix CRC computation to fit with standard CRC16-CCITT (XMODEM) +
- Fix a bug reception when FIFO threshold is set +
- Improve file aspect +
+ - HAL TIM driver
+
-
+
- Fix update flag (UIF) clearing in TIM_Base_SetConfig. +
+ - HAL UART driver
+
-
+
- Correct references to HAL_UARTEx_WakeupCallback and to +HAL_UART_WAKEUP_CB_ID define, according to series capabilities +
- Provide accurate position in RxEventCallback when ReceptionToIdle +mode is used with DMA, when UART and DMA interrupts process is +delayed. +
+ - HAL USB
+
-
+
- Fix SA0035 +
+ - HAL XSPI driver
+
-
+
- Check BUSY flag instead of TC flag in indirect mode to be sure that +command is well completed (FIFO flush) +
+
LL Drivers updates
+-
+
- LL LPUART driver
+
-
+
- Solve Coverity out-of-bound memory access warning in use of +LPUART_PRESCALER_TAB array +
+ - LL USART driver
+
-
+
- Solve Coverity out-of-bound memory access warning in use of +USART_PRESCALER_TAB array +
+
Backward compatibility
+-
+
- Not applicable +
Known Limitations
+-
+
- Not applicable +
+
+
+
+
+
+
+First Release
+-
+
- First Official Release of STM32CubeU3 HAL/LL Drivers supporting +STM32U375xx/STM32U385xx devices +
Contents
+-
+
- STM32CubeU3 HAL/LL Drivers supporting STM32U375xx/STM32U385xx
+devices :
+
-
+
HAL: ADC, CCB, COMP, CORTEX, CRC, CRS, CRYP, +DAC, DLB, DMA, EXTI, FDCAN, FLASH, GPIO, GTZC, HASH, I2C, I3C, ICACHE, +IRDA, IWDG, LPTIM, MDF, OPAMP, PKA, PWR, RAMCFG, RCC, RNG, RTC, SAI, +SDMMC, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, USB, WWDG, +XSPI
+LL: ADC, COMP, CRC, CRS, DAC, DLB, DMA, EXTI, +GPIO, I2C, I3C, ICACHE, LPTIM, LPUART, OPAMP, PKA, PWR, RCC, RNG, RTC, +SDMMC, SPI, TIM, USART, UTILS
+
+
Supported Devices and boards
+-
+
- STM32U375xx/STM32U385xx devices +
- NUCLEO-U385RG-Q (Rev.E) board +
Backward compatibility
+-
+
- Not applicable +
Known Limitations
+-
+
- None +
Dependencies
+-
+
- None +
Notes
+-
+
- None +
+