Skip to content
Verilog Conversion

⚠️ rename Zxcfu ISA extension #142

Sign in to view logs

⚠️ rename Zxcfu ISA extension

⚠️ rename Zxcfu ISA extension #142

Triggered via pull request February 1, 2026 15:47
@stnoltingstnolting
synchronize #1487
xcfu
Status Success
Total duration 6m 28s
Artifacts 1

Verilog.yml

on: pull_request
♻️ Convert to Verilog
14s
♻️ Convert to Verilog
🖥️ Verilog simulation - Icarus Verilog
6m 7s
🖥️ Verilog simulation - Icarus Verilog
🖥️ Verilog simulation - Verilator
36s
🖥️ Verilog simulation - Verilator
Fit to window
Zoom out
Zoom in

Artifacts

Produced during runtime
Name Size Digest
neorv32_verilog_wrapper
343 KB
sha256:c079fa1f9098df1c1086449ad97288706e188e2fd54c77c46d1ffca5d068a525