[cache] fix minimal cache block size (#1310)

Author: stnolting

CHANGELOG.md

@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 09.07.2025 | 1.11.7.9 | :bug: fix minimal cache block size (has to be at least 8 bytes / 2 words) | [#](https://github.com/stnolting/neorv32/pull/1310) |
 | 08.07.2025 | 1.11.7.8 | :warning: remove top `HART_BASE` generic | [#1308](https://github.com/stnolting/neorv32/pull/1308) |
 | 07.07.2025 | 1.11.7.7 | minor rtl edits and cleanups | [#1307](https://github.com/stnolting/neorv32/pull/1307) |
 | 06.07.2025 | 1.11.7.6 | :sparkles: add configurable number of HW triggers (break-/watchpoints) | [#1304](https://github.com/stnolting/neorv32/pull/1304) |

docs/datasheet/soc.adoc

@@ -261,7 +261,7 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
 | `ICACHE_NUM_BLOCKS`     | natural   | 4             | Number of blocks ("lines") Has to be a power of two.
 | `DCACHE_EN`             | boolean   | false         | Implement the data cache (D$)
 | `DCACHE_NUM_BLOCKS`     | natural   | 4             | Number of blocks ("lines"). Has to be a power of two.
-| `CACHE_BLOCK_SIZE`      | natural   | 64            | Size in bytes of each block (I$ and D$). Has to be a power of two.
+| `CACHE_BLOCK_SIZE`      | natural   | 64            | Size in bytes of each block (I$ and D$). Has to be a power of two, min 8.
 4+^| **<<_processor_external_bus_interface_xbus>> (Wishbone / AXI4)**
 | `XBUS_EN`               | boolean   | false         | Implement the external bus interface.
 | `XBUS_TIMEOUT`          | natural   | 255           | Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception.

docs/datasheet/soc_dcache.adoc

@@ -11,7 +11,7 @@
 | Top entity ports:       | none                |
 | Configuration generics: | `DCACHE_EN`         | implement processor-internal, CPU-exclusive data cache (D$) when `true`
 |                         | `DCACHE_NUM_BLOCKS` | number of cache blocks ("cache lines"); has to be a power of two
-|                         | `CACHE_BLOCK_SIZE`  | size of a cache block in bytes; has to be a power of two (global configuration for I$ and D$)
+|                         | `CACHE_BLOCK_SIZE`  | size of a cache block in bytes; has to be a power of two (global configuration for I$ and D$), min 8
 | CPU interrupts:         | none |
 |=======================
 

docs/datasheet/soc_icache.adoc

@@ -11,7 +11,7 @@
 | Top entity ports:       | none                |
 | Configuration generics: | `ICACHE_EN`         | implement processor-internal, CPU-exclusive instruction cache (I$) when `true`
 |                         | `ICACHE_NUM_BLOCKS` | number of cache blocks ("cache lines"); has to be a power of two
-|                         | `CACHE_BLOCK_SIZE`  | size of a cache block in bytes; has to be a power of two (global configuration for I$ and D$)
+|                         | `CACHE_BLOCK_SIZE`  | size of a cache block in bytes; has to be a power of two (global configuration for I$ and D$), min 8
 | CPU interrupts:         | none |
 |=======================
 

rtl/core/neorv32_cache.vhd

@@ -26,7 +26,7 @@ use neorv32.neorv32_package.all;
 entity neorv32_cache is
   generic (
     NUM_BLOCKS : natural range 2 to 1024;       -- number of cache blocks (min 2), has to be a power of 2
-    BLOCK_SIZE : natural range 4 to 32768;      -- cache block size in bytes (min 4), has to be a power of 2
+    BLOCK_SIZE : natural range 8 to 32768;      -- cache block size in bytes (min 8), has to be a power of 2
     UC_BEGIN   : std_ulogic_vector(3 downto 0); -- begin of uncached address space (page number / 4 MSBs of address)
     READ_ONLY  : boolean                        -- read-only accesses for host
   );

rtl/core/neorv32_package.vhd

@@ -29,7 +29,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110708"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110709"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width
 
@@ -845,7 +845,7 @@ package neorv32_package is
       ICACHE_NUM_BLOCKS     : natural range 1 to 4096        := 4;
       DCACHE_EN             : boolean                        := false;
       DCACHE_NUM_BLOCKS     : natural range 1 to 4096        := 4;
-      CACHE_BLOCK_SIZE      : natural range 4 to 1024        := 64;
+      CACHE_BLOCK_SIZE      : natural range 8 to 1024        := 64;
       -- External bus interface (XBUS) --
       XBUS_EN               : boolean                        := false;
       XBUS_TIMEOUT          : natural                        := 255;

rtl/core/neorv32_top.vhd

@@ -91,7 +91,7 @@ entity neorv32_top is
     ICACHE_NUM_BLOCKS     : natural range 1 to 4096        := 4;           -- i-cache: number of blocks (min 1), has to be a power of 2
     DCACHE_EN             : boolean                        := false;       -- implement data cache (d-cache)
     DCACHE_NUM_BLOCKS     : natural range 1 to 4096        := 4;           -- d-cache: number of blocks (min 1), has to be a power of 2
-    CACHE_BLOCK_SIZE      : natural range 4 to 1024        := 64;          -- i-cache/d-cache: block size in bytes (min 4), has to be a power of 2
+    CACHE_BLOCK_SIZE      : natural range 8 to 1024        := 64;          -- i-cache/d-cache: block size in bytes (min 8), has to be a power of 2
 
     -- External bus interface (XBUS) --
     XBUS_EN               : boolean                        := false;       -- implement external memory bus interface

rtl/system_integration/neorv32_libero_ip.vhd

@@ -85,7 +85,7 @@ entity neorv32_libero_ip is
     ICACHE_NUM_BLOCKS      : natural range 1 to 4096        := 4;
     DCACHE_EN_INT          : integer range 0 to 1           := 0;
     DCACHE_NUM_BLOCKS      : natural range 1 to 4096        := 4;
-    CACHE_BLOCK_SIZE       : natural range 4 to 1024        := 64;
+    CACHE_BLOCK_SIZE       : natural range 8 to 1024        := 64;
     -- External Bus Interface --
     XBUS_EN_INT            : integer range 0 to 1           := 1;
     XBUS_REGSTAGE_EN_INT   : integer range 0 to 1           := 1;

rtl/system_integration/neorv32_vivado_ip.vhd

@@ -86,7 +86,7 @@ entity neorv32_vivado_ip is
     ICACHE_NUM_BLOCKS     : natural range 1 to 4096        := 4;
     DCACHE_EN             : boolean                        := false;
     DCACHE_NUM_BLOCKS     : natural range 1 to 4096        := 4;
-    CACHE_BLOCK_SIZE      : natural range 4 to 1024        := 64;
+    CACHE_BLOCK_SIZE      : natural range 8 to 1024        := 64;
     -- External Bus Interface --
     XBUS_EN               : boolean                        := false;
     XBUS_REGSTAGE_EN      : boolean                        := false;

sim/neorv32_tb.vhd

@@ -57,7 +57,7 @@ entity neorv32_tb is
     ICACHE_NUM_BLOCKS   : natural range 1 to 4096        := 64;          -- i-cache: number of blocks (min 1), has to be a power of 2
     DCACHE_EN           : boolean                        := true;        -- implement data cache
     DCACHE_NUM_BLOCKS   : natural range 1 to 4096        := 32;          -- d-cache: number of blocks (min 1), has to be a power of 2
-    CACHE_BLOCK_SIZE    : natural range 4 to 1024        := 32;          -- i-cache/d-cache: block size in bytes (min 4), has to be a power of 2
+    CACHE_BLOCK_SIZE    : natural range 8 to 1024        := 32;          -- i-cache/d-cache: block size in bytes (min 8), has to be a power of 2
     -- external memory A --
     EXT_MEM_A_EN        : boolean                        := false;       -- enable memory
     EXT_MEM_A_BASE      : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address, has to be word-aligned