🚀 preparing release v1.12.1

Author: stnolting

CHANGELOG.md

@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 29.08.2025 | [**1.12.1**](https://github.com/stnolting/neorv32/releases/tag/v1.12.1) | :rocket: **New release** | |
 | 28.08.2025 | 1.12.0.10 | fix minor RISC-V incompatibilities (reset `mstatus.mpp` to all-zero; AMO memory faults have to raise store exceptions) | [#1360](https://github.com/stnolting/neorv32/pull/1360) |
 | 28.08.2025 | 1.12.0.9 | :warning: rework TWD module due do to several minor design flaws | [#1359](https://github.com/stnolting/neorv32/pull/1359) |
 | 27.08.2025 | 1.12.0.8 | add two new write-only flags to the SDI control register to clear the RX and TX FIFOs | [#1358](https://github.com/stnolting/neorv32/pull/1358) |

docs/attrs.adoc

@@ -1,6 +1,6 @@
 :keywords: neorv32, risc-v, fpga, soft-core, microcontroller, cpu, soc, processor, asip
 :description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
-:revnumber: v1.12.0
+:revnumber: v1.12.1
 :icons: font
 :source-highlighter: highlight.js
 :imagesdir: ../figures

rtl/core/neorv32_package.vhd

@@ -28,7 +28,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01120010"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01120100"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width
 

sw/svd/neorv32.svd

@@ -4,7 +4,7 @@
   <vendor>github.com/stnolting/neorv32</vendor>
   <name>neorv32</name>
   <series>RISC-V</series>
-  <version>1.12.0</version>
+  <version>1.12.1</version>
   <description>The NEORV32 RISC-V Processor</description>
 
   <!-- CPU core -->