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[cpu] remove mxcsr CSR (#1459)
2 parents 79237d5 + 15ce6e4 commit 3ac602d

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18 files changed

+118
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‎CHANGELOG.md‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,8 +29,9 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
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3030
| Date | Version | Comment | Ticket |
3131
|:----:|:-------:|:--------|:------:|
32+
| 21.12.2025 | 1.12.5.7 | :warning: remove `mxcsr` CSR | [#1459](https://github.com/stnolting/neorv32/pull/1459) |
3233
| 19.12.2025 | 1.12.5.6 | further CPU code cleanups | [#1456](https://github.com/stnolting/neorv32/pull/1456) |
33-
| 14.12.2025 | 1.12.5.5 | CPU control: massive code refactoring and optimization | [#1449](https://github.com/stnolting/neorv32/pull/1449) <
34+
| 14.12.2025 | 1.12.5.5 | CPU control: massive code refactoring and optimization | [#1449](https://github.com/stnolting/neorv32/pull/1449) |
3435
| 07.12.2025 | 1.12.5.4 | :sparkles: PWM: add optional phase-correct operation mode | [#1445](https://github.com/stnolting/neorv32/pull/1445) |
3536
| 06.12.2025 | 1.12.5.3 | minor rtl edits and cleanups | [#1444](https://github.com/stnolting/neorv32/pull/1444) |
3637
| 05.12.2025 | 1.12.5.2 | :warning: remove UART0/1 simulation-mode **file** logging | [#1443](https://github.com/stnolting/neorv32/pull/1443) |

‎docs/datasheet/cpu.adoc‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -290,12 +290,7 @@ package file (`neorv32_package.vhd`).
290290
The top module provides several tuning options to optimize the CPU for performance, size and even security.
291291
Note that these configuration options have no impact on the actual functionality (e.g. ISA compatibility).
292292

293-
.Tuning Options Discovery
294-
[TIP]
295-
Software can check for configured tuning options via specific flags in the <<_mxcsr>> CSR.
296-
297293

298-
{empty} +
299294
[discrete]
300295
===== **`CPU_TRACE_EN`**
301296

‎docs/datasheet/cpu_csr.adoc‎

Lines changed: 1 addition & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,6 @@ In the following table these CSRs are highlighted with "⚠️".
8181
| 0xf14 | <<_mhartid>> | `CSR_MHARTID` | MRO | Machine hardware thread ID
8282
| 0xf15 | <<_mconfigptr>> | `CSR_MCONFIGPTR` | MRO | Machine configuration pointer register
8383
5+^| **<<_neorv32_specific_csrs>>**
84-
| 0xbc0 | <<_mxcsr>> | `CSR_MXCSR` | MRW | Machine status and control register
8584
| 0xfc0 | <<_mxisa>> | `CSR_MXISA` | MRO | Extended machine CPU ISA and extensions
8685
|=======================
8786

@@ -921,39 +920,9 @@ ID of each core is unique and starts at 0 and is incremented continuously.
921920

922921
.RISC-V-Compliant Mapping
923922
[NOTE]
924-
All NEORV32-specific CSRs are mapped to addresses that are explicitly reserved for custom/implementation-specific use.
923+
NEORV32-specific CSRs are mapped to addresses that are explicitly reserved for custom/implementation-specific use.
925924

926925

927-
[discrete]
928-
===== **`mxcsr`**
929-
930-
[cols="<1,<8"]
931-
[grid="none"]
932-
|=======================
933-
| Name | Machine status and control register
934-
| Address | `0xbc0`
935-
| Reset value | `DEFINED`
936-
| ISA | `Zicsr` & `X`
937-
| Description | The `mxcsr` CSR is a NEORV32-specific read/write CSR that provides additional
938-
machine configurations and status information.
939-
|=======================
940-
941-
.`mxcsr` CSR Bits
942-
[cols="^1,<2,^1,<6"]
943-
[options="header",grid="rows"]
944-
|=======================
945-
| Bit | Name [C] | R/W | Description
946-
| 25:0 | - | r/- | _reserved_, read as zero
947-
| 26 | `CSR_MXCSR_TRACE` | r/- | <<_cpu_tuning_options>>: CPU trace generator and <<_execution_trace_port>> enabled (implicitly enabled when enabling <<_execution_trace_buffer_tracer>>)
948-
| 27 | `CSR_MXCSR_CONSTTBR` | r/- | <<_cpu_tuning_options>>: constant-time branches enabled when set (`CPU_CONSTT_BR_EN` top generic)
949-
| 28 | `CSR_MXCSR_RFHWRST` | r/- | <<_cpu_tuning_options>>: full hardware reset of register file available when set (`CPU_RF_HW_RST_EN` top generic)
950-
| 29 | `CSR_MXCSR_FASTMUL` | r/- | <<_cpu_tuning_options>>: fast multiplication available when set (`CPU_FAST_MUL_EN` top generic)
951-
| 30 | `CSR_MXCSR_FASTSHIFT` | r/- | <<_cpu_tuning_options>>: fast shifts available when set (`CPU_FAST_SHIFT_EN` top generic)
952-
| 31 | `CSR_MXCSR_IS_SIM` | r/- | set if CPU is being _simulated_ (not guaranteed)
953-
|=======================
954-
955-
956-
{empty} +
957926
[discrete]
958927
===== **`mxisa`**
959928

‎docs/datasheet/soc_sysinfo.adoc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,7 @@ to take into account a dynamic frequency scaling of the processor.
106106
| `28` | `SYSINFO_SOC_IO_GPTMR` | set if GPTMR is implemented (via top's `IO_GPTMR_NUM` generic)
107107
| `29` | `SYSINFO_SOC_IO_SLINK` | set if stream link interface is implemented (via top's `IO_SLINK_EN` generic)
108108
| `30` | `SYSINFO_SOC_IO_ONEWIRE` | set if ONEWIRE interface is implemented (via top's `IO_ONEWIRE_EN` generic)
109-
| `31` | - | _reserved_, read as zero
109+
| `31` | `SYSINFO_SOC_SIM` | set if NEORV32 is being simulated
110110
|=======================
111111

112112

‎rtl/core/neorv32_cache.vhd‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ architecture neorv32_cache_rtl of neorv32_cache is
6868
clr_i : in std_ulogic;
6969
new_i : in std_ulogic;
7070
hit_o : out std_ulogic;
71-
dir_o : out std_ulogic;
71+
drt_o : out std_ulogic;
7272
tag_o : out std_ulogic_vector(31 downto 0);
7373
addr_i : in std_ulogic_vector(31 downto 0);
7474
we_i : in std_ulogic_vector(3 downto 0);
@@ -93,7 +93,7 @@ architecture neorv32_cache_rtl of neorv32_cache is
9393
-- cache -> control interface --
9494
type cache_i_t is record
9595
sta_hit : std_ulogic;
96-
sta_dir : std_ulogic;
96+
sta_drt : std_ulogic;
9797
data : std_ulogic_vector(31 downto 0);
9898
stat : std_ulogic;
9999
end record;
@@ -210,14 +210,14 @@ begin
210210
ctrl_nxt.state <= S_IDLE;
211211
end if;
212212
elsif (host_req_i.rw = '0') or READ_ONLY then -- read MISS
213-
if (cache_i.sta_dir = '1') and (not WRITE_THROUGH) and (not READ_ONLY) then
213+
if (cache_i.sta_drt = '1') and (not WRITE_THROUGH) and (not READ_ONLY) then
214214
host_rsp_o.err <= '1'; -- [TODO] error as feature not implemented yet
215215
ctrl_nxt.state <= S_IDLE; -- [TODO] upload dirty block first
216216
else
217-
ctrl_nxt.state <= S_DOWNLOAD_START; -- just get block from main memory
217+
ctrl_nxt.state <= S_DOWNLOAD_START; -- get block from main memory
218218
end if;
219219
else -- write MISS
220-
if (cache_i.sta_dir = '1') and (not WRITE_THROUGH) then
220+
if (cache_i.sta_drt = '1') and (not WRITE_THROUGH) then
221221
host_rsp_o.err <= '1'; -- [TODO] error as feature not implemented yet
222222
ctrl_nxt.state <= S_IDLE; -- [TODO] upload dirty block first
223223
else -- write-through: write to main memory, no cache update
@@ -333,7 +333,7 @@ begin
333333
clr_i => cache_o.cmd_clr, -- clear entire cache
334334
new_i => cache_o.cmd_new, -- make accessed block valid and set tag
335335
hit_o => cache_i.sta_hit, -- cache hit
336-
dir_o => cache_i.sta_dir, -- cache dirty
336+
drt_o => cache_i.sta_drt, -- cache dirty
337337
tag_o => open, -- tag of accessed block; MSB-aligned, zero-extended
338338
-- cache access --
339339
addr_i => cache_o.addr, -- access address
@@ -377,7 +377,7 @@ entity neorv32_cache_memory is
377377
clr_i : in std_ulogic; -- clear entire cache
378378
new_i : in std_ulogic; -- make accessed block valid & clean and set tag
379379
hit_o : out std_ulogic; -- cache hit
380-
dir_o : out std_ulogic; -- accessed block is dirty
380+
drt_o : out std_ulogic; -- accessed block is dirty
381381
tag_o : out std_ulogic_vector(31 downto 0); -- tag of accessed block; MSB-aligned, zero-extended
382382
-- cache access --
383383
addr_i : in std_ulogic_vector(31 downto 0); -- access address
@@ -465,7 +465,7 @@ begin
465465
end process status_memory;
466466

467467
-- modified cache --
468-
dir_o <= valid_mem_rd and dirty_mem_rd;
468+
drt_o <= valid_mem_rd and dirty_mem_rd;
469469

470470

471471
-- Tag Memory -----------------------------------------------------------------------------

‎rtl/core/neorv32_cpu.vhd‎

Lines changed: 39 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -224,51 +224,47 @@ begin
224224
neorv32_cpu_control_inst: entity neorv32.neorv32_cpu_control
225225
generic map (
226226
-- General --
227-
HART_ID => HART_ID, -- hardware thread ID
228-
BOOT_ADDR => BOOT_ADDR, -- cpu boot address
229-
DEBUG_PARK_ADDR => DEBUG_PARK_ADDR, -- cpu debug mode parking loop entry address
230-
DEBUG_EXC_ADDR => DEBUG_EXC_ADDR, -- cpu debug mode exception entry address
227+
HART_ID => HART_ID, -- hardware thread ID
228+
BOOT_ADDR => BOOT_ADDR, -- CPU boot address
229+
DEBUG_PARK_ADDR => DEBUG_PARK_ADDR, -- CPU debug mode parking loop entry address
230+
DEBUG_EXC_ADDR => DEBUG_EXC_ADDR, -- CPU debug mode exception entry address
231231
-- RISC-V ISA Extensions --
232-
RISCV_ISA_A => riscv_a_c, -- atomic memory operations extension
233-
RISCV_ISA_B => riscv_b_c, -- bit-manipulation extension
234-
RISCV_ISA_C => RISCV_ISA_C, -- compressed extension
235-
RISCV_ISA_E => RISCV_ISA_E, -- embedded RF extension
236-
RISCV_ISA_M => RISCV_ISA_M, -- mul/div extension
237-
RISCV_ISA_U => RISCV_ISA_U, -- user mode extension
238-
RISCV_ISA_Zaamo => RISCV_ISA_Zaamo, -- atomic read-modify-write operations extension
239-
RISCV_ISA_Zalrsc => RISCV_ISA_Zalrsc, -- atomic reservation-set operations extension
240-
RISCV_ISA_Zcb => riscv_zcb_c, -- additional code size reduction instructions
241-
RISCV_ISA_Zba => RISCV_ISA_Zba, -- shifted-add bit-manipulation extension
242-
RISCV_ISA_Zbb => RISCV_ISA_Zbb, -- basic bit-manipulation extension
243-
RISCV_ISA_Zbkb => RISCV_ISA_Zbkb, -- bit-manipulation instructions for cryptography
244-
RISCV_ISA_Zbkc => RISCV_ISA_Zbkc, -- carry-less multiplication instructions
245-
RISCV_ISA_Zbkx => RISCV_ISA_Zbkx, -- cryptography crossbar permutation extension
246-
RISCV_ISA_Zbs => RISCV_ISA_Zbs, -- single-bit bit-manipulation extension
247-
RISCV_ISA_Zfinx => RISCV_ISA_Zfinx, -- 32-bit floating-point extension
248-
RISCV_ISA_Zibi => RISCV_ISA_Zibi, -- branch with immediate
249-
RISCV_ISA_Zicntr => RISCV_ISA_Zicntr, -- base counters
250-
RISCV_ISA_Zicond => RISCV_ISA_Zicond, -- integer conditional operations
251-
RISCV_ISA_Zihpm => RISCV_ISA_Zihpm, -- hardware performance monitors
252-
RISCV_ISA_Zimop => RISCV_ISA_Zimop, -- may-be-operations
253-
RISCV_ISA_Zkn => riscv_zkn_c, -- NIST algorithm suite available
254-
RISCV_ISA_Zknd => RISCV_ISA_Zknd, -- cryptography NIST AES decryption extension
255-
RISCV_ISA_Zkne => RISCV_ISA_Zkne, -- cryptography NIST AES encryption extension
256-
RISCV_ISA_Zknh => RISCV_ISA_Zknh, -- cryptography NIST hash extension
257-
RISCV_ISA_Zks => riscv_zks_c, -- ShangMi algorithm suite available
258-
RISCV_ISA_Zksed => RISCV_ISA_Zksed, -- ShangMi block cipher extension
259-
RISCV_ISA_Zksh => RISCV_ISA_Zksh, -- ShangMi hash extension
260-
RISCV_ISA_Zkt => riscv_zkt_c, -- data-independent execution time for cryptography operations available
261-
RISCV_ISA_Zmmul => RISCV_ISA_Zmmul, -- multiply-only M sub-extension
262-
RISCV_ISA_Zxcfu => RISCV_ISA_Zxcfu, -- custom (instr.) functions unit
263-
RISCV_ISA_Sdext => RISCV_ISA_Sdext, -- external debug mode extension
264-
RISCV_ISA_Sdtrig => RISCV_ISA_Sdtrig, -- trigger module extension
265-
RISCV_ISA_Smpmp => RISCV_ISA_Smpmp, -- physical memory protection
232+
RISCV_ISA_A => riscv_a_c, -- atomic memory operations extension
233+
RISCV_ISA_B => riscv_b_c, -- bit-manipulation extension
234+
RISCV_ISA_C => RISCV_ISA_C, -- compressed extension
235+
RISCV_ISA_E => RISCV_ISA_E, -- embedded RF extension
236+
RISCV_ISA_M => RISCV_ISA_M, -- mul/div extension
237+
RISCV_ISA_U => RISCV_ISA_U, -- user mode extension
238+
RISCV_ISA_Zaamo => RISCV_ISA_Zaamo, -- atomic read-modify-write operations extension
239+
RISCV_ISA_Zalrsc => RISCV_ISA_Zalrsc, -- atomic reservation-set operations extension
240+
RISCV_ISA_Zcb => riscv_zcb_c, -- additional code size reduction instructions
241+
RISCV_ISA_Zba => RISCV_ISA_Zba, -- shifted-add bit-manipulation extension
242+
RISCV_ISA_Zbb => RISCV_ISA_Zbb, -- basic bit-manipulation extension
243+
RISCV_ISA_Zbkb => RISCV_ISA_Zbkb, -- bit-manipulation instructions for cryptography
244+
RISCV_ISA_Zbkc => RISCV_ISA_Zbkc, -- carry-less multiplication instructions
245+
RISCV_ISA_Zbkx => RISCV_ISA_Zbkx, -- cryptography crossbar permutation extension
246+
RISCV_ISA_Zbs => RISCV_ISA_Zbs, -- single-bit bit-manipulation extension
247+
RISCV_ISA_Zfinx => RISCV_ISA_Zfinx, -- 32-bit floating-point extension
248+
RISCV_ISA_Zibi => RISCV_ISA_Zibi, -- branch with immediate
249+
RISCV_ISA_Zicntr => RISCV_ISA_Zicntr, -- base counters
250+
RISCV_ISA_Zicond => RISCV_ISA_Zicond, -- integer conditional operations
251+
RISCV_ISA_Zihpm => RISCV_ISA_Zihpm, -- hardware performance monitors
252+
RISCV_ISA_Zimop => RISCV_ISA_Zimop, -- may-be-operations
253+
RISCV_ISA_Zkn => riscv_zkn_c, -- NIST algorithm suite available
254+
RISCV_ISA_Zknd => RISCV_ISA_Zknd, -- cryptography NIST AES decryption extension
255+
RISCV_ISA_Zkne => RISCV_ISA_Zkne, -- cryptography NIST AES encryption extension
256+
RISCV_ISA_Zknh => RISCV_ISA_Zknh, -- cryptography NIST hash extension
257+
RISCV_ISA_Zks => riscv_zks_c, -- ShangMi algorithm suite available
258+
RISCV_ISA_Zksed => RISCV_ISA_Zksed, -- ShangMi block cipher extension
259+
RISCV_ISA_Zksh => RISCV_ISA_Zksh, -- ShangMi hash extension
260+
RISCV_ISA_Zkt => riscv_zkt_c, -- data-independent execution time for cryptography operations available
261+
RISCV_ISA_Zmmul => RISCV_ISA_Zmmul, -- multiply-only M sub-extension
262+
RISCV_ISA_Zxcfu => RISCV_ISA_Zxcfu, -- custom (instr.) functions unit
263+
RISCV_ISA_Sdext => RISCV_ISA_Sdext, -- external debug mode extension
264+
RISCV_ISA_Sdtrig => RISCV_ISA_Sdtrig, -- trigger module extension
265+
RISCV_ISA_Smpmp => RISCV_ISA_Smpmp, -- physical memory protection
266266
-- Tuning Options --
267-
CPU_TRACE_EN => CPU_TRACE_EN, -- enable CPU execution trace generator
268-
CPU_CONSTT_BR_EN => CPU_CONSTT_BR_EN, -- constant-time branches
269-
CPU_FAST_MUL_EN => CPU_FAST_MUL_EN, -- use DSPs for M extension's multiplier
270-
CPU_FAST_SHIFT_EN => CPU_FAST_SHIFT_EN, -- use barrel shifter for shift operations
271-
CPU_RF_HW_RST_EN => CPU_RF_HW_RST_EN -- enable full hardware reset for register file
267+
CPU_CONSTT_BR_EN => CPU_CONSTT_BR_EN -- constant-time branches
272268
)
273269
port map (
274270
-- global control --

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