88| Hardware source files: | neorv32_gptmr.vhd |
99| Software driver files: | neorv32_gptmr.c |
1010| | neorv32_gptmr.h |
11- | Top entity ports: | `gptmr_trig_i` | timer capture input
11+ | Top entity ports: | none |
1212| Configuration generics: | `IO_GPTMR_EN` | implement general purpose timer when `true`
1313| CPU interrupts: | fast IRQ channel 12 | timer interrupt (see <<_processor_interrupts>>)
1414|=======================
1818
1919The general purpose timer module implements a simple yet universal 32-bit timer. It is implemented if the processor's
2020`IO_GPTMR_EN` top generic is set `true` . The timer provides a pre-scaled counter register that can trigger an interrupt
21- when reaching a programmable threshold value. Additionally, a timer-capture feature is implemented that copies the current
22- counter value to a dedicated register if a programmable edge occurs at the `gptmr_trig_i` input signal.
21+ when reaching a programmable threshold value.l.
2322
24- Four interface registers are available : a control register (`CTRL` ), a 32-bit counter register (`COUNT` ), a 32-bit
25- threshold register ( `THRES` ) and a 32-bit read-only capture register (`CAPTURE ` ). The timer is globally enabled by setting the
26- `GPTMR_CTRL_EN` bit in the device's control register `CTRL` . When the timer is enable the `COUNT` register will start
27- incrementing at a programmable rate, which scales the main processor clock. The pre-scaler value is configured via the
28- three `GPTMR_CTRL_PRSCx` control register bits:
23+ The GPTMR provides three interface registers : a control register (`CTRL` ), a 32-bit counter register (`COUNT` ) and a
24+ 32-bit threshold register (`THRES ` ). The timer is globally enabled by setting the `GPTMR_CTRL_EN` bit in the module's
25+ control register. When the timer is enable the `COUNT` register will start incrementing from zero at a programmable
26+ rate that scales the main processor clock. this pre-scaler is configured via the three `GPTMR_CTRL_PRSCx`
27+ control register bits:
2928
3029.GPTMR prescaler configuration
3130[cols="<4,^1,^1,^1,^1,^1,^1,^1,^1"]
@@ -35,40 +34,24 @@ three `GPTMR_CTRL_PRSCx` control register bits:
3534| Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096
3635|=======================
3736
38- [NOTE]
39- Disabling the timer will not clear the `COUNT` register. However, it can be manually reset at any time by
40- writing zero to it.
41-
42-
43- **Interval Timer**
44-
45- Whenever the counter register `COUNT` reaches the programmable threshold value `THRES` the counter register
46- is reset to zero and the _timer-match_ flag `GPTMR_CTRL_TRIGM` gets set. This flag has to be cleared manually
47- by writing zero to it. Optionally, an interrupt can be triggered if the `GPTMR_CTRL_IRQM` bit is set.
37+ Whenever the counter register `COUNT` equals the programmable threshold value `THRES` the module's interrupt
38+ signal becomes pending (indicated by `GPTMR_CTRL_IRQ_PND` being set). Note that a pending interrupt has to be
39+ cleared manually by writing a `1` to `GPTMR_CTRL_IRQ_CLR` .
4840
41+ The control register's `GPTMR_CTRL_MODE` bit defines what will happen when `COUNT == THRES` .
4942
50- **Timer Capture**
43+ * `GPTMR_CTRL_MODE = 0` : **single-shot mode** - the `COUNT` register will stop incrementing
44+ * `GPTMR_CTRL_MODE = 1` : **continuous mode** - the `COUNT` register is automatically reset and restarts incrementing from zero
5145
52- In addition to the the internal timer, the GPTMR provides a timer-capture feature. Whenever an edge is detected
53- at the `gptmr_trig_i` input signal the current `COUNT` value is copied to the read-only `CAPTURE` register and the
54- _capture-trigger_ flag `GPTMR_CTRL_TRIGC` gets set. This flag has to be cleared manually by writing zero to it.
55- Optionally, an interrupt can be triggered if the `GPTMR_CTRL_IRQC` bit is set.
56-
57- The triggering edge can be a rising-edge (if `GPTMR_CTRL_RISE` is set), a falling-edge (if `GPTMR_CTRL_FALL` is
58- set) or even both. By default, the `gptmr_trig_i` is sampled two times at the processor clock for checking for
59- edges. This simple edge detection is sufficient for trigger signals that are generated by (on-chip) digital logic.
60-
61- For sampling chip-external signals an optional filtering mode is available that can be enabled by the
62- `GPTMR_CTRL_FILTER` bit. If this bit is set, the `gptmr_trig_i` is sampled at a reduced clock speed (1/4 of the
63- processor clock) and the signal has to be stable for at lest 4 sample clock in order to be considered high or low.
64- This stabilized signal is then fed to the edge detection logic.
46+ .Resetting the Counter
47+ [NOTE]
48+ Disabling the GPTMR will also clear the `COUNT` register.
6549
6650
6751**Interrupt**
6852
69- The GPTRM provides a single interrupt line that can be trigger by a timer-match event and/or by a timer-compare
70- event. Once triggered, the interrupt will stay active until explicitly cleared by writing zero to the according
71- interrupt flag (`GPTMR_CTRL_TRIGM` or `GPTMR_CTRL_TRIGC` ).
53+ The GPTRM provides a single interrupt line is triggered whenever `COUNT` equals `THRES` . Once triggered, the interrupt will
54+ stay pending until explicitly cleared by writing a 1 to `GPTMR_CTRL_IRQ_CLR` .
7255
7356
7457**Register Map**
@@ -78,17 +61,12 @@ interrupt flag (`GPTMR_CTRL_TRIGM` or `GPTMR_CTRL_TRIGC`).
7861[options="header",grid="all"]
7962|=======================
8063| Address | Name [C] | Bit(s), Name [C] | R/W | Function
81- .10+<| `0xfffff100` .10+<| `CTRL` <|`0` `GPTMR_CTRL_EN` ^| r/w <| Timer enable flag
82- <|`3:1` `GPTMR_CTRL_PRSC2 : GPTMR_CTRL_PRSC0` ^| r/w <| 3-bit clock prescaler select
83- <|`4` `GPTMR_CTRL_IRQM` ^| r/w <| Enable interrupt on timer-match
84- <|`5` `GPTMR_CTRL_IRQC` ^| r/w <| Enable interrupt on capture-trigger
85- <|`6` `GPTMR_CTRL_RISE` ^| r/w <| Capture on rising edge
86- <|`7` `GPTMR_CTRL_FALL` ^| r/w <| Capture on falling edge
87- <|`8` `GPTMR_CTRL_FILTER` ^| r/w <| Filter capture input
88- <|`29:9` - ^| r/- <| _reserved_ , read as zero
89- <|`30` `GPTMR_CTRL_TRIGM` ^| r/c <| Timer-match has fired, cleared by writing 0
90- <|`31` `GPTMR_CTRL_TRIGC` ^| r/c <| Capture-trigger has fired, cleared by writing 0
64+ .6+<| `0xfffff100` .6+<| `CTRL` <|`0` `GPTMR_CTRL_EN` ^| r/w <| Timer enable flag
65+ <|`3:1` `GPTMR_CTRL_PRSC2 : GPTMR_CTRL_PRSC0` ^| r/w <| 3-bit clock prescaler select
66+ <|`4` `GPTMR_CTRL_MODE` ^| r/w <| Operation mode (0=single-shot, 1=continuous)
67+ <|`29:5` - ^| r/- <| _reserved_ , read as zero
68+ <|`30` `GPTMR_CTRL_IRQ_CLR` ^| -/w <| Write `1` to clear timer-match interrupt; auto-clears
69+ <|`31` `GPTMR_CTRL_IRQ_PND` ^| r/- <| Timer-match interrupt pending
9170| `0xfffff104` | `THRES` |`31:0` | r/w | Threshold value register
92- | `0xfffff108` | `COUNT` |`31:0` | r/w | Counter register
93- | `0xfffff10C` | `CAPTURE` |`31:0` | r/- | Capture register
71+ | `0xfffff108` | `COUNT` |`31:0` | r/- | Counter register
9472|=======================
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