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✨ [cpu] add support for RISC-V Zimop ISA extension (#1431)
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‎CHANGELOG.md‎

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@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
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| Date | Version | Comment | Ticket |
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|:----:|:-------:|:--------|:------:|
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| 23.11.2025 | 1.12.4.7 | :sparkles: add support for RISC-V `Zimop` ISA extension (may-be-operations) | [#1431](https://github.com/stnolting/neorv32/pull/1431) |
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| 22.11.2025 | 1.12.4.6 | :warning: extend max number of PWM channels from 16 to 32; rename PWM configuration generic to `IO_PWM_NUM`; resize `pwm_o` port | [#1429](https://github.com/stnolting/neorv32/pull/1429) |
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| 22.11.2025 | 1.12.4.5 | :warning: rework/redesign general purpose timer (GPTMR) module | [#1428](https://github.com/stnolting/neorv32/pull/1428) |
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| 21.11.2025 | 1.12.4.4 | :test_tube: cleanup NEORV32 RTE code and rewrite core in plain inline-assembly | [#](https://github.com/stnolting/neorv32/pull/1427) |

‎README.md‎

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@@ -97,13 +97,14 @@ setup according to your needs. Note that all of the following SoC modules are en
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[`Zbkc`](https://stnolting.github.io/neorv32/#_zbkc_isa_extension)
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[`Zbkx`](https://stnolting.github.io/neorv32/#_zbkx_isa_extension)
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[`Zbs`](https://stnolting.github.io/neorv32/#_zbs_isa_extension)
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[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_isa_extension)
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[`Zibi`](https://stnolting.github.io/neorv32/#_zibi_isa_extension)
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[`Zicntr`](https://stnolting.github.io/neorv32/#_zicntr_isa_extension)
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[`Zicond`](https://stnolting.github.io/neorv32/#_zicond_isa_extension)
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[`Zicsr`](https://stnolting.github.io/neorv32/#_zicsr_isa_extension)
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[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_isa_extension)
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[`Zihpm`](https://stnolting.github.io/neorv32/#_zihpm_isa_extension)
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[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_isa_extension)
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[`Zimop`](https://stnolting.github.io/neorv32/#_zimop_isa_extension)
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[`Zkn`](https://stnolting.github.io/neorv32/#_zkn_isa_extension)
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[`Zknd`](https://stnolting.github.io/neorv32/#_zknd_isa_extension)
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[`Zkne`](https://stnolting.github.io/neorv32/#_zkne_isa_extension)

‎docs/datasheet/cpu_csr.adoc‎

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@@ -968,36 +968,37 @@ discover additional ISA (sub-)extensions and CPU configuration options.
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[cols="^1,<2,^1,<6"]
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[options="header",grid="rows"]
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|=======================
971-
| Bit | Name [C] | R/W | Description
972-
| 0 | `CSR_MXISA_ZICSR` | r/- | <<_zicsr_isa_extension>> available
973-
| 1 | `CSR_MXISA_ZIFENCEI` | r/- | <<_zifencei_isa_extension>> available
974-
| 2 | `CSR_MXISA_ZMMUL` | r/- | <<_zmmul_isa_extension>> available
975-
| 3 | `CSR_MXISA_ZXCFU` | r/- | <<_zxcfu_isa_extension>> available
976-
| 4 | `CSR_MXISA_ZKT` | r/- | <<_zkt_isa_extension>> available
977-
| 5 | `CSR_MXISA_ZFINX` | r/- | <<_zfinx_isa_extension>> available
978-
| 6 | `CSR_MXISA_ZICOND` | r/- | <<_zicond_isa_extension>> available
979-
| 7 | `CSR_MXISA_ZICNTR` | r/- | <<_zicntr_isa_extension>> available
980-
| 8 | `CSR_MXISA_SMPMP` | r/- | <<_smpmp_isa_extension>> available
981-
| 9 | `CSR_MXISA_ZIHPM` | r/- | <<_zihpm_isa_extension>> available
982-
| 10 | `CSR_MXISA_SDEXT` | r/- | <<_sdext_isa_extension>> available
983-
| 11 | `CSR_MXISA_SDTRIG` | r/- | <<_sdtrig_isa_extension>> available
984-
| 12 | `CSR_MXISA_ZBKX` | r/- | <<_zbkx_isa_extension>> available
985-
| 13 | `CSR_MXISA_ZKND` | r/- | <<_zknd_isa_extension>> available
986-
| 14 | `CSR_MXISA_ZKNE` | r/- | <<_zkne_isa_extension>> available
987-
| 15 | `CSR_MXISA_ZKNH` | r/- | <<_zknh_isa_extension>> available
988-
| 16 | `CSR_MXISA_ZBKB` | r/- | <<_zbkb_isa_extension>> available
989-
| 17 | `CSR_MXISA_ZBKC` | r/- | <<_zbkc_isa_extension>> available
990-
| 18 | `CSR_MXISA_ZKN` | r/- | <<_zkn_isa_extension>> available
991-
| 19 | `CSR_MXISA_ZKSH` | r/- | <<_zksh_isa_extension>> available
992-
| 20 | `CSR_MXISA_ZKSED` | r/- | <<_zksed_isa_extension>> available
993-
| 21 | `CSR_MXISA_ZKS` | r/- | <<_zks_isa_extension>> available
994-
| 22 | `CSR_MXISA_ZBA` | r/- | <<_zba_isa_extension>> available
995-
| 23 | `CSR_MXISA_ZBB` | r/- | <<_zbb_isa_extension>> available
996-
| 24 | `CSR_MXISA_ZBS` | r/- | <<_zbs_isa_extension>> available
997-
| 25 | `CSR_MXISA_ZAAMO` | r/- | <<_zaamo_isa_extension>> available
998-
| 26 | `CSR_MXISA_ZALRSC` | r/- | <<_zalrsc_isa_extension>> available
999-
| 27 | `CSR_MXISA_ZCB` | r/- | <<_zcb_isa_extension>> available
1000-
| 28 | `CSR_MXISA_ZCA` | r/- | "`C` without floating-point", available when <<_c_isa_extension>> is available
1001-
| 29 | `CSR_MXISA_ZIBI` | r/- | <<_zibi_isa_extension>> available
1002-
| 31:30 | - | r/- | _reserved_, read as zero
971+
| Bit | Name [C] | R/W | Description
972+
| 0 | `CSR_MXISA_ZICSR` | r/- | <<_zicsr_isa_extension>> available
973+
| 1 | `CSR_MXISA_ZIFENCEI` | r/- | <<_zifencei_isa_extension>> available
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| 2 | `CSR_MXISA_ZMMUL` | r/- | <<_zmmul_isa_extension>> available
975+
| 3 | `CSR_MXISA_ZXCFU` | r/- | <<_zxcfu_isa_extension>> available
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| 4 | `CSR_MXISA_ZKT` | r/- | <<_zkt_isa_extension>> available
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| 5 | `CSR_MXISA_ZFINX` | r/- | <<_zfinx_isa_extension>> available
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| 6 | `CSR_MXISA_ZICOND` | r/- | <<_zicond_isa_extension>> available
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| 7 | `CSR_MXISA_ZICNTR` | r/- | <<_zicntr_isa_extension>> available
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| 8 | `CSR_MXISA_SMPMP` | r/- | <<_smpmp_isa_extension>> available
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| 9 | `CSR_MXISA_ZIHPM` | r/- | <<_zihpm_isa_extension>> available
982+
| 10 | `CSR_MXISA_SDEXT` | r/- | <<_sdext_isa_extension>> available
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| 11 | `CSR_MXISA_SDTRIG` | r/- | <<_sdtrig_isa_extension>> available
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| 12 | `CSR_MXISA_ZBKX` | r/- | <<_zbkx_isa_extension>> available
985+
| 13 | `CSR_MXISA_ZKND` | r/- | <<_zknd_isa_extension>> available
986+
| 14 | `CSR_MXISA_ZKNE` | r/- | <<_zkne_isa_extension>> available
987+
| 15 | `CSR_MXISA_ZKNH` | r/- | <<_zknh_isa_extension>> available
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| 16 | `CSR_MXISA_ZBKB` | r/- | <<_zbkb_isa_extension>> available
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| 17 | `CSR_MXISA_ZBKC` | r/- | <<_zbkc_isa_extension>> available
990+
| 18 | `CSR_MXISA_ZKN` | r/- | <<_zkn_isa_extension>> available
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| 19 | `CSR_MXISA_ZKSH` | r/- | <<_zksh_isa_extension>> available
992+
| 20 | `CSR_MXISA_ZKSED` | r/- | <<_zksed_isa_extension>> available
993+
| 21 | `CSR_MXISA_ZKS` | r/- | <<_zks_isa_extension>> available
994+
| 22 | `CSR_MXISA_ZBA` | r/- | <<_zba_isa_extension>> available
995+
| 23 | `CSR_MXISA_ZBB` | r/- | <<_zbb_isa_extension>> available
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| 24 | `CSR_MXISA_ZBS` | r/- | <<_zbs_isa_extension>> available
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| 25 | `CSR_MXISA_ZAAMO` | r/- | <<_zaamo_isa_extension>> available
998+
| 26 | `CSR_MXISA_ZALRSC` | r/- | <<_zalrsc_isa_extension>> available
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| 27 | `CSR_MXISA_ZCB` | r/- | <<_zcb_isa_extension>> available
1000+
| 28 | `CSR_MXISA_ZCA` | r/- | "`C` without floating-point", available when <<_c_isa_extension>> is available
1001+
| 29 | `CSR_MXISA_ZIBI` | r/- | <<_zibi_isa_extension>> available
1002+
| 30 | `CSR_MXISA_ZIMOP` | r/- | <<_zimop_isa_extension>> available
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| 31 | - | r/- | _reserved_, read as zero
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|=======================

‎docs/datasheet/cpu_isa.adoc‎

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@@ -21,20 +21,21 @@ This chapter gives a brief overview of all available ISA extensions.
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| <<_zaamo_isa_extension,`Zaamo`>> | Atomic read-modify-write memory operations | <<_processor_top_entity_generics, `RISCV_ISA_Zaamo`>>
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| <<_zalrsc_isa_extension,`Zalrsc`>> | Atomic reservation-set memory operations | <<_processor_top_entity_generics, `RISCV_ISA_Zalrsc`>>
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| `Zca` (_just an alias_) | Compressed instruction without floating-point operations | Implicitly enabled via <<_processor_top_entity_generics, `RISCV_ISA_C`>>
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| <<_zcb_isa_extension,`Zcb`>> | Additional code size reduction instructions (build upon `C`) | <<_processor_top_entity_generics, `RISCV_ISA_Zcb`>>
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| <<_zba_isa_extension,`Zba`>> | Shifted-add bit manipulation instructions | <<_processor_top_entity_generics, `RISCV_ISA_Zba`>>
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| <<_zbb_isa_extension,`Zbb`>> | Basic bit manipulation instructions | <<_processor_top_entity_generics, `RISCV_ISA_Zbb`>>
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| <<_zbkb_isa_extension,`Zbkb`>> | Scalar cryptography bit manipulation instructions | <<_processor_top_entity_generics, `RISCV_ISA_Zbkb`>>
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| <<_zbkc_isa_extension,`Zbkc`>> | Scalar cryptography carry-less multiplication instructions | <<_processor_top_entity_generics, `RISCV_ISA_Zbkc`>>
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| <<_zbkx_isa_extension,`Zbkx`>> | Scalar cryptography crossbar permutation instructions | <<_processor_top_entity_generics, `RISCV_ISA_Zbkx`>>
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| <<_zbs_isa_extension,`Zbs`>> | Single-bit bit manipulation instructions | <<_processor_top_entity_generics, `RISCV_ISA_Zbs`>>
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| <<_zcb_isa_extension,`Zcb`>> | Additional code size reduction instructions (build upon `C`) | <<_processor_top_entity_generics, `RISCV_ISA_Zcb`>>
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| <<_zfinx_isa_extension,`Zfinx`>> | Floating-point instructions using integer registers | <<_processor_top_entity_generics, `RISCV_ISA_Zfinx`>>
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| <<_zifencei_isa_extension,`Zifencei`>> | Instruction stream synchronization instruction | Always enabled
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| <<_zibi_isa_extension,`Zibi`>> | Branches with immediate-comparison | <<_processor_top_entity_generics, `RISCV_ISA_Zibi`>>
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| <<_zicntr_isa_extension,`Zicntr`>> | Base counters extension | <<_processor_top_entity_generics, `RISCV_ISA_Zicntr`>>
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| <<_zicond_isa_extension,`Zicond`>> | Integer conditional operations | <<_processor_top_entity_generics, `RISCV_ISA_Zicond`>>
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| <<_zicsr_isa_extension,`Zicsr`>> | Control and status register access instructions | Always enabled
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| <<_zihpm_isa_extension,`Zihpm`>> | Hardware performance monitors extension | <<_processor_top_entity_generics, `RISCV_ISA_Zihpm`>>
38+
| <<_zimop_isa_extension,`Zimop`>> | May-be-operations | <<_processor_top_entity_generics, `RISCV_ISA_Zimop`>>
3839
| <<_zkn_isa_extension,`Zkn`>> | Scalar cryptography NIST algorithm suite | _Implicitly_ enabled
3940
| <<_zknd_isa_extension,`Zknd`>> | Scalar cryptography NIST AES decryption instructions | <<_processor_top_entity_generics, `RISCV_ISA_Zknd`>>
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| <<_zkne_isa_extension,`Zkne`>> | Scalar cryptography NIST AES encryption instructions | <<_processor_top_entity_generics, `RISCV_ISA_Zkne`>>
@@ -285,6 +286,7 @@ Technically, `Zbc` required the `Zca` extension which is `C` but excluding the f
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Therefore, `Zca` and `Zbc` must be contained in the ISA string so that the compiler generates `Zbc` instructions..
286287
Example: `MARCH=rv32imc_zca_zcb_...`
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==== `Zifencei` ISA Extension
289291

290292
This instruction is the only standard mechanism to ensure that stores visible to a hart will also be visible to its
@@ -428,6 +430,22 @@ Accessing any user-mode HPM CSR (`hpmcounter*[h]`) will raise an illegal instruc
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The event-driven increment of the HPMs can be deactivated individually via the <<_mcountinhibit>> CSR.
429431

430432

433+
==== `Zimop` ISA Extension
434+
435+
The `Zimop` ISA extension introduces the concept of instructions that may be operations (MOPs). MOPs are initially
436+
defined to simply write zero to the destination register, but are designed to be redefined by later extensions to
437+
perform some other system/environment-class actions. NEORV32 can implement this ISA extension for software compatibility.
438+
Without the `Zimop` extension, any `mop.r*` instruction will raise an illegal instruction exception.
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440+
.Instructions and Timing
441+
[cols="<2,<5,<4"]
442+
[options="header", grid="rows"]
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|=======================
444+
| Class | Instructions | Execution cycles
445+
| System | `mop.r.[0..31]` `mop.rr.[0..7]` | 3
446+
|=======================
447+
448+
431449
==== `Zba` ISA Extension
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The `Zba` sub-extension is part of the _RISC-V bit manipulation_ ISA specification (<<_b_isa_extension>>)

‎docs/datasheet/soc.adoc‎

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@@ -224,18 +224,19 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
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| `RISCV_ISA_U` | boolean | false | Enable <<_u_isa_extension>> (less-privileged user mode).
225225
| `RISCV_ISA_Zaamo` | boolean | false | Enable <<_zaamo_isa_extension>> (atomic read-modify-write operations).
226226
| `RISCV_ISA_Zalrsc` | boolean | false | Enable <<_zalrsc_isa_extension>> (atomic reservation-set operations).
227-
| `RISCV_ISA_Zcb` | boolean | false | Enable <<_zcb_isa_extension>> (additional code size reduction instruction; builds upon `C`).
228227
| `RISCV_ISA_Zba` | boolean | false | Enable <<_zba_isa_extension>> (shifted-add bit-manipulation instructions).
229228
| `RISCV_ISA_Zbb` | boolean | false | Enable <<_zbb_isa_extension>> (basic bit-manipulation instructions).
230229
| `RISCV_ISA_Zbkb` | boolean | false | Enable <<_zbkb_isa_extension>> (scalar cryptography bit manipulation instructions).
231230
| `RISCV_ISA_Zbkc` | boolean | false | Enable <<_zbkc_isa_extension>> (scalar cryptography carry-less multiplication instructions).
232231
| `RISCV_ISA_Zbkx` | boolean | false | Enable <<_zbkx_isa_extension>> (scalar cryptography crossbar permutations).
233232
| `RISCV_ISA_Zbs` | boolean | false | Enable <<_zbs_isa_extension>> (single-bit bit-manipulation instructions).
233+
| `RISCV_ISA_Zcb` | boolean | false | Enable <<_zcb_isa_extension>> (additional code size reduction instruction; builds upon `C`).
234234
| `RISCV_ISA_Zfinx` | boolean | false | Enable <<_zfinx_isa_extension>> (single-precision floating-point unit).
235235
| `RISCV_ISA_Zibi` | boolean | false | Enable <<_zibi_isa_extension>> (CPU base counters).
236236
| `RISCV_ISA_Zicntr` | boolean | false | Enable <<_zicntr_isa_extension>> (CPU base counters).
237237
| `RISCV_ISA_Zicond` | boolean | false | Enable <<_zicond_isa_extension>> (integer conditional instructions).
238238
| `RISCV_ISA_Zihpm` | boolean | false | Enable <<_zihpm_isa_extension>> (hardware performance monitors).
239+
| `RISCV_ISA_Zimop` | boolean | false | Enable <<_zimop_isa_extension>> (may-be-operations).
239240
| `RISCV_ISA_Zknd` | boolean | false | Enable <<_zknd_isa_extension>> (scalar cryptography NIST AES decryption instructions).
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| `RISCV_ISA_Zkne` | boolean | false | Enable <<_zkne_isa_extension>> (scalar cryptography NIST AES encryption instructions).
241242
| `RISCV_ISA_Zknh` | boolean | false | Enable <<_zknh_isa_extension>> (scalar cryptography NIST hash instructions).

‎docs/figures/neorv32_processor.png‎

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‎rtl/core/neorv32_cpu.vhd‎

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@@ -33,18 +33,19 @@ entity neorv32_cpu is
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RISCV_ISA_U : boolean; -- user mode extension
3434
RISCV_ISA_Zaamo : boolean; -- atomic read-modify-write operations extension
3535
RISCV_ISA_Zalrsc : boolean; -- atomic reservation-set operations extension
36-
RISCV_ISA_Zcb : boolean; -- additional code size reduction instructions
3736
RISCV_ISA_Zba : boolean; -- shifted-add bit-manipulation extension
3837
RISCV_ISA_Zbb : boolean; -- basic bit-manipulation extension
3938
RISCV_ISA_Zbkb : boolean; -- bit-manipulation instructions for cryptography
4039
RISCV_ISA_Zbkc : boolean; -- carry-less multiplication instructions
4140
RISCV_ISA_Zbkx : boolean; -- cryptography crossbar permutation extension
4241
RISCV_ISA_Zbs : boolean; -- single-bit bit-manipulation extension
42+
RISCV_ISA_Zcb : boolean; -- additional code size reduction instructions
4343
RISCV_ISA_Zfinx : boolean; -- 32-bit floating-point extension
4444
RISCV_ISA_Zibi : boolean; -- branch with immediate
4545
RISCV_ISA_Zicntr : boolean; -- base counters
4646
RISCV_ISA_Zicond : boolean; -- integer conditional operations
4747
RISCV_ISA_Zihpm : boolean; -- hardware performance monitors
48+
RISCV_ISA_Zimop : boolean; -- may-be-operations
4849
RISCV_ISA_Zknd : boolean; -- cryptography NIST AES decryption extension
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RISCV_ISA_Zkne : boolean; -- cryptography NIST AES encryption extension
5051
RISCV_ISA_Zknh : boolean; -- cryptography NIST hash extension
@@ -155,13 +156,14 @@ begin
155156
cond_sel_string_f(RISCV_ISA_Zbkc, "_zbkc", "" ) &
156157
cond_sel_string_f(RISCV_ISA_Zbkx, "_zbkx", "" ) &
157158
cond_sel_string_f(RISCV_ISA_Zbs, "_zbs", "" ) &
159+
cond_sel_string_f(RISCV_ISA_Zfinx, "_zfinx", "" ) &
158160
cond_sel_string_f(RISCV_ISA_Zibi, "_zibi", "" ) &
159161
cond_sel_string_f(RISCV_ISA_Zicntr, "_zicntr", "" ) &
160162
cond_sel_string_f(RISCV_ISA_Zicond, "_zicond", "" ) &
161163
cond_sel_string_f(true, "_zicsr", "" ) & -- always enabled
162164
cond_sel_string_f(true, "_zifencei", "" ) & -- always enabled
163165
cond_sel_string_f(RISCV_ISA_Zihpm, "_zihpm", "" ) &
164-
cond_sel_string_f(RISCV_ISA_Zfinx, "_zfinx", "" ) &
166+
cond_sel_string_f(RISCV_ISA_Zimop, "_zimop", "" ) &
165167
cond_sel_string_f(riscv_zkn_c, "_zkn", "" ) &
166168
cond_sel_string_f(RISCV_ISA_Zknd, "_zknd", "" ) &
167169
cond_sel_string_f(RISCV_ISA_Zkne, "_zkne", "" ) &
@@ -239,6 +241,7 @@ begin
239241
RISCV_ISA_Zicntr => RISCV_ISA_Zicntr, -- base counters
240242
RISCV_ISA_Zicond => RISCV_ISA_Zicond, -- integer conditional operations
241243
RISCV_ISA_Zihpm => RISCV_ISA_Zihpm, -- hardware performance monitors
244+
RISCV_ISA_Zimop => RISCV_ISA_Zimop, -- may-be-operations
242245
RISCV_ISA_Zkn => riscv_zkn_c, -- NIST algorithm suite available
243246
RISCV_ISA_Zknd => RISCV_ISA_Zknd, -- cryptography NIST AES decryption extension
244247
RISCV_ISA_Zkne => RISCV_ISA_Zkne, -- cryptography NIST AES encryption extension

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