🚀 preparing release v1.11.5

Author: stnolting

CHANGELOG.md

@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 22.05.2025 | [**:rocket:1.11.5**](https://github.com/stnolting/neorv32/releases/tag/v1.11.5) | **New release** | |
 | 17.05.2025 | 1.11.4.9 | :bug: fix CPU's `lock` being cleared too early during atomic read-modify-write operations; :bug: fix cache's `ben` signal generation | [#1270](https://github.com/stnolting/neorv32/pull/1270) |
 | 16.05.2025 | 1.11.4.8 | :warning: remove hardware spinlocks and CPU's inter-core communication links | [#1268](https://github.com/stnolting/neorv32/pull/1268) |
 | 16.05.2025 | 1.11.4.7 | :warning: make `mcause` CSR read-only | [#1267](https://github.com/stnolting/neorv32/pull/1267) |

docs/attrs.adoc

@@ -2,7 +2,7 @@
 :email: [email protected]
 :keywords: neorv32, risc-v, riscv, rv32, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb, verilog, rtl, asip, asic
 :description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
-:revnumber: v1.11.4
+:revnumber: v1.11.5
 :icons: font
 :source-highlighter: highlight.js
 :imagesdir: ../figures

rtl/core/neorv32_package.vhd

@@ -29,7 +29,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110409"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110500"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width
 
@@ -766,7 +766,6 @@ package neorv32_package is
   function replicate_f(input : std_ulogic; num : natural) return std_ulogic_vector;
   impure function mem32_init_f(init : mem32_t; depth : natural) return mem32_t;
   function print_version_f(version : std_ulogic_vector(31 downto 0)) return string;
-  function match_f(input : std_ulogic_vector; pattern : std_ulogic_vector) return boolean;
 
 -- **********************************************************************************************************
 -- NEORV32 Processor Top Entity (component prototype)
@@ -1220,23 +1219,4 @@ package body neorv32_package is
     return res_v;
   end function print_version_f;
 
-  -- Check if signal matches binary pattern (skip elements compared with '-') ---------------
-  -- -------------------------------------------------------------------------------------------
-  function match_f(input : std_ulogic_vector; pattern : std_ulogic_vector) return boolean is
-    variable match_v : boolean;
-  begin
-    if (input'length /= pattern'length) then
-      report "[NEORV32] match_f: input and pattern have different sizes!" severity error;
-      return false;
-    else
-      match_v := true;
-      for i in input'length-1 downto 0 loop
-        if (pattern(i) = '1') or (pattern(i) = '0') then -- valid pattern value, skip everything else
-          match_v := match_v and boolean(pattern(i) = input(i));
-        end if;
-      end loop;
-      return match_v;
-    end if;
-  end function match_f;
-
 end neorv32_package;

sw/svd/neorv32.svd

@@ -4,7 +4,7 @@
   <vendor>stnolting</vendor>
   <name>neorv32</name>
   <series>RISC-V</series>
-  <version>1.11.4</version>
+  <version>1.11.5</version>
   <description>The NEORV32 RISC-V Processor</description>
 
   <!-- CPU core -->