Added a test case to show the 1.0 + -1.0 instruction time-out under f… (#592)

Author: stnolting

CHANGELOG.md

@@ -33,6 +33,7 @@ mimpid = 0x01080200 => Version 01.08.02.00 => v1.8.2
 
 | Date (*dd.mm.yyyy*) | Version | Comment |
 |:-------------------:|:-------:|:--------|
+| 21.04.2023 | 1.8.3.9 | :bug: fix timeout bug in **FPU** normalizer; [#592](https://github.com/stnolting/neorv32/pull/592) |
 | 19.04.2023 | 1.8.3.8 | minor processor bus system optimizations and clean-ups; [#591](https://github.com/stnolting/neorv32/pull/591) |
 | 15.04.2023 | 1.8.3.7 | :bug: :warning: `wfi` and XIRQ bug fixes; massive RTL code cleanup and optimization of CPU control; [#586](https://github.com/stnolting/neorv32/pull/586) |
 | 14.04.2023 | 1.8.3.6 | [UARTs] software can now retrieve the configured RX/TX FIFO sizes from the `DATA` register; [#581](https://github.com/stnolting/neorv32/pull/581) |

rtl/core/neorv32_cpu_cp_fpu.vhd

@@ -1358,6 +1358,14 @@ begin
                ctrl.flags(fp_exc_of_c) or -- overflow
                ctrl.flags(fp_exc_nv_c)) = '1') then -- invalid
             ctrl.state <= S_FINALIZE;
+          -- The normalizer only checks the class of the inputs and not the result.
+          -- Check whether adder result is 0.0 which can happen if eg. 1.0 - 1.0
+          -- Set the ctrl.cnt to 0 to force the resulting exponent to be 0
+          -- Do not change sreg.lower as that is already all 0s
+          -- Do not change sign as that should be the right sign from the add/sub
+          elsif (unsigned(mantissa_i(47 downto 0)) = 0) then 
+            ctrl.cnt <= (others => '0');
+            ctrl.state <= S_FINALIZE;
           else
             ctrl.state <= S_PREPARE_SHIFT;
           end if;

rtl/core/neorv32_package.vhd

@@ -60,7 +60,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080308"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080309"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width, do not change!
 

sw/example/float_corner_test/main.c

@@ -150,6 +150,35 @@ int main() {
   neorv32_cpu_csr_write(CSR_FFLAGS, 0); // real hardware
   feclearexcept(FE_ALL_EXCEPT); // software runtime (GCC floating-point emulation)
 
+// ----------------------------------------------------------------------------
+// Floating point add/sub Instruction Time-out test
+// ----------------------------------------------------------------------------
+
+  neorv32_uart0_printf("\n#%u: FADD.S (Floating point add)...\n", test_cnt);
+
+// Test the addition of 1.0 + (-1.0) to trigger long normalizer times
+// +1.0 e0
+// 0_011 1111 1_000 0000 0000 0000 0000 0000
+// sign 0, exp 0111_1111/0x7F, mant 0 => 1.0
+// 0x3F80_0000
+
+  neorv32_cpu_csr_write(CSR_MCAUSE, 0);
+  opa.binary_value = 0x3F800000;
+
+// -1.0 e0
+// 1_011 1111 1_000 0000 0000 0000 0000 0000
+// sign 1, exp 0111_1111/0x7F, mant 0 => 1.0
+// 0xBF80_0000
+
+  opb.binary_value = 0xBF800000;
+  riscv_intrinsic_fadds(opa.float_value,opb.float_value);
+
+  if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
+    neorv32_uart0_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
+    neorv32_uart0_printf("Addition of 1.0 + (-1.0) timed out\n");
+    err_cnt_total++;
+  }
+  test_cnt++;
 
 // ----------------------------------------------------------------------------
 // Conversion Tests Instruction Time-out test