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🐛 fix enabling of Zbkx ISA extension (#1486)
2 parents 2cdcad9 + 3c501e4 commit 8121aed

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-63
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7 files changed

+67
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‎CHANGELOG.md‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
2929

3030
| Date | Version | Comment | Ticket |
3131
|:----:|:-------:|:--------|:------:|
32+
| 30.01.2025 | 1.12.7.5 | :bug: fix enabling of `Zbkx` ISA extension | [#1486](https://github.com/stnolting/neorv32/pull/1486) |
3233
| 22.01.2025 | 1.12.7.4 | :warning: rework memory image files | [#1482](https://github.com/stnolting/neorv32/pull/1482) |
3334
| 18.01.2025 | 1.12.7.3 | :sparkles: encapsulate memory components; caches: use block invalidation when a bus error occurs during block download | [#1481](https://github.com/stnolting/neorv32/pull/1481) |
3435
| 18.01.2025 | 1.12.7.2 | :bug: fix `csrr[r/c][i]` instructions: do not write CSR if `rs1/imm5` is not zero | [#1479](https://github.com/stnolting/neorv32/pull/1479) |
@@ -603,4 +604,4 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
603604
| 29.06.2022 | 1.7.3.2 | :test_tube: add experimental core complex wrapper for integration into the [**LiteX**](https://github.com/enjoy-digital/litex) SoC builder framework | [#353](https://github.com/stnolting/neorv32/pull/353) |
604605
| 28.06.2022 | 1.7.3.1 | :bug: fix bug that caused permanent CPU stall if illegal load/store instruction | [#356](https://github.com/stnolting/neorv32/pull/356) |
605606
| 23.06.2022 | [**1.7.3**](https://github.com/stnolting/neorv32/releases/tag/v1.7.3) | :rocket: **New release** | |
606-
| ... | ... | Changelog trimmed. See [`CHANGELOG.md` in v1.7.3](https://github.com/stnolting/neorv32/blob/v1.7.3/CHANGELOG.md) for older logs. | ... |
607+
| ... | ... | Change log trimmed. See [`CHANGELOG.md` in v1.7.3](https://github.com/stnolting/neorv32/blob/v1.7.3/CHANGELOG.md) for older logs. | ... |

‎rtl/core/neorv32_cache.vhd‎

Lines changed: 17 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -234,16 +234,15 @@ begin
234234

235235
when S_DOWNLOAD_START => -- start block download / send single request (if no bursts)
236236
-- ------------------------------------------------------------
237-
cache_o.addr <= ctrl.tag_idx & ctrl.ofs_int & "00";
238237
bus_req_o.addr <= ctrl.tag_idx & ctrl.ofs_ext(offset_width_c-1 downto 0) & "00";
239238
bus_req_o.rw <= '0'; -- read access
240-
bus_req_o.stb <= '1'; -- send initial (burst/locking) request
239+
bus_req_o.stb <= '1'; -- send (initial burst/locking) request
241240
bus_req_o.lock <= '1'; -- this is a locked transfer
242241
bus_req_o.burst <= bool_to_ulogic_f(bursts_en_c); -- this is a burst transfer
243242
bus_req_o.ben <= (others => '1'); -- full-word access
244243
ctrl_nxt.state <= S_DOWNLOAD_WAIT;
245244

246-
when S_DOWNLOAD_WAIT => -- wait for exclusive (=locked) bus access / response
245+
when S_DOWNLOAD_WAIT => -- wait for exclusive/locked bus access
247246
-- ------------------------------------------------------------
248247
cache_o.addr <= ctrl.tag_idx & ctrl.ofs_int & "00";
249248
cache_o.data <= bus_rsp_i.data;
@@ -373,6 +372,21 @@ begin
373372
end generate;
374373

375374

375+
-- Cache Hit Check ------------------------------------------------------------------------
376+
-- -------------------------------------------------------------------------------------------
377+
tag_buffer: process(rstn_i, clk_i)
378+
begin
379+
if (rstn_i = '0') then
380+
tag_reg <= (others => '0');
381+
elsif rising_edge(clk_i) then
382+
tag_reg <= cache_o.addr(31 downto 31-(tag_width_c-1));
383+
end if;
384+
end process tag_buffer;
385+
386+
-- cache hit --
387+
cache_i.hit <= '1' when (valid_rd = '1') and (tag_rd(tag_width_c-1 downto 0) = tag_reg) else '0';
388+
389+
376390
-- Cache Tag and Data Memory (Wrapper) ----------------------------------------------------
377391
-- -------------------------------------------------------------------------------------------
378392
neorv32_cache_ram_inst: neorv32_cache_ram
@@ -391,19 +405,4 @@ begin
391405
data_o => cache_i.data
392406
);
393407

394-
395-
-- Cache Hit Check ------------------------------------------------------------------------
396-
-- -------------------------------------------------------------------------------------------
397-
tag_buffer: process(rstn_i, clk_i)
398-
begin
399-
if (rstn_i = '0') then
400-
tag_reg <= (others => '0');
401-
elsif rising_edge(clk_i) then
402-
tag_reg <= cache_o.addr(31 downto 31-(tag_width_c-1));
403-
end if;
404-
end process tag_buffer;
405-
406-
-- cache hit --
407-
cache_i.hit <= '1' when (valid_rd = '1') and (tag_rd(tag_width_c-1 downto 0) = tag_reg) else '0';
408-
409408
end neorv32_cache_rtl;

‎rtl/core/neorv32_cpu.vhd‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -200,6 +200,10 @@ begin
200200
cond_sel_string_f(boolean(CPU_RF_ARCH_SEL = 3), "rf_arch=latch ", "")
201201
severity note;
202202

203+
-- ISA configuration checks --
204+
assert not (RISCV_ISA_Zcb and (not RISCV_ISA_C)) report
205+
"[NEORV32] CPU ISA: Zcb requires C!" severity error;
206+
203207
end generate;
204208

205209

‎rtl/core/neorv32_cpu_alu.vhd‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -190,7 +190,7 @@ begin
190190
-- ALU[I]-Opcode Co-Processor: Bit-Manipulation Unit ('B' ISA Extension) ------------------
191191
-- -------------------------------------------------------------------------------------------
192192
neorv32_cpu_alu_bitmanip_enabled:
193-
if RISCV_ISA_Zba or RISCV_ISA_Zbb or RISCV_ISA_Zbkb or RISCV_ISA_Zbs or RISCV_ISA_Zbkc generate
193+
if RISCV_ISA_Zba or RISCV_ISA_Zbb or RISCV_ISA_Zbkb or RISCV_ISA_Zbkc or RISCV_ISA_Zbkx or RISCV_ISA_Zbs generate
194194
neorv32_cpu_alu_bitmanip_inst: entity neorv32.neorv32_cpu_alu_bitmanip
195195
generic map (
196196
FAST_SHIFT => FAST_SHIFT_EN, -- use barrel shifter for shift operations
@@ -218,7 +218,7 @@ begin
218218
end generate;
219219

220220
neorv32_cpu_alu_bitmanip_disabled:
221-
if not (RISCV_ISA_Zba or RISCV_ISA_Zbb or RISCV_ISA_Zbkb or RISCV_ISA_Zbs or RISCV_ISA_Zbkc) generate
221+
if not (RISCV_ISA_Zba or RISCV_ISA_Zbb or RISCV_ISA_Zbkb or RISCV_ISA_Zbkc or RISCV_ISA_Zbkx or RISCV_ISA_Zbs) generate
222222
cp_result(2) <= (others => '0');
223223
cp_valid(2) <= '0';
224224
end generate;
@@ -346,12 +346,12 @@ begin
346346
-- ALU[I]-Opcode Co-Processor: Scalar Cryptography Unit ('Zk*' ISA Extensions) ------------
347347
-- -------------------------------------------------------------------------------------------
348348
neorv32_cpu_alu_crypto_enabled:
349-
if RISCV_ISA_Zbkx or RISCV_ISA_Zknh or RISCV_ISA_Zkne or RISCV_ISA_Zknd or RISCV_ISA_Zksh or RISCV_ISA_Zksed generate
349+
if RISCV_ISA_Zknd or RISCV_ISA_Zkne or RISCV_ISA_Zknh or RISCV_ISA_Zksed or RISCV_ISA_Zksh generate
350350
neorv32_cpu_alu_crypto_inst: entity neorv32.neorv32_cpu_alu_crypto
351351
generic map (
352-
EN_ZKNH => RISCV_ISA_Zknh, -- enable NIST hash extension
353-
EN_ZKNE => RISCV_ISA_Zkne, -- enable NIST AES encryption extension
354352
EN_ZKND => RISCV_ISA_Zknd, -- enable NIST AES decryption extension
353+
EN_ZKNE => RISCV_ISA_Zkne, -- enable NIST AES encryption extension
354+
EN_ZKNH => RISCV_ISA_Zknh, -- enable NIST hash extension
355355
EN_ZKSED => RISCV_ISA_Zksed, -- enable ShangMi block cypher extension
356356
EN_ZKSH => RISCV_ISA_Zksh -- enable ShangMi hash extension
357357
)
@@ -370,7 +370,7 @@ begin
370370
end generate;
371371

372372
neorv32_cpu_alu_crypto_disabled:
373-
if not (RISCV_ISA_Zbkx or RISCV_ISA_Zknh or RISCV_ISA_Zkne or RISCV_ISA_Zknd or RISCV_ISA_Zksh or RISCV_ISA_Zksed) generate
373+
if not (RISCV_ISA_Zknd or RISCV_ISA_Zkne or RISCV_ISA_Zknh or RISCV_ISA_Zksed or RISCV_ISA_Zksh) generate
374374
cp_result(6) <= (others => '0');
375375
cp_valid(6) <= '0';
376376
end generate;

‎rtl/core/neorv32_cpu_alu_crypto.vhd‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,9 @@
22
-- NEORV32 CPU - ALU Scalar Cryptography Unit (RISC-V Zk* ISA Extensions) --
33
-- -------------------------------------------------------------------------------- --
44
-- Supported sub-extensions: --
5-
-- + Zknh: NIST suite's hash functions --
6-
-- + Zkne: NIST suite's AES encryption --
75
-- + Zknd: NIST suite's AES decryption --
6+
-- + Zkne: NIST suite's AES encryption --
7+
-- + Zknh: NIST suite's hash functions --
88
-- + Zksed: ShangMi suite's block ciphers --
99
-- + Zksh: ShangMi suite's hash functions --
1010
-- -------------------------------------------------------------------------------- --
@@ -24,9 +24,9 @@ use neorv32.neorv32_package.all;
2424

2525
entity neorv32_cpu_alu_crypto is
2626
generic (
27-
EN_ZKNH : boolean; -- enable NIST hash extension
28-
EN_ZKNE : boolean; -- enable NIST AES encryption extension
2927
EN_ZKND : boolean; -- enable NIST AES decryption extension
28+
EN_ZKNE : boolean; -- enable NIST AES encryption extension
29+
EN_ZKNH : boolean; -- enable NIST hash extension
3030
EN_ZKSED : boolean; -- enable ShangMi block cipher extension
3131
EN_ZKSH : boolean -- enable ShangMi hash extension
3232
);

‎rtl/core/neorv32_cpu_control.vhd‎

Lines changed: 33 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -229,9 +229,9 @@ begin
229229
trap.ecall <= '0';
230230
trap.ebreak <= '0';
231231
ctrl_nxt <= ctrl_bus_zero_c; -- all zero/off by default (ALU operation = ZERO, ALU.adder_out = ADD)
232-
ctrl_nxt.csr_addr <= ctrl.csr_addr; -- keep previous CSR address
233-
ctrl_nxt.lsu_rd <= ctrl.lsu_rd; -- keep memory access read/write type
234-
ctrl_nxt.lsu_wr <= ctrl.lsu_wr;
232+
ctrl_nxt.csr_addr <= ctrl.csr_addr; -- keep previous CSR address
233+
ctrl_nxt.lsu_rd <= ctrl.lsu_rd; -- keep memory read access type
234+
ctrl_nxt.lsu_wr <= ctrl.lsu_wr; -- keep memory write access type
235235

236236
-- immediate --
237237
case opcode_v is
@@ -794,6 +794,35 @@ begin
794794
(trap.ebreak and (not csr.prv_level) and (not csr.dcsr_ebreaku) and (not debug_ctrl.run)); -- M-mode trap on U-ebreak
795795

796796

797+
-- Trap Triggers --------------------------------------------------------------------------
798+
-- -------------------------------------------------------------------------------------------
799+
trap_pending: process(rstn_i, clk_i)
800+
begin
801+
if (rstn_i = '0') then
802+
trap.env_pend <= '0';
803+
elsif rising_edge(clk_i) then
804+
if (trap.env_enter = '1') then -- start of trap environment acknowledged by execute engine
805+
trap.env_pend <= '0';
806+
elsif (trap.exc_fire = '1') or (or_reduce_f(trap.irq_fire) = '1') then -- trap trigger
807+
trap.env_pend <= '1';
808+
end if;
809+
end if;
810+
end process trap_pending;
811+
812+
-- any sync. exception? --
813+
trap.exc_fire <= or_reduce_f(trap.exc_buf); -- cannot be masked
814+
815+
-- any system interrupt? --
816+
trap.irq_fire(0) <= '1' when
817+
((exec.state = S_EXECUTE) or (exec.state = S_SLEEP)) and -- trigger system IRQ only in S_EXECUTE state or in sleep mode
818+
(or_reduce_f(trap.irq_buf(irq_firq_15_c downto irq_msi_irq_c)) = '1') and -- pending system IRQ
819+
((csr.mstatus_mie = '1') or (csr.prv_level = priv_mode_u_c)) and -- IRQ only when in M-mode and MIE=1 OR when in U-mode
820+
(debug_ctrl.run = '0') and (csr.dcsr_step = '0') else '0'; -- no system IRQs when in debug-mode / during single-stepping
821+
822+
-- debug-entry halt interrupt? allow halt also after "reset" (#879) --
823+
trap.irq_fire(1) <= trap.irq_buf(irq_db_halt_c) when (exec.state = S_RESTART) or (exec.state = S_EXECUTE) or (exec.state = S_SLEEP) else '0';
824+
825+
797826
-- Trap Priority Encoder ------------------------------------------------------------------
798827
-- -------------------------------------------------------------------------------------------
799828
trap.cause <=
@@ -807,7 +836,7 @@ begin
807836
trap_lma_c when (trap.exc_buf(exc_lalign_c) = '1') else -- load address misaligned
808837
trap_saf_c when (trap.exc_buf(exc_saccess_c) = '1') else -- store access fault
809838
trap_laf_c when (trap.exc_buf(exc_laccess_c) = '1') else -- load access fault
810-
-- standard RISC-V debug mode traps --
839+
-- standard RISC-V debug-mode traps --
811840
trap_db_halt_c when (trap.irq_buf(irq_db_halt_c) = '1') else -- external halt request
812841
trap_db_trig_c when (trap.exc_buf(exc_db_trig_c) = '1') else -- hardware trigger
813842
trap_db_brkp_c when (trap.exc_buf(exc_db_brkp_c) = '1') else -- breakpoint
@@ -841,35 +870,6 @@ begin
841870
trap.pc <= exec.pc2 when (trap.cause(trap.cause'left) = '1') else exec.pc;
842871

843872

844-
-- Trap Triggers --------------------------------------------------------------------------
845-
-- -------------------------------------------------------------------------------------------
846-
trap_pending: process(rstn_i, clk_i)
847-
begin
848-
if (rstn_i = '0') then
849-
trap.env_pend <= '0';
850-
elsif rising_edge(clk_i) then
851-
if (trap.env_enter = '1') then -- start of trap environment acknowledged by execute engine
852-
trap.env_pend <= '0';
853-
elsif (trap.exc_fire = '1') or (or_reduce_f(trap.irq_fire) = '1') then -- trap trigger
854-
trap.env_pend <= '1';
855-
end if;
856-
end if;
857-
end process trap_pending;
858-
859-
-- any sync. exception? --
860-
trap.exc_fire <= or_reduce_f(trap.exc_buf); -- cannot be masked
861-
862-
-- any system interrupt? --
863-
trap.irq_fire(0) <= '1' when
864-
((exec.state = S_EXECUTE) or (exec.state = S_SLEEP)) and -- trigger system IRQ only in S_EXECUTE state or in sleep mode
865-
(or_reduce_f(trap.irq_buf(irq_firq_15_c downto irq_msi_irq_c)) = '1') and -- pending system IRQ
866-
((csr.mstatus_mie = '1') or (csr.prv_level = priv_mode_u_c)) and -- IRQ only when in M-mode and MIE=1 OR when in U-mode
867-
(debug_ctrl.run = '0') and (csr.dcsr_step = '0') else '0'; -- no system IRQs when in debug-mode / during single-stepping
868-
869-
-- debug-entry halt interrupt? allow halt also after "reset" (#879) --
870-
trap.irq_fire(1) <= trap.irq_buf(irq_db_halt_c) when (exec.state = S_RESTART) or (exec.state = S_EXECUTE) or (exec.state = S_SLEEP) else '0';
871-
872-
873873
-- Debug-Mode Control ---------------------------------------------------------------------
874874
-- -------------------------------------------------------------------------------------------
875875
debug_mode_enabled:

‎rtl/core/neorv32_package.vhd‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ package neorv32_package is
2020

2121
-- Architecture Constants -----------------------------------------------------------------
2222
-- -------------------------------------------------------------------------------------------
23-
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01120704"; -- hardware version
23+
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01120705"; -- hardware version
2424
constant int_bus_tmo_c : natural := 16; -- internal bus timeout window; has to be a power of two
2525
constant alu_cp_tmo_c : natural := 9; -- log2 of max ALU co-processor execution cycles
2626

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