🚀 preparing release v1.12.6

Author: stnolting

CHANGELOG.md

@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 27.12.2025 | [**1.12.6**](https://github.com/stnolting/neorv32/releases/tag/v1.12.6) | :rocket: **New release** | |
 | 24.12.2025 | 1.12.5.9 | minor rtl cleanups | [#1461](https://github.com/stnolting/neorv32/pull/1461) |
 | 23.12.2025 | 1.12.5.8 | :sparkles: add new tuning option `CPU_RF_ARCH_SEL` to select implementation style of CPU register file (FPGA block RAM, FPGA distributed RAM, individual FFs, individual latches) | [#1460](https://github.com/stnolting/neorv32/pull/1460) |
 | 21.12.2025 | 1.12.5.7 | :warning: remove `mxcsr` CSR | [#1459](https://github.com/stnolting/neorv32/pull/1459) |

docs/attrs.adoc

@@ -1,6 +1,6 @@
 :keywords: neorv32, risc-v, fpga, soft-core, microcontroller, cpu, soc, processor, asip
 :description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
-:revnumber: v1.12.5
+:revnumber: v1.12.6
 :icons: font
 :source-highlighter: highlight.js
 :imagesdir: ../figures

rtl/core/neorv32_package.vhd

@@ -20,7 +20,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c  : std_ulogic_vector(31 downto 0) := x"01120509"; -- hardware version
+  constant hw_version_c  : std_ulogic_vector(31 downto 0) := x"01120600"; -- hardware version
   constant archid_c      : natural := 19; -- official RISC-V architecture ID
   constant int_bus_tmo_c : natural := 16; -- internal bus timeout window; has to be a power of two
   constant alu_cp_tmo_c  : natural := 9;  -- log2 of max ALU co-processor execution cycles

sw/svd/neorv32.svd

@@ -4,7 +4,7 @@
   <vendor>github.com/stnolting/neorv32</vendor>
   <name>neorv32</name>
   <series>RISC-V</series>
-  <version>1.12.5</version>
+  <version>1.12.6</version>
   <description>The NEORV32 RISC-V Processor</description>
 
   <!-- CPU core -->