[docs] remove per-module FPGA results

they are just outdated

Author: stnolting

docs/datasheet/overview.adoc

@@ -352,59 +352,6 @@ See section <<_processor_top_entity_generics>> for more information. Also, take
 https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration].
 
 
-[discrete]
-==== Processor - Modules
-
-[cols="<2,<8"]
-[grid="topbot"]
-|=======================
-| HW version:  | `1.8.6.7`
-| Top entity:  | `rtl/core/neorv32_top.vhd`
-| FPGA:        | Intel Cyclone IV E `EP4CE22F17C6`
-| Toolchain:   | Quartus Prime Lite 21.1
-| Constraints: | **no timing constraints**, "balanced optimization"
-|=======================
-
-.Hardware utilization by processor module
-[cols="<2,<8,>1,>1,>2,>1"]
-[options="header",grid="rows"]
-|=======================
-| Module            | Description                                                    | LEs | FFs | MEM bits | DSPs
-| BOOT ROM          | Bootloader ROM (4kB)                                           |   2 |   2 |    32768 |    0
-| Bus switch (core) | _SoC bus infrastructure_                                       |  28 |  15 |        0 |    0
-| Bus switch (DMA)  | _SoC bus infrastructure_                                       | 159 |   9 |        0 |    0
-| CFS               | Custom functions subsystem (depends on custom design logic)    |   - |   - |        - |    -
-| CRC               | Cyclic redundancy check unit                                   | 130 | 117 |        0 |    0
-| dCACHE            | Data cache (4 blocks, 64 bytes per block)                      | 300 | 167 |     2112 |    0
-| DM                | On-chip debugger - debug module                                | 377 | 241 |        0 |    0
-| DTM               | On-chip debugger - debug transfer module (JTAG)                | 262 | 220 |        0 |    0
-| DMA               | Direct memory access controller                                | 365 | 291 |        0 |    0
-| DMEM              | Processor-internal data memory (8kB)                           |   6 |   2 |    65536 |    0
-| Gateway           | _SoC bus infrastructure_                                       | 215 |  91 |        0 |    0
-| GPIO              | General purpose input/output ports                             | 102 |  98 |        0 |    0
-| GPTMR             | General Purpose Timer                                          | 150 | 105 |        0 |    0
-| IO Switch         | _SoC bus infrastructure_                                       | 217 |   0 |        0 |    0
-| iCACHE            | Instruction cache (2x4 blocks, 64 bytes per block)             | 458 | 296 |     4096 |    0
-| IMEM              | Processor-internal instruction memory (16kB)                   |   7 |   2 |   131072 |    0
-| CLINT             | Core local interruptor                                         | 307 | 166 |        0 |    0
-| NEOLED            | Smart LED Interface (NeoPixel/WS28128) (FIFO_depth=1)          | 171 | 129 |        0 |    0
-| ONEWIRE           | 1-wire interface                                               | 105 |  77 |        0 |    0
-| PWM               | Pulse_width modulation controller (4 channels)                 |  91 |  81 |        0 |    0
-| Reservation Set   | Reservation set controller for LR/SC instructions              |  52 |  33 |        0 |    0
-| SDI               | Serial data interface                                          | 103 |  77 |      512 |    0
-| SLINK             | Stream link interface (RX/TX FIFO depth=32)                    |  96 |  73 |     2048 |    0
-| SPI               | Serial peripheral interface                                    | 137 |  97 |     1024 |    0
-| SYSINFO           | System configuration information memory                        |  11 |  11 |        0 |    0
-| TRNG              | True random number generator                                   | 140 | 108 |      512 |    0
-| TWI               | Two-wire interface                                             |  93 |  64 |        0 |    0
-| UART0, UART1      | Universal asynchronous receiver/transmitter 0/1 (FIFO_depth=1) | 222 | 142 |     1024 |    0
-| WDT               | Watchdog timer                                                 | 107 |  89 |        0 |    0
-| WISHBONE          | External memory interface                                      | 122 | 112 |        0 |    0
-| XIP               | Execute in place module                                        | 369 | 276 |        0 |    0
-| XIRQ              | External interrupt controller (4 channels)                     |  35 |  29 |        0 |    0
-|=======================
-
-
 <<<
 // ####################################################################################################################
 :sectnums: