✨ [cpu] add experimental support for RISC-V Zibi ISA extension (#1418)

Author: stnolting

CHANGELOG.md

@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 01.11.2025 | 1.12.3.9 | :sparkles: add experimental support for the RISC-V `Zibi` ISA extension (branches with immediates) | [#1418](https://github.com/stnolting/neorv32/pull/1418) |
 | 25.10.2025 | 1.12.3.8 | :bug: fix CLINT register read-back (bug introduced in previous version / v1.12.3.7) | [#1411](https://github.com/stnolting/neorv32/pull/1411) |
 | 23.10.2025 | 1.12.3.7 | counter optimizations and PMP logic cleanup | [#1410](https://github.com/stnolting/neorv32/pull/1410) |
 | 18.10.2025 | 1.12.3.6 | improve PMP logic (shortening of critical path) | [#1408](https://github.com/stnolting/neorv32/pull/1408) |

README.md

@@ -97,6 +97,7 @@ setup according to your needs. Note that all of the following SoC modules are en
 [`Zbkc`](https://stnolting.github.io/neorv32/#_zbkc_isa_extension)
 [`Zbkx`](https://stnolting.github.io/neorv32/#_zbkx_isa_extension)
 [`Zbs`](https://stnolting.github.io/neorv32/#_zbs_isa_extension)
+[`Zibi`](https://stnolting.github.io/neorv32/#_zibi_isa_extension)
 [`Zicntr`](https://stnolting.github.io/neorv32/#_zicntr_isa_extension)
 [`Zicond`](https://stnolting.github.io/neorv32/#_zicond_isa_extension)
 [`Zicsr`](https://stnolting.github.io/neorv32/#_zicsr_isa_extension)

docs/datasheet/cpu_csr.adoc

@@ -998,5 +998,6 @@ discover additional ISA (sub-)extensions and CPU configuration options.
 | 26    | `CSR_MXISA_ZALRSC`   | r/- | <<_zalrsc_isa_extension>> available
 | 27    | `CSR_MXISA_ZCB`      | r/- | <<_zcb_isa_extension>> available
 | 28    | `CSR_MXISA_ZCA`      | r/- | "`C` without floating-point", available when <<_c_isa_extension>> is available
-| 31:29 | -                    | r/- | _reserved_, read as zero
+| 29    | `CSR_MXISA_ZIBI`     | r/- | <<_zibi_isa_extension>> available
+| 31:30 | -                    | r/- | _reserved_, read as zero
 |=======================

docs/datasheet/cpu_isa.adoc

@@ -30,6 +30,7 @@ This chapter gives a brief overview of all available ISA extensions.
 | <<_zbs_isa_extension,`Zbs`>>           | Single-bit bit manipulation instructions                     | <<_processor_top_entity_generics, `RISCV_ISA_Zbs`>>
 | <<_zfinx_isa_extension,`Zfinx`>>       | Floating-point instructions using integer registers          | <<_processor_top_entity_generics, `RISCV_ISA_Zfinx`>>
 | <<_zifencei_isa_extension,`Zifencei`>> | Instruction stream synchronization instruction               | Always enabled
+| <<_zibi_isa_extension,`Zibi`>>         | Branches with immediate-comparison                           | <<_processor_top_entity_generics, `RISCV_ISA_Zibi`>>
 | <<_zicntr_isa_extension,`Zicntr`>>     | Base counters extension                                      | <<_processor_top_entity_generics, `RISCV_ISA_Zicntr`>>
 | <<_zicond_isa_extension,`Zicond`>>     | Integer conditional operations                               | <<_processor_top_entity_generics, `RISCV_ISA_Zicond`>>
 | <<_zicsr_isa_extension,`Zicsr`>>       | Control and status register access instructions              | Always enabled
@@ -134,7 +135,7 @@ The "compressed" ISA extension provides 16-bit encodings of commonly used instru
 | ALU        | `c.addi4spn` `c.nop` `c.add[i]` `c.li` `c.addi16sp` `c.lui` `c.and[i]` `c.sub` `c.xor` `c.or` `c.mv` | 2
 | ALU shifts | `c.srli` `c.srai` `c.slli`                                                                           | 2 + `T_shift_latency`
 | Branch     | `c.beqz` `c.bnez`                                                                                    | not taken: 3 +
-taken 5 + `T_inst_latency`
+taken: 5 + `T_inst_latency`
 | Jump/call  | `c.jal[r]` `c.j` `c.jr`                                                                              | 5 + `T_inst_latency`
 | Load/store | `c.lw` `c.sw` `c.lwsp` `c.swsp`                                                                      | 4 + `T_data_latency`
 | System     | `c.break`                                                                                            | 7 + `T_inst_latency`
@@ -163,7 +164,7 @@ The `I` ISA extensions is the base RISC-V integer ISA that is always enabled.
 | ALU            | `add[i]` `slt[i]` `slt[i]u` `xor[i]` `or[i]` `and[i]` `sub` `lui` `auipc` | 2
 | ALU shifts     | `sll[i]` `srl[i]` `sra[i]`                                                | 3 + `T_shift_latency`
 | Branch         | `beq` `bne` `blt` `bge` `bltu` `bgeu`                                     | not taken: 3 +
-taken 5 + `T_inst_latency`
+taken: 5 + `T_inst_latency`
 | Jump/call      | `jal[r]`                                                                  | 5 + `T_inst_latency`
 | Load/store     | `lb` `lh` `lw` `lbu` `lhu` `sb` `sh` `sw`                                 | 4 + `T_data_latency`
 | Data fence     | `fence`                                                                   | 2
@@ -336,6 +337,26 @@ If a computational instruction generates a subnormal result it is also flushed t
 |=======================
 
 
+==== `Zibi` ISA Extension
+
+The RISC-V `Zibi` ISA extension adds two new "branch with immediate" instruction. The instruction's
+`rs2` address bits are used to select one out of 32 pre-defined immediate values which is used for
+the actual comparison.
+
+.Non-Ratified ISA Extension
+[WARNING]
+The RISC-V `Zibi` ISA extension has not been ratified yet!
+
+.Instructions and Timing
+[cols="<3,<2,<5"]
+[options="header", grid="rows"]
+|=======================
+| Class | Instructions | Execution cycles
+| Branch with immediate | `beqi` `bnei` | not taken: 3 +
+taken: 5 + `T_inst_latency`
+|=======================
+
+
 ==== `Zicntr` ISA Extension
 
 The `Zicntr` ISA extension adds the basic <<_cycleh>>, <<_mcycleh>>, <<_instreth>> and <<_minstreth>>

docs/datasheet/soc.adoc

@@ -232,6 +232,7 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
 | `RISCV_ISA_Zbkx`        | boolean   | false         | Enable <<_zbkx_isa_extension>> (scalar cryptography crossbar permutations).
 | `RISCV_ISA_Zbs`         | boolean   | false         | Enable <<_zbs_isa_extension>> (single-bit bit-manipulation instructions).
 | `RISCV_ISA_Zfinx`       | boolean   | false         | Enable <<_zfinx_isa_extension>> (single-precision floating-point unit).
+| `RISCV_ISA_Zibi`        | boolean   | false         | Enable <<_zibi_isa_extension>> (CPU base counters).
 | `RISCV_ISA_Zicntr`      | boolean   | false         | Enable <<_zicntr_isa_extension>> (CPU base counters).
 | `RISCV_ISA_Zicond`      | boolean   | false         | Enable <<_zicond_isa_extension>> (integer conditional instructions).
 | `RISCV_ISA_Zihpm`       | boolean   | false         | Enable <<_zihpm_isa_extension>> (hardware performance monitors).

docs/figures/neorv32_processor.png

@@ -59,7 +59,7 @@ architecture neorv32_clint_rtl of neorv32_clint is
   signal mtime_we : std_ulogic_vector(1 downto 0);
 
   -- mtimecmp access --
-  type mtimecmp_rwe_t is array (0 to 15) of std_ulogic_vector(1 downto 0);
+  type mtimecmp_rwe_t is array (0 to NUM_HARTS-1) of std_ulogic_vector(1 downto 0);
   signal mtimecmp_we : mtimecmp_rwe_t;
   signal mtimecmp_re : mtimecmp_rwe_t;
   signal mtimecmp_en : std_ulogic_vector(NUM_HARTS-1 downto 0);