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⚠️ rename UART RTS/CTS signals (#1180)
2 parents 41a9afe + 91d44ff commit e7eee30

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‎CHANGELOG.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
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3030
| Date | Version | Comment | Ticket |
3131
|:----:|:-------:|:--------|:------:|
32+
| 07.02.2025 | 1.11.0.10 | :warning: rename UART RTS/CTS signals | [#1180](https://github.com/stnolting/neorv32/pull/1180) |
3233
| 07.02.2025 | 1.11.0.9 | minor rtl edits and cleanups | [#1179](https://github.com/stnolting/neorv32/pull/1179) |
3334
| 03.02.2025 | 1.11.0.8 | :sparkles: add explicit memory ordering/coherence support; :warning: remove WDT "halt-on-debug" and "halt-on-sleep" options; :bug: rework cache module fixing several (minor?) design flaws | [#1176](https://github.com/stnolting/neorv32/pull/1176) |
3435
| 03.02.2025 | 1.11.0.7 | :bug: add missing CFS clock gen enable signal | [#1177](https://github.com/stnolting/neorv32/pull/1177) |

‎docs/datasheet/soc.adoc‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -120,13 +120,13 @@ to all inputs and output so the synthesis tool can insert an explicit IO (bounda
120120
5+^| **<<_primary_universal_asynchronous_receiver_and_transmitter_uart0>>**
121121
| `uart0_txd_o` | 1 | out | - | serial transmitter
122122
| `uart0_rxd_i` | 1 | in | `'L'` | serial receiver
123-
| `uart0_rts_o` | 1 | out | - | RX ready to receive new char
124-
| `uart0_cts_i` | 1 | in | `'L'` | TX allowed to start sending, low-active
123+
| `uart0_rtsn_o` | 1 | out | - | RX ready to receive new char
124+
| `uart0_ctsn_i` | 1 | in | `'L'` | TX allowed to start sending, low-active
125125
5+^| **<<_secondary_universal_asynchronous_receiver_and_transmitter_uart1>>**
126126
| `uart1_txd_o` | 1 | out | - | serial transmitter
127127
| `uart1_rxd_i` | 1 | in | `'L'` | serial receiver
128-
| `uart1_rts_o` | 1 | out | - | RX ready to receive new char
129-
| `uart1_cts_i` | 1 | in | `'L'` | TX allowed to start sending, low-active
128+
| `uart1_rtsn_o` | 1 | out | - | RX ready to receive new char
129+
| `uart1_ctsn_i` | 1 | in | `'L'` | TX allowed to start sending, low-active
130130
5+^| **<<_serial_peripheral_interface_controller_spi>>**
131131
| `spi_clk_o` | 1 | out | - | controller clock line
132132
| `spi_dat_o` | 1 | out | - | serial data output

‎docs/datasheet/soc_uart.adoc‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -8,10 +8,10 @@
88
| Hardware source files: | neorv32_uart.vhd |
99
| Software driver files: | neorv32_uart.c | link:https://stnolting.github.io/neorv32/sw/neorv32__uart_8c.html[Online software reference (Doxygen)]
1010
| | neorv32_uart.h | link:https://stnolting.github.io/neorv32/sw/neorv32__uart_8h.html[Online software reference (Doxygen)]
11-
| Top entity ports: | `uart0_txd_o` | serial transmitter output
12-
| | `uart0_rxd_i` | serial receiver input
13-
| | `uart0_rts_o` | flow control: RX ready to receive, low-active
14-
| | `uart0_cts_i` | flow control: RX ready to receive, low-active
11+
| Top entity ports: | `uart0_txd_o` | serial transmitter output
12+
| | `uart0_rxd_i` | serial receiver input
13+
| | `uart0_rtsn_o` | flow control: RX ready to receive, low-active
14+
| | `uart0_ctsn_i` | flow control: RX ready to receive, low-active
1515
| Configuration generics: | `IO_UART0_EN` | implement UART0 when `true`
1616
| | `UART0_RX_FIFO` | RX FIFO depth (power of 2, min 1)
1717
| | `UART0_TX_FIFO` | TX FIFO depth (power of 2, min 1)
@@ -92,17 +92,17 @@ Software can retrieve the configured sizes of the RX and TX FIFO via the accordi
9292

9393
**RTS/CTS Hardware Flow Control**
9494

95-
The NEORV32 UART supports optional hardware flow control using the standard CTS `uart0_cts_i` ("clear to send") and RTS
96-
`uart0_rts_o` ("ready to send" / "ready to receive (RTR)") signals. Both signals are low-active.
95+
The NEORV32 UART supports optional hardware flow control using the standard CTS `uart0_ctsn_i` ("clear to send") and RTS
96+
`uart0_rtsn_o` ("ready to send" / "ready to receive (RTR)") signals. Both signals are low-active.
9797
Hardware flow control is enabled by setting the `UART_CTRL_HWFC_EN` bit in the modules control register `CTRL`.
9898

9999
When hardware flow control is enabled:
100100

101-
. The UART's transmitter will not start a new transmission until the `uart0_cts_i` signal goes low.
101+
. The UART's transmitter will not start a new transmission until the `uart0_ctsn_i` signal goes low.
102102
During this time, the UART busy flag `UART_CTRL_TX_BUSY` remains set.
103-
. The UART will set `uart0_rts_o` signal low if the RX FIFO is **less than half full** (to have a wide safety margin).
104-
As long as this signal is low, the connected device can send new data. `uart0_rts_o` is always low if the hardware flow-control
105-
is disabled. Disabling the UART (setting `UART_CTRL_EN` low) while having hardware flow-control enabled, will set `uart0_rts_o`
103+
. The UART will set `uart0_rtsn_o` signal low if the RX FIFO is **less than half full** (to have a wide safety margin).
104+
As long as this signal is low, the connected device can send new data. `uart0_rtsn_o` is always low if the hardware flow-control
105+
is disabled. Disabling the UART (setting `UART_CTRL_EN` low) while having hardware flow-control enabled, will set `uart0_rtsn_o`
106106
high to signal that the UARt is not capable of receiving new data.
107107

108108
[NOTE]
@@ -167,10 +167,10 @@ Both file are created in the simulation's home folder.
167167
| Hardware source files: | neorv32_uart.vhd |
168168
| Software driver files: | neorv32_uart.c |
169169
| | neorv32_uart.h |
170-
| Top entity ports: | `uart1_txd_o` | serial transmitter output
171-
| | `uart1_rxd_i` | serial receiver input
172-
| | `uart1_rts_o` | flow control: RX ready to receive, low-active
173-
| | `uart1_cts_i` | flow control: RX ready to receive, low-active
170+
| Top entity ports: | `uart1_txd_o` | serial transmitter output
171+
| | `uart1_rxd_i` | serial receiver input
172+
| | `uart1_rtsn_o` | flow control: RX ready to receive, low-active
173+
| | `uart1_ctsn_i` | flow control: RX ready to receive, low-active
174174
| Configuration generics: | `IO_UART1_EN` | implement UART1 when `true`
175175
| | `UART1_RX_FIFO` | RX FIFO depth (power of 2, min 1)
176176
| | `UART1_TX_FIFO` | TX FIFO depth (power of 2, min 1)

‎rtl/core/neorv32_package.vhd‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ package neorv32_package is
2929

3030
-- Architecture Constants -----------------------------------------------------------------
3131
-- -------------------------------------------------------------------------------------------
32-
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110009"; -- hardware version
32+
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110010"; -- hardware version
3333
constant archid_c : natural := 19; -- official RISC-V architecture ID
3434
constant XLEN : natural := 32; -- native data path width
3535

@@ -868,13 +868,13 @@ package neorv32_package is
868868
-- primary UART0 (available if IO_UART0_EN = true) --
869869
uart0_txd_o : out std_ulogic;
870870
uart0_rxd_i : in std_ulogic := 'L';
871-
uart0_rts_o : out std_ulogic;
872-
uart0_cts_i : in std_ulogic := 'L';
871+
uart0_rtsn_o : out std_ulogic;
872+
uart0_ctsn_i : in std_ulogic := 'L';
873873
-- secondary UART1 (available if IO_UART1_EN = true) --
874874
uart1_txd_o : out std_ulogic;
875875
uart1_rxd_i : in std_ulogic := 'L'; -- UART1 receive data
876-
uart1_rts_o : out std_ulogic;
877-
uart1_cts_i : in std_ulogic := 'L';
876+
uart1_rtsn_o : out std_ulogic;
877+
uart1_ctsn_i : in std_ulogic := 'L';
878878
-- SPI (available if IO_SPI_EN = true) --
879879
spi_clk_o : out std_ulogic;
880880
spi_dat_o : out std_ulogic;

‎rtl/core/neorv32_top.vhd‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -182,14 +182,14 @@ entity neorv32_top is
182182
-- primary UART0 (available if IO_UART0_EN = true) --
183183
uart0_txd_o : out std_ulogic; -- UART0 send data
184184
uart0_rxd_i : in std_ulogic := 'L'; -- UART0 receive data
185-
uart0_rts_o : out std_ulogic; -- HW flow control: UART0.RX ready to receive ("RTR"), low-active, optional
186-
uart0_cts_i : in std_ulogic := 'L'; -- HW flow control: UART0.TX allowed to transmit, low-active, optional
185+
uart0_rtsn_o : out std_ulogic; -- HW flow control: UART0.RX ready to receive ("RTR"), low-active, optional
186+
uart0_ctsn_i : in std_ulogic := 'L'; -- HW flow control: UART0.TX allowed to transmit, low-active, optional
187187

188188
-- secondary UART1 (available if IO_UART1_EN = true) --
189189
uart1_txd_o : out std_ulogic; -- UART1 send data
190190
uart1_rxd_i : in std_ulogic := 'L'; -- UART1 receive data
191-
uart1_rts_o : out std_ulogic; -- HW flow control: UART1.RX ready to receive ("RTR"), low-active, optional
192-
uart1_cts_i : in std_ulogic := 'L'; -- HW flow control: UART1.TX allowed to transmit, low-active, optional
191+
uart1_rtsn_o : out std_ulogic; -- HW flow control: UART1.RX ready to receive ("RTR"), low-active, optional
192+
uart1_ctsn_i : in std_ulogic := 'L'; -- HW flow control: UART1.TX allowed to transmit, low-active, optional
193193

194194
-- SPI (available if IO_SPI_EN = true) --
195195
spi_clk_o : out std_ulogic; -- SPI serial clock
@@ -1186,8 +1186,8 @@ begin
11861186
clkgen_i => clk_gen,
11871187
uart_txd_o => uart0_txd_o,
11881188
uart_rxd_i => uart0_rxd_i,
1189-
uart_rts_o => uart0_rts_o,
1190-
uart_cts_i => uart0_cts_i,
1189+
uart_rtsn_o => uart0_rtsn_o,
1190+
uart_ctsn_i => uart0_ctsn_i,
11911191
irq_rx_o => firq(FIRQ_UART0_RX),
11921192
irq_tx_o => firq(FIRQ_UART0_TX)
11931193
);
@@ -1197,7 +1197,7 @@ begin
11971197
if not IO_UART0_EN generate
11981198
iodev_rsp(IODEV_UART0) <= rsp_terminate_c;
11991199
uart0_txd_o <= '0';
1200-
uart0_rts_o <= '1';
1200+
uart0_rtsn_o <= '1';
12011201
clk_gen_en(CG_UART0) <= '0';
12021202
firq(FIRQ_UART0_RX) <= '0';
12031203
firq(FIRQ_UART0_TX) <= '0';
@@ -1224,8 +1224,8 @@ begin
12241224
clkgen_i => clk_gen,
12251225
uart_txd_o => uart1_txd_o,
12261226
uart_rxd_i => uart1_rxd_i,
1227-
uart_rts_o => uart1_rts_o,
1228-
uart_cts_i => uart1_cts_i,
1227+
uart_rtsn_o => uart1_rtsn_o,
1228+
uart_ctsn_i => uart1_ctsn_i,
12291229
irq_rx_o => firq(FIRQ_UART1_RX),
12301230
irq_tx_o => firq(FIRQ_UART1_TX)
12311231
);
@@ -1235,7 +1235,7 @@ begin
12351235
if not IO_UART1_EN generate
12361236
iodev_rsp(IODEV_UART1) <= rsp_terminate_c;
12371237
uart1_txd_o <= '0';
1238-
uart1_rts_o <= '1';
1238+
uart1_rtsn_o <= '1';
12391239
clk_gen_en(CG_UART1) <= '0';
12401240
firq(FIRQ_UART1_RX) <= '0';
12411241
firq(FIRQ_UART1_TX) <= '0';

‎rtl/core/neorv32_uart.vhd‎

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -37,8 +37,8 @@ entity neorv32_uart is
3737
clkgen_i : in std_ulogic_vector(7 downto 0);
3838
uart_txd_o : out std_ulogic; -- serial TX line
3939
uart_rxd_i : in std_ulogic; -- serial RX line
40-
uart_rts_o : out std_ulogic; -- UART.RX ready to receive ("RTR"), low-active, optional
41-
uart_cts_i : in std_ulogic; -- UART.TX allowed to transmit, low-active, optional
40+
uart_rtsn_o : out std_ulogic; -- ready to receive ("RTR"), low-active, optional
41+
uart_ctsn_i : in std_ulogic; -- allowed to transmit, low-active, optional
4242
irq_rx_o : out std_ulogic; -- RX interrupt
4343
irq_tx_o : out std_ulogic -- TX interrupt
4444
);
@@ -105,14 +105,14 @@ architecture neorv32_uart_rtl of neorv32_uart is
105105

106106
-- UART transmitter --
107107
type tx_engine_t is record
108-
state : std_ulogic_vector(2 downto 0);
109-
sreg : std_ulogic_vector(8 downto 0);
110-
bitcnt : std_ulogic_vector(3 downto 0);
111-
baudcnt : std_ulogic_vector(9 downto 0);
112-
done : std_ulogic;
113-
busy : std_ulogic;
114-
cts_sync : std_ulogic_vector(1 downto 0);
115-
txd : std_ulogic;
108+
state : std_ulogic_vector(2 downto 0);
109+
sreg : std_ulogic_vector(8 downto 0);
110+
bitcnt : std_ulogic_vector(3 downto 0);
111+
baudcnt : std_ulogic_vector(9 downto 0);
112+
done : std_ulogic;
113+
busy : std_ulogic;
114+
cts : std_ulogic_vector(1 downto 0);
115+
txd : std_ulogic;
116116
end record;
117117
signal tx_engine : tx_engine_t;
118118

@@ -321,16 +321,16 @@ begin
321321
transmitter: process(rstn_i, clk_i)
322322
begin
323323
if (rstn_i = '0') then
324-
tx_engine.cts_sync <= (others => '0');
325-
tx_engine.done <= '0';
326-
tx_engine.state <= (others => '0');
327-
tx_engine.baudcnt <= (others => '0');
328-
tx_engine.bitcnt <= (others => '0');
329-
tx_engine.sreg <= (others => '0');
330-
tx_engine.txd <= '1';
324+
tx_engine.cts <= (others => '0');
325+
tx_engine.done <= '0';
326+
tx_engine.state <= (others => '0');
327+
tx_engine.baudcnt <= (others => '0');
328+
tx_engine.bitcnt <= (others => '0');
329+
tx_engine.sreg <= (others => '0');
330+
tx_engine.txd <= '1';
331331
elsif rising_edge(clk_i) then
332332
-- synchronize clear-to-send --
333-
tx_engine.cts_sync <= tx_engine.cts_sync(0) & uart_cts_i;
333+
tx_engine.cts <= tx_engine.cts(0) & uart_ctsn_i;
334334

335335
-- defaults --
336336
tx_engine.done <= '0';
@@ -352,7 +352,7 @@ begin
352352
when "101" => -- WAIT: check if we can start sending
353353
-- ------------------------------------------------------------
354354
if (uart_clk = '1') and -- start with next clock tick
355-
((tx_engine.cts_sync(1) = '0') or (ctrl.hwfc_en = '0')) then -- allowed to send OR flow-control disabled
355+
((tx_engine.cts(1) = '0') or (ctrl.hwfc_en = '0')) then -- allowed to send OR flow-control disabled
356356
tx_engine.state(1 downto 0) <= "11";
357357
end if;
358358

@@ -463,17 +463,17 @@ begin
463463
rtr_control: process(rstn_i, clk_i)
464464
begin
465465
if (rstn_i = '0') then
466-
uart_rts_o <= '0';
466+
uart_rtsn_o <= '0';
467467
elsif rising_edge(clk_i) then
468468
if (ctrl.hwfc_en = '1') then
469469
if (ctrl.enable = '0') or -- UART disabled
470470
(rx_fifo.half = '1') then -- RX FIFO at least half-full: no "safe space" left in RX FIFO
471-
uart_rts_o <= '1'; -- NOT allowed to send
471+
uart_rtsn_o <= '1'; -- NOT allowed to send
472472
else
473-
uart_rts_o <= '0'; -- ready to receive
473+
uart_rtsn_o <= '0'; -- ready to receive
474474
end if;
475475
else
476-
uart_rts_o <= '0'; -- always ready to receive when HW flow-control is disabled
476+
uart_rtsn_o <= '0'; -- always ready to receive when HW flow-control is disabled
477477
end if;
478478
end if;
479479
end process rtr_control;

‎rtl/system_integration/neorv32_vivado_ip.tcl‎

Lines changed: 17 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -123,7 +123,6 @@ proc setup_ip_gui {} {
123123
set_property enablement_dependency {$IO_SLINK_EN} [ipx::get_bus_interfaces s0_axis -of_objects [ipx::current_core]]
124124
set_property enablement_dependency {$IO_SLINK_EN} [ipx::get_bus_interfaces s1_axis -of_objects [ipx::current_core]]
125125
set_property enablement_dependency {$XBUS_EN} [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
126-
set_property enablement_dependency {$OCD_EN} [ipx::get_ports jtag_* -of_objects [ipx::current_core]]
127126
set_property enablement_dependency {$IO_GPIO_EN} [ipx::get_ports gpio_* -of_objects [ipx::current_core]]
128127
set_property enablement_dependency {$IO_UART0_EN} [ipx::get_ports uart0_* -of_objects [ipx::current_core]]
129128
set_property enablement_dependency {$IO_UART1_EN} [ipx::get_ports uart1_* -of_objects [ipx::current_core]]
@@ -139,6 +138,23 @@ proc setup_ip_gui {} {
139138
set_property enablement_dependency {!$IO_CLINT_EN} [ipx::get_ports mtime_irq_i -of_objects [ipx::current_core]]
140139
set_property enablement_dependency {!$IO_CLINT_EN} [ipx::get_ports msw_irq_i -of_objects [ipx::current_core]]
141140

141+
# **************************************************************
142+
# Interfaces: Add JTAG as standard interface
143+
# **************************************************************
144+
ipx::add_bus_interface JTAG [ipx::current_core]
145+
set_property abstraction_type_vlnv xilinx.com:interface:jtag_rtl:2.0 [ipx::get_bus_interfaces JTAG -of_objects [ipx::current_core]]
146+
set_property bus_type_vlnv xilinx.com:interface:jtag:2.0 [ipx::get_bus_interfaces JTAG -of_objects [ipx::current_core]]
147+
set_property display_name JTAG [ipx::get_bus_interfaces JTAG -of_objects [ipx::current_core]]
148+
set_property description {JTAG tap of the on-chip debugger} [ipx::get_bus_interfaces JTAG -of_objects [ipx::current_core]]
149+
set_property enablement_dependency {$OCD_EN} [ipx::get_bus_interfaces JTAG -of_objects [ipx::current_core]]
150+
ipx::add_port_map TDI [ipx::get_bus_interfaces JTAG -of_objects [ipx::current_core]]
151+
set_property physical_name jtag_tdi_i [ipx::get_port_maps TDI -of_objects [ipx::get_bus_interfaces JTAG -of_objects [ipx::current_core]]]
152+
ipx::add_port_map TMS [ipx::get_bus_interfaces JTAG -of_objects [ipx::current_core]]
153+
set_property physical_name jtag_tms_i [ipx::get_port_maps TMS -of_objects [ipx::get_bus_interfaces JTAG -of_objects [ipx::current_core]]]
154+
ipx::add_port_map TCK [ipx::get_bus_interfaces JTAG -of_objects [ipx::current_core]]
155+
set_property physical_name jtag_tck_i [ipx::get_port_maps TCK -of_objects [ipx::get_bus_interfaces JTAG -of_objects [ipx::current_core]]]
156+
ipx::add_port_map TDO [ipx::get_bus_interfaces JTAG -of_objects [ipx::current_core]]
157+
set_property physical_name jtag_tdo_o [ipx::get_port_maps TDO -of_objects [ipx::get_bus_interfaces JTAG -of_objects [ipx::current_core]]]
142158

143159
# **************************************************************
144160
# Configuration pages

‎rtl/system_integration/neorv32_vivado_ip.vhd‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -200,13 +200,13 @@ entity neorv32_vivado_ip is
200200
-- primary UART0 (available if IO_UART0_EN = true) --
201201
uart0_txd_o : out std_logic;
202202
uart0_rxd_i : in std_logic := '0';
203-
uart0_rts_o : out std_logic;
204-
uart0_cts_i : in std_logic := '0';
203+
uart0_rtsn_o : out std_logic;
204+
uart0_ctsn_i : in std_logic := '0';
205205
-- secondary UART1 (available if IO_UART1_EN = true) --
206206
uart1_txd_o : out std_logic;
207207
uart1_rxd_i : in std_logic := '0';
208-
uart1_rts_o : out std_logic;
209-
uart1_cts_i : in std_logic := '0';
208+
uart1_rtsn_o : out std_logic;
209+
uart1_ctsn_i : in std_logic := '0';
210210
-- SPI (available if IO_SPI_EN = true) --
211211
spi_clk_o : out std_logic;
212212
spi_dat_o : out std_logic;
@@ -301,7 +301,7 @@ architecture neorv32_vivado_ip_rtl of neorv32_vivado_ip is
301301
signal s0_axis_tdata_aux : std_ulogic_vector(31 downto 0);
302302
signal s0_axis_tdest_aux : std_ulogic_vector(3 downto 0);
303303
signal s1_axis_tready_aux, s0_axis_tvalid_aux, s0_axis_tlast_aux : std_ulogic;
304-
signal uart0_txd_aux, uart0_rts_aux, uart1_txd_aux, uart1_rts_aux : std_ulogic;
304+
signal uart0_txd_aux, uart0_rtsn_aux, uart1_txd_aux, uart1_rtsn_aux : std_ulogic;
305305
signal spi_clk_aux, spi_do_aux : std_ulogic;
306306
signal spi_csn_aux : std_ulogic_vector(7 downto 0);
307307
signal sdi_do_aux : std_ulogic;
@@ -477,13 +477,13 @@ begin
477477
-- primary UART0 (available if IO_UART0_EN = true) --
478478
uart0_txd_o => uart0_txd_aux,
479479
uart0_rxd_i => std_ulogic(uart0_rxd_i),
480-
uart0_rts_o => uart0_rts_aux,
481-
uart0_cts_i => std_ulogic(uart0_cts_i),
480+
uart0_rtsn_o => uart0_rtsn_aux,
481+
uart0_ctsn_i => std_ulogic(uart0_ctsn_i),
482482
-- secondary UART1 (available if IO_UART1_EN = true) --
483483
uart1_txd_o => uart1_txd_aux,
484484
uart1_rxd_i => std_ulogic(uart1_rxd_i),
485-
uart1_rts_o => uart1_rts_aux,
486-
uart1_cts_i => std_ulogic(uart1_cts_i),
485+
uart1_rtsn_o => uart1_rtsn_aux,
486+
uart1_ctsn_i => std_ulogic(uart1_ctsn_i),
487487
-- SPI (available if IO_SPI_EN = true) --
488488
spi_clk_o => spi_clk_aux,
489489
spi_dat_o => spi_do_aux,
@@ -537,9 +537,9 @@ begin
537537
s0_axis_tlast <= std_logic(s0_axis_tlast_aux);
538538

539539
uart0_txd_o <= std_logic(uart0_txd_aux);
540-
uart0_rts_o <= std_logic(uart0_rts_aux);
540+
uart0_rtsn_o <= std_logic(uart0_rtsn_aux);
541541
uart1_txd_o <= std_logic(uart1_txd_aux);
542-
uart1_rts_o <= std_logic(uart1_rts_aux);
542+
uart1_rtsn_o <= std_logic(uart1_rtsn_aux);
543543

544544
spi_clk_o <= std_logic(spi_clk_aux);
545545
spi_dat_o <= std_logic(spi_do_aux);

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