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[top] disable all optional extensions by default
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‎docs/datasheet/soc.adoc

Lines changed: 15 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -178,7 +178,8 @@ optimize the system for certain design goals like minimal area or maximum perfor
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.Default Values
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[NOTE]
181-
All _optional_ configuration generics provide default values in case they are not explicitly assigned during instantiation.
181+
All configuration generics provide default values in case they are not explicitly assigned during instantiation.
182+
By default, all configuration options are **disabled**.
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.Software Discovery of Configuration
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[TIP]
@@ -195,7 +196,6 @@ and do not impact timing.
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[NOTE]
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The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downto y)`".
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198-
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.NEORV32 Processor Generic List
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[cols="<3,^2,^2,<8"]
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[options="header",grid="rows"]
@@ -226,7 +226,7 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
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| `RISCV_ISA_Zbkx` | boolean | false | Enable <<_zbkx_isa_extension>> (scalar cryptography crossbar permutations).
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| `RISCV_ISA_Zbs` | boolean | false | Enable <<_zbs_isa_extension>> (single-bit bit-manipulation instructions).
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| `RISCV_ISA_Zfinx` | boolean | false | Enable <<_zfinx_isa_extension>> (single-precision floating-point unit).
229-
| `RISCV_ISA_Zicntr` | boolean | true | Enable <<_zicntr_isa_extension>> (CPU base counters).
229+
| `RISCV_ISA_Zicntr` | boolean | false | Enable <<_zicntr_isa_extension>> (CPU base counters).
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| `RISCV_ISA_Zicond` | boolean | false | Enable <<_zicond_isa_extension>> (integer conditional instructions).
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| `RISCV_ISA_Zihpm` | boolean | false | Enable <<_zihpm_isa_extension>> (hardware performance monitors).
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| `RISCV_ISA_Zknd` | boolean | false | Enable <<_zknd_isa_extension>> (scalar cryptography NIST AES decryption instructions).
@@ -244,8 +244,8 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
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4+^| **Physical Memory Protection (<<_smpmp_isa_extension>>)**
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| `PMP_NUM_REGIONS` | natural | 0 | Number of implemented PMP regions (0..16).
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| `PMP_MIN_GRANULARITY` | natural | 4 | Minimal region granularity in bytes. Has to be a power of two, min 4.
247-
| `PMP_TOR_MODE_EN` | boolean | true | Implement support for top-of-region (TOR) mode.
248-
| `PMP_NAP_MODE_EN` | boolean | true | Implement support for naturally-aligned power-of-two (NAPOT & NA4) modes.
247+
| `PMP_TOR_MODE_EN` | boolean | false | Implement support for top-of-region (TOR) mode.
248+
| `PMP_NAP_MODE_EN` | boolean | false | Implement support for naturally-aligned power-of-two (NAPOT & NA4) modes.
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4+^| **Hardware Performance Monitors (<<_zihpm_isa_extension>>)**
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| `HPM_NUM_CNTS` | natural | 0 | Number of implemented hardware performance monitor counters (0..13).
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| `HPM_CNT_WIDTH` | natural | 40 | Total LSB-aligned size of each HPM counter. Min 0, max 64.
@@ -271,7 +271,7 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
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| `XBUS_CACHE_NUM_BLOCKS` | natural | 64 | Number of blocks ("lines"). Has to be a power of two.
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| `XBUS_CACHE_BLOCK_SIZE` | natural | 32 | Size in bytes of each block. Has to be a power of two.
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4+^| **Peripheral/IO Modules**
274-
| `IO_DISABLE_SYSINFO` | boolean | false | Disable <<_system_configuration_information_memory_sysinfo>> module; ⚠️ not recommended - for advanced users only!
274+
| `IO_DISABLE_SYSINFO` | boolean | false | Disable <<_system_configuration_information_memory_sysinfo>> module; not recommended - for advanced users only!
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| `IO_GPIO_NUM` | natural | 0 | Number of general purpose input/output pairs of the <<_general_purpose_input_and_output_port_gpio>>, max 32.
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| `IO_CLINT_EN` | boolean | false | Implement the <<_core_local_interruptor_clint>>.
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| `IO_UART0_EN` | boolean | false | Implement the <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>>.
@@ -646,10 +646,10 @@ The reservation-set controller implements the _strong semnatics_. An active rese
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:sectnums:
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==== Memory Coherence
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649-
Depending on the configuration, the NEORV32 processor provides several _layer_ of memory consisting
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Depending on the configuration, the NEORV32 processor provides several _layers_ of memory consisting
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of caches, buffers and storage.
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* The CPU instruction prefetch buffer ("level-0")
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* The CPU pipeline and its instruction prefetch buffer (level-0)
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* The <<_processor_internal_data_cache_dcache>> (level-1)
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* The <<_processor_internal_instruction_cache_icache>> (level-1)
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* The cache of the <<_processor_external_bus_interface_xbus>> (level-2)
@@ -665,6 +665,13 @@ regardless of the actual CPU/ISA configuration:
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* `fence` (<<_i_isa_extension>> / <<_e_isa_extension>>)
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* `fence.i` (<<_zifencei_isa_extension>>)
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.Weak Coherence Model
669+
[IMPORTANT]
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The NEORV32-specific implementation of the `fence[.i]` ordering instructions only provides a rather **weak**
671+
coherence model. A core's `fence` just orders all memory accesses towards main memory. Hence, they _can_ become
672+
visible by other agents (the secondary CPU core, the DMA, processor-external modules) if these agents also
673+
synchronize (e.g. reload) their cache(s).
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By executing the "data" `fence` instruction the CPU's load/store operations are ordered
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and synchronized across the entire system:
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‎rtl/core/neorv32_package.vhd

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ package neorv32_package is
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
32-
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110103"; -- hardware version
32+
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110104"; -- hardware version
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constant archid_c : natural := 19; -- official RISC-V architecture ID
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constant XLEN : natural := 32; -- native data path width
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@@ -783,7 +783,7 @@ package neorv32_package is
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RISCV_ISA_Zbkx : boolean := false;
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RISCV_ISA_Zbs : boolean := false;
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RISCV_ISA_Zfinx : boolean := false;
786-
RISCV_ISA_Zicntr : boolean := true;
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RISCV_ISA_Zicntr : boolean := false;
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RISCV_ISA_Zicond : boolean := false;
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RISCV_ISA_Zihpm : boolean := false;
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RISCV_ISA_Zmmul : boolean := false;
@@ -801,8 +801,8 @@ package neorv32_package is
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-- Physical Memory Protection (PMP) --
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PMP_NUM_REGIONS : natural range 0 to 16 := 0;
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PMP_MIN_GRANULARITY : natural := 4;
804-
PMP_TOR_MODE_EN : boolean := true;
805-
PMP_NAP_MODE_EN : boolean := true;
804+
PMP_TOR_MODE_EN : boolean := false;
805+
PMP_NAP_MODE_EN : boolean := false;
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS : natural range 0 to 13 := 0;
808808
HPM_CNT_WIDTH : natural range 0 to 64 := 40;

‎rtl/core/neorv32_top.vhd

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ entity neorv32_top is
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RISCV_ISA_Zbkx : boolean := false; -- implement cryptography crossbar permutation extension
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RISCV_ISA_Zbs : boolean := false; -- implement single-bit bit-manipulation extension
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RISCV_ISA_Zfinx : boolean := false; -- implement 32-bit floating-point extension
52-
RISCV_ISA_Zicntr : boolean := true; -- implement base counters
52+
RISCV_ISA_Zicntr : boolean := false; -- implement base counters
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RISCV_ISA_Zicond : boolean := false; -- implement integer conditional operations
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RISCV_ISA_Zihpm : boolean := false; -- implement hardware performance monitors
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RISCV_ISA_Zknd : boolean := false; -- implement cryptography NIST AES decryption extension
@@ -69,8 +69,8 @@ entity neorv32_top is
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-- Physical Memory Protection (PMP) --
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PMP_NUM_REGIONS : natural range 0 to 16 := 0; -- number of regions (0..16)
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PMP_MIN_GRANULARITY : natural := 4; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
72-
PMP_TOR_MODE_EN : boolean := true; -- implement TOR mode
73-
PMP_NAP_MODE_EN : boolean := true; -- implement NAPOT/NA4 modes
72+
PMP_TOR_MODE_EN : boolean := false; -- implement TOR mode
73+
PMP_NAP_MODE_EN : boolean := false; -- implement NAPOT/NA4 modes
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS : natural range 0 to 13 := 0; -- number of implemented HPM counters (0..13)

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