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2 | 2 |
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3 | 3 |  |
4 | 4 |
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5 | | -Formal verification of SP1 zkVM arithmetization |
| 5 | +Formal verification of SP1 Hypercube zkVM arithmetization |
6 | 6 |
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7 | 7 | </div> |
8 | 8 |
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9 | 9 | ## Overview |
10 | 10 |
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11 | | -This repository provides **formal proofs for the arithmetization of the SP1 zkVM**, a zero-knowledge virtual machine for verifying RISC-V 64-bit computations. Using the Lean 4 theorem prover, we formally verify that the constraint systems used in SP1's AIR (Algebraic Intermediate Representation) correctly implement the RISC-V ISA semantics. |
12 | | - |
13 | | -## What is SP1? |
14 | | - |
15 | | -[SP1](https://github.com/succinctlabs/sp1) is a zero-knowledge virtual machine that generates proofs of RISC-V program execution. It uses AIR-based arithmetization to encode the computation into polynomial constraints that can be proven using cryptographic proof systems. |
16 | | - |
17 | | -This repository focuses on **proving the correctness of those constraints** - ensuring that the polynomial equations actually enforce the intended RISC-V semantics. |
| 11 | +This repository provides formal specifications and proofs for the arithmetization of the SP1 Hypercube zkVM using the Lean 4 theorem prover, we formally verify that the constraint systems used in SP1's AIR (Algebraic Intermediate Representation) in addition to constraints implied by the lookup argument, correctly implement the RISC-V ISA semantics. |
18 | 12 |
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19 | 13 | ## Repository Structure |
20 | 14 |
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@@ -99,25 +93,3 @@ lake build |
99 | 93 |
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100 | 94 | - **[Mathlib](https://github.com/leanprover-community/mathlib4)**: Lean's mathematics library (v4.23.0-rc2) |
101 | 95 | - **[Lean_RV64D](https://github.com/succinctlabs/sail-riscv-lean)**: Formal RISC-V semantics extracted from Sail |
102 | | - |
103 | | -## Current Status |
104 | | - |
105 | | -The repository currently includes formal verification for: |
106 | | -- ✅ Arithmetic operations (add, sub, mul, div/rem) |
107 | | -- ✅ Bitwise operations |
108 | | -- ✅ Shift operations |
109 | | -- ✅ Comparison operations |
110 | | -- ✅ Memory operations (load/store) |
111 | | -- ✅ Control flow (branches, jumps) |
112 | | -- ✅ Immediate operations |
113 | | - |
114 | | -## Contributing |
115 | | - |
116 | | -Contributions are welcome! Please see the [contributing guidelines](CONTRIBUTING.md) for more information. |
117 | | - |
118 | | -## Acknowledgments |
119 | | - |
120 | | -This work builds on: |
121 | | -- The [Sail RISC-V specification](https://github.com/rems-project/sail-riscv) |
122 | | -- The [Lean 4 theorem prover](https://github.com/leanprover/lean4) |
123 | | -- The [Mathlib](https://github.com/leanprover-community/mathlib4) mathematics library |
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