Skip to content

Commit 5ee62f8

Browse files
committed
polish
1 parent 7e92677 commit 5ee62f8

File tree

1 file changed

+2
-30
lines changed

1 file changed

+2
-30
lines changed

README.md

Lines changed: 2 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -2,19 +2,13 @@
22

33
![SP1 Lean](./.github/assets/header.png)
44

5-
Formal verification of SP1 zkVM arithmetization
5+
Formal verification of SP1 Hypercube zkVM arithmetization
66

77
</div>
88

99
## Overview
1010

11-
This repository provides **formal proofs for the arithmetization of the SP1 zkVM**, a zero-knowledge virtual machine for verifying RISC-V 64-bit computations. Using the Lean 4 theorem prover, we formally verify that the constraint systems used in SP1's AIR (Algebraic Intermediate Representation) correctly implement the RISC-V ISA semantics.
12-
13-
## What is SP1?
14-
15-
[SP1](https://github.com/succinctlabs/sp1) is a zero-knowledge virtual machine that generates proofs of RISC-V program execution. It uses AIR-based arithmetization to encode the computation into polynomial constraints that can be proven using cryptographic proof systems.
16-
17-
This repository focuses on **proving the correctness of those constraints** - ensuring that the polynomial equations actually enforce the intended RISC-V semantics.
11+
This repository provides formal specifications and proofs for the arithmetization of the SP1 Hypercube zkVM using the Lean 4 theorem prover, we formally verify that the constraint systems used in SP1's AIR (Algebraic Intermediate Representation) in addition to constraints implied by the lookup argument, correctly implement the RISC-V ISA semantics.
1812

1913
## Repository Structure
2014

@@ -99,25 +93,3 @@ lake build
9993

10094
- **[Mathlib](https://github.com/leanprover-community/mathlib4)**: Lean's mathematics library (v4.23.0-rc2)
10195
- **[Lean_RV64D](https://github.com/succinctlabs/sail-riscv-lean)**: Formal RISC-V semantics extracted from Sail
102-
103-
## Current Status
104-
105-
The repository currently includes formal verification for:
106-
- ✅ Arithmetic operations (add, sub, mul, div/rem)
107-
- ✅ Bitwise operations
108-
- ✅ Shift operations
109-
- ✅ Comparison operations
110-
- ✅ Memory operations (load/store)
111-
- ✅ Control flow (branches, jumps)
112-
- ✅ Immediate operations
113-
114-
## Contributing
115-
116-
Contributions are welcome! Please see the [contributing guidelines](CONTRIBUTING.md) for more information.
117-
118-
## Acknowledgments
119-
120-
This work builds on:
121-
- The [Sail RISC-V specification](https://github.com/rems-project/sail-riscv)
122-
- The [Lean 4 theorem prover](https://github.com/leanprover/lean4)
123-
- The [Mathlib](https://github.com/leanprover-community/mathlib4) mathematics library

0 commit comments

Comments
 (0)