Fix GLO changes to match profile switching logic changes

Author: Adel Mamin

peregrine/defaults.py

@@ -215,6 +215,11 @@
     'pll_bw': (20, 18, 16, 14, 12, 10, 8, 7, 6.5, 6, 5.5, 5),
     'coherent_ms': (20,) }
 
+glol1_track_params = {
+    'fll_bw': (2, 1, 0),
+    'pll_bw': (40, 20, 18, 16, 14, 12, 10, 8, 7, 6.5, 6, 5.5, 5),
+    'coherent_ms': (1,) }
+
 l1ca_loop_filter_params_template = {
      'code_params': (1., 0.7, 1.),   # NBW, zeta, k
      'carr_params': (20., 0.7, 1.),   # NBW, zeta, k
@@ -231,6 +236,14 @@
      'carr_to_code': 1200.           # carr_to_code
     }
 
+glol1_loop_filter_params_template = {
+     'code_params': (1., 0.7, 1.),   # NBW, zeta, k
+     'carr_params': (20., 0.7, 1.),   # NBW, zeta, k
+     'loop_freq': 1000.,             # 1000/coherent_ms
+     'carr_freq_b1': 1.,             # FLL NBW
+     'carr_to_code': 3135.0293542074364 # carr_to_code
+    }
+
 # Tracking stages. See track.c for more details.
 # 1;20 ms stages
 l1ca_stage_params_slow = \
@@ -372,7 +385,25 @@
 USE_COMPENSATED_BIT = 10
 PREPARE_BIT_COMPENSATION = 11
 
-fsm_states = \
+glo_fsm_states = \
+  { '1ms':
+    { 'no_bit_sync':
+      { 'short_n_long':
+        { 0: (511, 1, {'pre': (APPLY_CORR_1,),
+                       'post': (RUN_LD, GET_CORR_1, ALIAS_DETECT_1ST)}),
+          1: (511, 0, {'pre': (APPLY_CORR_2,),
+                       'post': (RUN_LD, GET_CORR_2, ALIAS_DETECT_2ND)}) },
+
+        'ideal':
+        { 0: (511, 1, {'pre': (APPLY_CORR_1,),
+                       'post': (RUN_LD, GET_CORR_1, ALIAS_DETECT_1ST)}),
+          1: (511, 0, {'pre': (APPLY_CORR_1,),
+                       'post': (RUN_LD, GET_CORR_1, ALIAS_DETECT_2ND)}) }
+      }
+    }
+  }
+
+gps_fsm_states = \
   { '1ms':
     { 'no_bit_sync':
       { 'short_n_long':
@@ -1257,6 +1288,8 @@
     'lp': 50,      # 1000ms worth of I/Q samples to reach pessimistic lock
     'lo': 240}     # 4800ms worth of I/Q samples to lower optimistic lock
 
+glol1_lock_detect_params = l1ca_lock_detect_params_opt
+
 # The time interval, over which the alias detection is done.
 # The alias detect algorithm averages the phase angle over this time [ms]
 alias_detect_interval_ms = 500

peregrine/tracking.py

@@ -128,7 +128,7 @@ def _tracking_channel_factory(parameters):
   if parameters['acq'].signal == glo_constants.GLO_L1:
     return TrackingChannelGLOL1(parameters)
 
-def get_fsm_states(ms, short_n_long, bit_sync):
+def get_fsm_states(fsm_states, ms, short_n_long, bit_sync):
   if ms == 1:
     ms = '1ms'
   elif ms == 2:
@@ -158,7 +158,7 @@ def get_fsm_states(ms, short_n_long, bit_sync):
   else:
     bit_sync_status = 'no_bit_sync'
 
-  return defaults.fsm_states[ms][bit_sync_status][mode]
+  return fsm_states[ms][bit_sync_status][mode]
 
 
 def get_lock_detector(cur_bw, lock_detect_set):
@@ -244,7 +244,8 @@ def __init__(self, params):
 
     self.track_settled = False
     self.fsm_index = 0
-    self.fsm_states = get_fsm_states(ms=self.coherent_ms,
+    self.fsm_states = get_fsm_states(self.fsm_states_all,
+                                     ms=self.coherent_ms,
                                      short_n_long=self.short_n_long,
                                      bit_sync=self.bit_sync)
 
@@ -408,7 +409,8 @@ def _set_track_profile(self):
                                 cutoff_freq=10,
                                 loop_freq=1e3 / self.coherent_ms)
 
-    self.fsm_states = get_fsm_states(ms=self.coherent_ms,
+    self.fsm_states = get_fsm_states(self.fsm_states_all,
+                                     ms=self.coherent_ms,
                                      short_n_long=self.short_n_long,
                                      bit_sync=self.bit_sync)
     self.fsm_index = 0
@@ -960,6 +962,7 @@ def __init__(self, params):
     params['chipping_rate'] = gps_constants.l1ca_chip_rate
     params['sample_index'] = params['samples']['sample_index']
     params['carrier_freq'] = gps_constants.l1
+    params['fsm_states_all'] = defaults.gps_fsm_states
 
     self.bit_sync = False
 
@@ -1075,6 +1078,7 @@ def __init__(self, params):
     params['chipping_rate'] = gps_constants.l2c_chip_rate
     params['sample_index'] = 0
     params['carrier_freq'] = gps_constants.l2
+    params['fsm_states_all'] = defaults.gps_fsm_states
 
     self.bit_sync = True
 
@@ -1135,22 +1139,29 @@ def __init__(self, params):
     GLO L1 tracking initialization parameters
 
     """
+
     # Convert acquisition SNR to C/N0
     cn0_0 = 10 * np.log10(params['acq'].snr)
     cn0_0 += 10 * np.log10(defaults.GLOL1_CHANNEL_BANDWIDTH_HZ)
+
     params['cn0_0'] = cn0_0
-    params['coherent_ms'] = 1
-    params['coherent_iter'] = 1
-    params['loop_filter_params'] = defaults.l1ca_stage1_loop_filter_params
-    params['lock_detect_params'] = defaults.l1ca_lock_detect_params_opt
     params['IF'] = params['samples'][glo_constants.GLO_L1]['IF']
     params['prn_code'] = GLOCode
     params['code_freq_init'] = params['acq'].doppler * \
         glo_constants.glo_chip_rate / glo_constants.glo_l1
+
+    params['track_params'] = defaults.glol1_track_params
+    params['loop_filter_params_template'] = \
+        defaults.glol1_loop_filter_params_template
+
+    params['lock_detect_params'] = defaults.glol1_lock_detect_params
     params['chipping_rate'] = glo_constants.glo_chip_rate
-    params['sample_index'] = 0
-    params['alias_detector'] = \
-        alias_detector.AliasDetectorGLO(params['coherent_ms'])
+    params['sample_index'] = params['samples']['sample_index']
+    params['carrier_freq'] = glo_constants.glo_l1
+
+    params['fsm_states_all'] = defaults.glo_fsm_states
+
+    self.bit_sync = False
 
     TrackingChannel.__init__(self, params)
 
@@ -1196,42 +1207,14 @@ def _run_preprocess(self):
 
     self.coherent_iter = self.coherent_ms
 
-  def _short_n_long_preprocess(self):
-    if self.stage1:
-      self.E = self.P = self.L = 0.j
-    else:
-      # When simulating short and long cycles, short step resets EPL
-      # registers, and long one adds up to them
-      if self.short_step:
-        self.E = self.P = self.L = 0.j
-        self.coherent_iter = 1
-      else:
-        self.coherent_iter = self.coherent_ms - 1
-
-    self.code_chips_to_integrate = glo_constants.glo_code_len
-
-    return self.coherent_iter, self.code_chips_to_integrate
-
-  def _short_n_long_postprocess(self):
-    more_integration_needed = False
-    if not self.stage1:
-      if self.short_step:
-        # In case of short step - go to next integration period
-        self.short_step = False
-        more_integration_needed = True
-      else:
-        # Next step is short cycle
-        self.short_step = True
-    return more_integration_needed
-
-  def _run_postprocess(self):
+  def _run_nav_data_decoding(self):
     """
     Run GLO L1 coherent integration postprocessing.
     Runs navigation bit sync decoding operation and
     GLO L1 to GLO L2 handover.
     """
 
-    # Handover to L2C if possible
+    # Handover to L2 if possible
     if self.glol2_handover and not self.glol2_handover_acq and \
         glo_constants.GLO_L2 in  self.samples and \
        'samples' in self.samples[glo_constants.GLO_L2]:  # and sync:

tests/test_tracking.py

@@ -187,7 +187,7 @@ def test_tracking_gps():
   run_track_test(samples, 0.6, init_doppler, init_code_phase, prn, file_format,
                  freq_profile)
   run_track_test(samples, 0.3, init_doppler, init_code_phase, prn, file_format,
-    freq_profile)
+                 freq_profile)
   run_track_test(samples, 0.3, init_doppler, init_code_phase, prn, file_format,
                  freq_profile, short_long_cycles=True)
 
@@ -253,9 +253,9 @@ def test_tracking_glo():
   run_track_test(samples, 0.6, init_doppler, init_code_phase, prn, file_format,
                  freq_profile)
   run_track_test(samples, 0.3, init_doppler, init_code_phase, prn, file_format,
-                 freq_profile, pipelining=0.5)
+                 freq_profile)
   run_track_test(samples, 0.3, init_doppler, init_code_phase, prn, file_format,
-                 freq_profile, short_long_cycles=0.5)
+                 freq_profile, short_long_cycles=True)
 
   os.remove(samples)