5_conclusion.tex

\section{Conclusion}
It gets more and more important to generate uniform structures in the hardware design process to manage the increasing number of transistors available on a chip.\\
Thereby the RFG provides the functionality to generate the hardware description, verification model and documentation for RFs. This leads to a reduction in development time by avoiding time consuming and error prone tasks. The RF description syntax of the RFG is clearer than those of both SystemRDL and Spirit IP-XACT and supports hierarchical RFs, making it more suitable for large designs. Additionally, the verification model provides the ability to create reusable tests by accessing registers by their name instead of their address via the software interface. Furthermore, the RFG can easily be extended with generators for other parts of the RF.