HyperRAM stability fixes

Taken from the C64 core:
MJoergen@a227944
MJoergen@ce927cb

Author: sy2002

M2M/vhdl/controllers/hyperram/hyperram_ctrl.vhd

@@ -55,6 +55,7 @@ architecture synthesis of hyperram_ctrl is
       INIT_ST,
       COMMAND_ADDRESS_ST,
       WAIT_ST,
+      WAIT2_ST,
       SAMPLE_RWDS_ST,
       LATENCY_ST,
       READ_ST,
@@ -144,17 +145,35 @@ begin
                end if;
 
             when WAIT_ST =>
+               state <= WAIT2_ST;
+
+            when WAIT2_ST =>
                state <= SAMPLE_RWDS_ST;
 
             when SAMPLE_RWDS_ST =>
                if hb_rwds_in_i = '1' then
-                  latency_count <= 2*G_LATENCY - 4;
-                  count_long <= count_long + 1;
+                  latency_count <= 2*G_LATENCY - 5;
+                  count_long    <= count_long + 1;
+                  state         <= LATENCY_ST;
                else
-                  latency_count <= G_LATENCY - 4;
                   count_short <= count_short + 1;
+                  if G_LATENCY >= 5 then
+                     latency_count <= G_LATENCY - 5;
+                     state         <= LATENCY_ST;
+                  else
+                     if read = '1' then
+                        read_clk_count    <= burst_count+1;
+                        read_return_count <= burst_count;
+                        hb_read_o         <= '1';
+                        state             <= READ_ST;
+                     else
+                        write_clk_count <= burst_count;
+                        hb_dq_oe_o      <= '1';
+                        hb_rwds_oe_o    <= '1';
+                        state           <= WRITE_ST;
+                     end if;
+                  end if;
                end if;
-               state <= LATENCY_ST;
 
             when LATENCY_ST =>
                if latency_count > 0 then

M2M/vhdl/controllers/hyperram/hyperram_rx.vhd

@@ -36,6 +36,7 @@ architecture synthesis of hyperram_rx is
 
    signal rwds_dq_in    : std_logic_vector(15 downto 0);
    signal rwds_in_delay : std_logic;
+   signal rwds_in_delay_idelay : std_logic;
 
    signal ctrl_dq_ie   : std_logic;
    signal ctrl_dq_ie_d : std_logic;
@@ -58,7 +59,7 @@ begin
       generic map (
          IDELAY_TYPE           => "FIXED",
          DELAY_SRC             => "IDATAIN",
-         IDELAY_VALUE          => 20,    -- Number of taps.
+         IDELAY_VALUE          => 12,    -- Number of taps: 6/21/24 sy2002 implemented Antti Lukats proposal
          HIGH_PERFORMANCE_MODE => "TRUE",
          SIGNAL_PATTERN        => "CLOCK",
          REFCLK_FREQUENCY      => 200.0, -- Each tap on average 5/32 ns.
@@ -76,9 +77,23 @@ begin
          idatain     => hr_rwds_in_i,
          datain      => '0',
          ldpipeen    => '0',
-         dataout     => rwds_in_delay,
+         dataout     => rwds_in_delay_idelay,
          cntvalueout => open
       ); -- delay_rwds_inst
+    
+   -- 6/21/24 sy2002 implemented Antti Lukats proposal   
+   -- add local buffer, is faster than BUFG insertion!
+   BUFR_inst : BUFR
+   generic map (
+      BUFR_DIVIDE => "BYPASS",   -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
+      SIM_DEVICE => "7SERIES"    -- Must be set to "7SERIES"
+   )
+   port map (
+      O => rwds_in_delay,        -- 1-bit output: Clock output port
+      CE => '1',                 -- 1-bit input: Active high, clock enable (Divided modes only)
+      CLR => '0',                -- 1-bit input: Active high, asynchronous clear (Divided modes only)
+      I => rwds_in_delay_idelay  -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
+   );      
 
    -- Transfer the RWDS signal to the clk_i domain. This is used solely to determine the
    -- latency mode of the current transaction.