RELEASE 1.3 (incl stable bitstreams)

Author: sy2002

README.md

@@ -47,7 +47,7 @@ Getting Started
 
 * Compile the assembler and the ROM generator by entering
   `cc assembler/qasm.c -o assembler/qasm` and then
-  `cc assembler/qasm2rom.c -o assembler/qasm2rom` 
+  `cc assembler/qasm2rom.c -o assembler/qasm2rom -std=c99` 
   on the command line from the root folder of the GIT repository.
 
 * Compile the mandelbrot demo by entering

VERSIONS.txt

@@ -1,4 +1,4 @@
-Version x.y    May, 6 2016
+Version 1.3    May, 6 2016
 ==========================
 
 * CPU: Significant speed improvement by removing old tristate driver:
@@ -11,15 +11,18 @@ Version x.y    May, 6 2016
 * ALU: Fixed CMP opcode behaviour: using the N flag it now treats the
   operands as unsigned and using the V flag it treats them as signed.
 * ALU: Fixed V flag CPU bug (AND, OR, XOR)
-* CYCLE COUNTER: Added.
+* CYCLE COUNTER: Added. Counts clock cycles. Can be used for performance
+  testing, as shown in test_programs/mandel_perf_test.asm.
 * DEBUG MODE: If switch #2 is ON, then the LEDs are showing the current
   address bus value in real-time and on HALT the TIL shows the address
   of the executed HALT command.
 * ASSEMBLER: Is able to handle labels on separate lines, improved error
-  handling, CMP allows a constant as second operand
+  handling, CMP allows a constant as second operand.
 * EMULATOR: Fixed CMP opcode behaviour (see above), fixed similar CPU bug
-  as described above. Outputs address of HALT instruction.
-* DOCUMENTATION: Added a programming card
+  as described above. Outputs address of HALT instruction. Also emulates
+  the new cycle counter (register compatible), but instead of counting
+  clock cycles, it is counting instructions.
+* DOCUMENTATION: Added a programming card.
 
 Version 1.21   February, 13 2016
 ================================

dist_kit/qnice.bit

@@ -126,10 +126,6 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
     </file>
-    <file xil_pn:name="../vhdl/EAE.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="135"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="135"/>
-    </file>
   </files>
 
   <properties>

forth/forth.asm

@@ -2,4 +2,4 @@ PORE$NEWLINE  .ASCII_W "\n"
 
 ; PORE$RESETMSG .ASCII_W "QNICE-FPGA [WIP] [only 16 reg-banks!] by sy2002 in May 2016 (GIT #"
 
-PORE$RESETMSG .ASCII_W "QNICE-FPGA Version 1.3 by sy2002 in May 2016 (GIT COMMIT #d6f58a0)\n"
+PORE$RESETMSG .ASCII_W "QNICE-FPGA Version 1.3 by sy2002 in May 2016 (GIT COMMIT #fba6df4)\n"

nexys4ddr/env1.xise

@@ -16,7 +16,7 @@
 ;  CPU revision GIT #60f1294 needs 02CF 1666 = 47.126.118 cycles = 0,9425 sec
 ;  CPU revision GIT #83e2936 needs 02CC 0531 = 46.925.105 cycles = 0,9385 sec
 ;
-;  using the emulator's instruction counter feature we learned, that this
+;  using the instruction counter feature of the emulator we learned, that this
 ;  test program consists of 12.143.388 instructions, i.e. the FGA QNICE system
 ;  performs at an average of 3,86 cycles/instruction which leads to 
 ;  a system performance 12,93 MIPS.