eclipse-threadx · Nov 20, 2024 · Nov 20, 2024 · Nov 20, 2024 · Nov 20, 2024 · Nov 20, 2024
diff --git a/.devcontainer/devcontainer.json b/.devcontainer/devcontainer.json
@@ -10,4 +10,4 @@
 	"remoteUser": "vscode",
 
     "runArgs": [ "--cap-add=NET_ADMIN"]
-}
+}
diff --git a/.gitattributes b/.gitattributes
@@ -37,4 +37,4 @@ configure        eol=lf
 
 *.cmake          whitespace=tab-in-indent
 *.rst            whitespace=tab-in-indent conflict-marker-size=79
-*.txt            whitespace=tab-in-indent
+*.txt            whitespace=tab-in-indent
diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md
@@ -2,4 +2,4 @@
 <!--- Put an `x` in all the boxes that apply. -->
 - [ ] Updated function header with a short description and version number
 - [ ] Added test case for bug fix or new feature
-- [ ] Validated on real hardware <!-- hardware - toolchain -->
+- [ ] Validated on real hardware <!-- hardware - toolchain -->
diff --git a/.github/workflows/ci_cortex_m.yml b/.github/workflows/ci_cortex_m.yml
@@ -3,12 +3,12 @@
 name: cortex_m
 
 # Controls when the action will run. Triggers the workflow on push or pull request
-# events but only for the master branch
+# events but only for the dev branch
 on:
   push:
-    branches: [ master ]
+    branches: [ dev ]
   pull_request:
-    branches: [ master ]
+    branches: [ dev ]
     paths:
       - ".github/workflows/ci_cortex_m.yml"
       - 'common/**'
@@ -39,39 +39,24 @@ jobs:
       with:
         submodules: true
 
-    # Store the arm compilers in the cache to speed up builds
-    - name: Cache arm-none-eabi-gcc tools
-      id: cache-arm-gcc
-      uses: actions/cache@v1
-      with:
-        path: $HOME/arm-none-eabi-gcc-9-2019-q4
-        key: ${{ runner.os }}-arm-gcc-9-2019-q4
-
     # Get the arm-non-eabi-gcc toolchain   
     - name: Install arm-none-eabi-gcc
-      uses: fiam/arm-none-eabi-gcc@v1
+      uses: carlosperate/arm-none-eabi-gcc-action@v1
       if: steps.cache-arm-gcc.outputs.cache-hit != 'true'
       with:
-          release: '9-2019-q4' # The arm-none-eabi-gcc release to use.
-          directory: $HOME/arm-none-eabi-gcc-9-2019-q4
+          release: '13.3.Rel1' # The arm-none-eabi-gcc release to use.
 
     # Get CMake into the environment
-    - name: Install cmake 3.19.1
-      uses: lukka/get-cmake@v3.19.1
+    - name: Install cmake
+      uses: lukka/get-cmake@v3.31.0
 
     # Get Ninja into the environment
     - name: Install ninja-build
-      uses: seanmiddleditch/gha-setup-ninja@v3
+      uses: seanmiddleditch/gha-setup-ninja@v5
 
     # Prepare the build system
     - name: Prepare build system
       run: cmake -Bbuild -DCMAKE_TOOLCHAIN_FILE=./cmake/cortex_m${{ matrix.port }}.cmake -GNinja .
-      env:
-        PATH: "$HOME/arm-none-eabi-gcc-9-2019-q4/bin:$PATH"
 
     - name: Compile and link
       run: cmake --build ./build
-      env:
-        PATH: "$HOME/arm-none-eabi-gcc-9-2019-q4/bin:$PATH"
-
-
diff --git a/.github/workflows/ports_arch_check.yml b/.github/workflows/ports_arch_check.yml
@@ -3,10 +3,10 @@
 name: ports_arch_check
 
 # Controls when the action will run. Triggers the workflow on push or pull request
-# events but only for the master branch
+# events but only for the dev branch
 on:
   pull_request:
-    branches: [ master ]
+    branches: [ dev ]
     paths:
       - ".github/workflows/ports_arch_check.yml"
       - 'common/**'
@@ -28,7 +28,7 @@ jobs:
     steps:
     # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it
     - name: Checkout sources recursively
-      uses: actions/checkout@v2
+      uses: actions/checkout@v4
       with:
         token: ${{ secrets.REPO_SCOPED_TOKEN }}
         submodules: true
@@ -38,36 +38,10 @@ jobs:
       run: |
         scripts/copy_armv7_m.sh && scripts/copy_armv8_m.sh && scripts/copy_module_armv7_m.sh
         if [[ -n $(git status --porcelain -uno) ]]; then
-          echo "Ports for ARM architecture is not updated"
+          echo "Ports for Arm architecture is not updated"
           git status
           exit 1
         fi
 
-  cortex-a:
-    # Check ports for cortex-a
-    runs-on: windows-latest
-
-    # Steps represent a sequence of tasks that will be executed as part of the job
-    steps:
-    # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it
-    - name: Checkout sources recursively
-      uses: actions/checkout@v2
-      with:
-        token: ${{ secrets.REPO_SCOPED_TOKEN }}
-        submodules: true
-
-    # Copy ports arch
-    - name: Copy ports arch
-      run: |
-        cd ports_arch/ARMv7-A
-        pwsh -Command ./update.ps1 -PortSets tx -CopyCommonFiles -CopyPortFiles -CopyExample -PatchFiles
-        cd ../../ports_arch/ARMv8-A
-        pwsh -Command ./update.ps1 -PortSets tx,tx_smp -CopyCommonFiles -CopyPortFiles -CopyExample -PatchFiles
-        if ((git status --porcelain -uno) -ne $null) {
-          Write-Host "Ports for ARM architecture is not updated"
-          git status
-          Exit 1
-        }
-
-
-
+  # FIXME: Re-enable the checks for Arm Cortex-A
+  # cortex-a:
diff --git a/.github/workflows/regression_template.yml b/.github/workflows/regression_template.yml
@@ -77,7 +77,7 @@ jobs:
       run: ${{ inputs.test_script }}
 
     - name: Publish Test Results
-      uses: EnricoMi/publish-unit-test-result-action@v2.11.0
+      uses: EnricoMi/publish-unit-test-result-action@v2.18.0
       if: always()
       with:
         check_name: Test Results ${{ inputs.result_affix }}
@@ -86,7 +86,7 @@ jobs:
           
     - name: Upload Test Results
       if: success() || failure()
-      uses: actions/upload-artifact@v3.1.3
+      uses: actions/upload-artifact@v4
       with:
         name: test_reports ${{ inputs.result_affix }}
         path: |
@@ -95,7 +95,7 @@ jobs:
           ${{ inputs.cmake_path }}/build/**/regression/output_files/*.bin
     
     - name: Configure GitHub Pages
-      uses: actions/configure-pages@v3.0.6
+      uses: actions/configure-pages@v5
 
     - name: Generate Code Coverage Results Summary
       if: (!inputs.skip_coverage)
@@ -115,7 +115,7 @@ jobs:
 
     - name: Create CheckRun for Code Coverage
       if: ((github.event_name == 'push') || (github.event_name == 'workflow_dispatch') || (github.event.pull_request.head.repo.full_name == github.repository)) && (!inputs.skip_coverage)
-      uses: LouisBrunner/checks-action@v1.6.2
+      uses: LouisBrunner/checks-action@v2.0.0
       with:
         token: ${{ secrets.GITHUB_TOKEN }}
         name: Code Coverage ${{ inputs.result_affix }}
@@ -141,15 +141,15 @@ jobs:
         fi
           
     - name: Upload Code Coverage Artifacts
-      uses: actions/upload-artifact@v3.1.3
+      uses: actions/upload-artifact@v4
       if: (inputs.skip_deploy && !inputs.skip_coverage)
       with:
-        name: coverage_report
+        name: coverage_report-${{inputs.context}}-${{inputs.job-index}}
         path: ${{ inputs.cmake_path }}/coverage_report
         retention-days: 1
 
     - name: Upload Code Coverage Pages
-      uses: actions/upload-pages-artifact@v2.0.0
+      uses: actions/upload-pages-artifact@v3
       if: (!inputs.skip_deploy && !inputs.skip_coverage)
       with:
         path: ${{ inputs.cmake_path }}/coverage_report/${{ inputs.coverage_name }}
@@ -166,13 +166,14 @@ jobs:
       id-token: write
 
     steps:
-    - uses: actions/download-artifact@v3
+    - uses: actions/download-artifact@v4
       if: ${{ inputs.skip_test }}
       with:
-        name: coverage_report
+        pattern: coverage_report-${{inputs.context}}*
+        merge-multiple: true
 
     - name: Upload Code Coverage Pages
-      uses: actions/upload-pages-artifact@v2.0.0
+      uses: actions/upload-pages-artifact@v3
       if: ${{ inputs.skip_test }}
       with:
         path: .
@@ -184,7 +185,7 @@ jobs:
 
     - name: Deploy GitHub Pages site
       id: deployment
-      uses: actions/deploy-pages@v1.2.9
+      uses: actions/deploy-pages@v4
 
     - name: Write Code Coverage Report URL
       run: >-

diff --git a/.github/workflows/regression_test.yml b/.github/workflows/regression_test.yml
@@ -1,13 +1,13 @@
 name: regression_test
 
 # Controls when the action will run. Triggers the workflow on push or pull request
-# events but only for the master branch
+# events but only for the dev branch
 on:
   workflow_dispatch:
   push:
-    branches: [ master ]
+    branches: [ dev ]
   pull_request:
-    branches: [ master ]
+    branches: [ dev ]
 
 # A workflow run is made up of one or more jobs that can run sequentially or in parallel
 jobs:
@@ -32,4 +32,4 @@ jobs:
     uses: ./.github/workflows/regression_template.yml
     with:
       skip_test: true
-      deploy_list: "ThreadX SMP"
+      deploy_list: "ThreadX SMP"
diff --git a/CMakeLists.txt b/CMakeLists.txt
@@ -1,4 +1,4 @@
-cmake_minimum_required(VERSION 3.0.0 FATAL_ERROR)
+cmake_minimum_required(VERSION 3.5 FATAL_ERROR)
 
 # Set up the project
 project(threadx
@@ -69,4 +69,4 @@ set(CPACK_SOURCE_IGNORE_FILES
   ".*~$"
 )
 set(CPACK_VERBATIM_VARIABLES YES)
-include(CPack)
+include(CPack)
diff --git a/README.md b/README.md
@@ -197,7 +197,7 @@ Instruction for building the ThreadX as static library using Arm GNU Toolchain a
     An example of building the library for Cortex-M4:
 
     ```bash
-    $ cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=cmake/cortex_m4.cmake .
+    $ cmake -Bbuild -GNinja --toolchain cmake/cortex_m4.cmake .
 
     $ cmake --build ./build
     ```

diff --git a/cmake/arm-none-eabi.cmake b/cmake/arm-none-eabi.cmake
@@ -26,4 +26,4 @@ SET(CMAKE_ASM_FLAGS_DEBUG "-g -ggdb3" CACHE INTERNAL "asm debug compiler flags")
 
 SET(CMAKE_C_FLAGS_RELEASE "-O3" CACHE INTERNAL "c release compiler flags")
 SET(CMAKE_CXX_FLAGS_RELEASE "-O3" CACHE INTERNAL "cxx release compiler flags")
-SET(CMAKE_ASM_FLAGS_RELEASE "" CACHE INTERNAL "asm release compiler flags")
+SET(CMAKE_ASM_FLAGS_RELEASE "" CACHE INTERNAL "asm release compiler flags")
diff --git a/cmake/cortex_m0.cmake b/cmake/cortex_m0.cmake
@@ -10,4 +10,4 @@ set(VFP_FLAGS "")
 set(SPEC_FLAGS "--specs=nosys.specs")
 # set(LD_FLAGS "-nostartfiles")
 
-include(${CMAKE_CURRENT_LIST_DIR}/arm-none-eabi.cmake)
+include(${CMAKE_CURRENT_LIST_DIR}/arm-none-eabi.cmake)
diff --git a/cmake/cortex_m3.cmake b/cmake/cortex_m3.cmake
@@ -10,4 +10,4 @@ set(VFP_FLAGS "")
 set(SPEC_FLAGS "--specs=nosys.specs")
 # set(LD_FLAGS "-nostartfiles")
 
-include(${CMAKE_CURRENT_LIST_DIR}/arm-none-eabi.cmake)
+include(${CMAKE_CURRENT_LIST_DIR}/arm-none-eabi.cmake)
diff --git a/cmake/cortex_m4.cmake b/cmake/cortex_m4.cmake
@@ -10,4 +10,4 @@ set(VFP_FLAGS "")
 set(SPEC_FLAGS "--specs=nosys.specs")
 # set(LD_FLAGS "-nostartfiles")
 
-include(${CMAKE_CURRENT_LIST_DIR}/arm-none-eabi.cmake)
+include(${CMAKE_CURRENT_LIST_DIR}/arm-none-eabi.cmake)
diff --git a/cmake/cortex_m7.cmake b/cmake/cortex_m7.cmake
@@ -10,4 +10,4 @@ set(VFP_FLAGS "")
 set(SPEC_FLAGS "--specs=nosys.specs")
 # set(LD_FLAGS "-nostartfiles")
 
-include(${CMAKE_CURRENT_LIST_DIR}/arm-none-eabi.cmake)
+include(${CMAKE_CURRENT_LIST_DIR}/arm-none-eabi.cmake)
diff --git a/cmake/utilities.cmake b/cmake/utilities.cmake
@@ -12,4 +12,4 @@ function(add_azrtos_component_dir dirname)
     list(APPEND tmp "azrtos::${dirname}")
     # Copy the temp back up to the parent list
     set(azrtos_targets ${tmp} PARENT_SCOPE)
-endfunction()
+endfunction()
diff --git a/docs/revision_history.txt b/docs/revision_history.txt
@@ -1550,4 +1550,4 @@ Below is the revision history for 5.x.
             tx*.h                                           Changed comments and copyright header.
 
 
-12-12-2012  Initial ThreadX SMP generic code version 5.6.1.
+12-12-2012  Initial ThreadX SMP generic code version 5.6.1.
diff --git a/ports/arm11/gnu/example_build/libnosys.a b/ports/arm11/gnu/example_build/libnosys.a
diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/targetConfigs/readme.txt b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/targetConfigs/readme.txt
@@ -6,4 +6,4 @@ connection settings will either modify an existing or generate a new target-conf
 if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively,
 you may create your own target-configuration file for this project and manage it manually. You can
 always switch back to automatic target-configuration management by checking the "Manage the project's
-target-configuration automatically" checkbox on the project's Properties > General page.
+target-configuration automatically" checkbox on the project's Properties > General page.
diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/targetConfigs/readme.txt b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/targetConfigs/readme.txt
@@ -6,4 +6,4 @@ connection settings will either modify an existing or generate a new target-conf
 if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively,
 you may create your own target-configuration file for this project and manage it manually. You can
 always switch back to automatic target-configuration management by checking the "Manage the project's
-target-configuration automatically" checkbox on the project's Properties > General page.
+target-configuration automatically" checkbox on the project's Properties > General page.
diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.txt b/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.txt
@@ -12,4 +12,4 @@ LOAD 0x80000000
 
   ARM_LIB_STACKHEAP 0x80090000 EMPTY -0x00040000
   {}
-}
+}
diff --git a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s
@@ -175,6 +175,9 @@ _tx_initialize_low_level
 ;    /* Configure SysTick.  */
 ;
     LDR     r0, =0xE000E000                         ; Build address of NVIC registers
+    LDR     r1, =0
+    STR     r1, [r0, #0x10]                         ; Reset SysTick Control
+    STR     r1, [r0, #0x18]                         ; Reset SysTick Counter Value
     LDR     r1, =SYSTICK_CYCLES
     STR     r1, [r0, #0x14]                         ; Setup SysTick Reload Value
     MOVS    r1, #0x7                                ; Build SysTick Control Enable Value

diff --git a/ports/cortex_m0/gnu/example_build/cortexm0_crt0.S b/ports/cortex_m0/gnu/example_build/cortexm0_crt0.S
@@ -116,4 +116,3 @@ memory_set_done:
   .section .stack, "wa", %nobits
   .section .stack_process, "wa", %nobits
   .section .heap, "wa", %nobits
-  
diff --git a/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S
@@ -133,6 +133,9 @@ _tx_initialize_low_level:
 @    /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference.  */
 @
     LDR     r0, =0xE000E000                         @ Build address of NVIC registers
+    LDR     r1, =0
+    STR     r1, [r0, #0x10]                         // Reset SysTick Control
+    STR     r1, [r0, #0x18]                         // Reset SysTick Counter Value
     LDR     r1, =SYSTICK_CYCLES
     STR     r1, [r0, #0x14]                         // Setup SysTick Reload Value
     LDR     r1, =0x7                                // Build SysTick Control Enable Value

diff --git a/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s
@@ -124,6 +124,9 @@ _tx_initialize_low_level:
 ;    /* Configure SysTick.  */
 ;
     LDR     r0, =0xE000E000                         ; Build address of NVIC registers
+    LDR     r1, =0
+    STR     r1, [r0, #0x10]                         ; Reset SysTick Control
+    STR     r1, [r0, #0x18]                         ; Reset SysTick Counter Value
     LDR     r1, =SYSTICK_CYCLES
     STR     r1, [r0, #0x14]                         ; Setup SysTick Reload Value
     MOVS    r1, #0x7                                ; Build SysTick Control Enable Value

diff --git a/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s b/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s
@@ -175,6 +175,9 @@ _tx_initialize_low_level
 ;    /* Configure SysTick.  */
 ;
     LDR     r0, =0xE000E000                         ; Build address of NVIC registers
+    LDR     r1, =0
+    STR     r1, [r0, #0x10]                         ; Reset SysTick Control
+    STR     r1, [r0, #0x18]                         ; Reset SysTick Counter Value
     LDR     r1, =SYSTICK_CYCLES
     STR     r1, [r0, #0x14]                         ; Setup SysTick Reload Value
     MOVS    r1, #0x7                                ; Build SysTick Control Enable Value

diff --git a/ports/cortex_m23/ac6/example_build/Debug.ini b/ports/cortex_m23/ac6/example_build/Debug.ini
@@ -1,4 +1,4 @@
 LOAD "..\\demo_threadx_non-secure_zone\\Objects\\demo_threadx_non-secure_zone.axf" incremental
 LOAD "..\\demo_secure_zone\\Objects\\demo_secure_zone.axf" incremental
 RESET
-g, \\demo_secure_zone\main_s\main
+g, \\demo_secure_zone\main_s\main
-Original file line number
+Diff line change
@@ @@ -10,4 +10,4 @@ @@
     	"remoteUser": "vscode",
         "runArgs": [ "--cap-add=NET_ADMIN"]
-    }
+    }
Original file line number	Diff line number	Diff line change
		@@ -1550,4 +1550,4 @@ Below is the revision history for 5.x.
		tx*.h Changed comments and copyright header.


		12-12-2012 Initial ThreadX SMP generic code version 5.6.1.
		12-12-2012 Initial ThreadX SMP generic code version 5.6.1.
Original file line number	Diff line number	Diff line change
		@@ -116,4 +116,3 @@ memory_set_done:
		.section .stack, "wa", %nobits
		.section .stack_process, "wa", %nobits
		.section .heap, "wa", %nobits