Fix critical miss queue pushing

Author: ArijusGrotuzas

src/main/scala/caches/hardware/pipelined/stages/Rep.scala

@@ -85,6 +85,7 @@ class Rep(nCores: Int, nSets: Int, nWays: Int, nMshrs: Int, reqIdWidth: Int, tag
   val updateStageValid = WireDefault(false.B)
   val updateStageIsHit = WireDefault(false.B)
   val updateStageIsCrit = WireDefault(false.B)
+  val updateStageMshrIdx = WireDefault(0.U(log2Up(nWays).W))
 
   def updateValidAndDirtyBits(inValid: Vec[Bool], inDirty: Vec[Bool], inTags: Vec[UInt], currIdx: UInt, useInvalidate: Boolean = true): (Vec[Bool], Vec[Bool], Vec[UInt]) = {
     val newValidBits = VecInit(Seq.fill(nWays)(false.B))
@@ -126,19 +127,28 @@ class Rep(nCores: Int, nSets: Int, nWays: Int, nMshrs: Int, reqIdWidth: Int, tag
   // We compute a half miss check here, since we do not need to know the replacement way either way
   val halfMissCheckInMissFifoNonCrit = halfMissCheck(io.rep.index, io.rep.tag, io.missNonCritInfo.currentIndexes, io.missNonCritInfo.currentTags, io.missNonCritInfo.validMSHRs)
   val halfMissCheckInMissFifoCrit = halfMissCheck(io.rep.index, io.rep.tag, io.missCritInfo.currentIndexes, io.missCritInfo.currentTags, io.missCritInfo.validMSHRs)
-  val halfMissCheckInMissFifo = (halfMissCheckInMissFifoCrit._1 || halfMissCheckInMissFifoNonCrit._1, Mux(halfMissCheckInMissFifoCrit._1, halfMissCheckInMissFifoCrit._2, halfMissCheckInMissFifoNonCrit._2))
 
   val halfMissCheckInUpdateStage = io.rep.index === updateStageIndex && io.rep.tag === updateStageTag && updateStageValid && !updateStageIsHit
-  val halfMissIdxInUpdateStage = Mux(updateStageIsCrit, io.missCritInfo.wrPtr, io.missNonCritInfo.wrPtr)
 
-  val isHalfMiss = halfMissCheckInMissFifo._1 || halfMissCheckInUpdateStage
-  val halfMissIdx = Mux(halfMissCheckInMissFifo._1, halfMissCheckInMissFifo._2, halfMissIdxInUpdateStage)
+  val isHalfMiss = halfMissCheckInMissFifoNonCrit._1 || halfMissCheckInMissFifoCrit._1 || halfMissCheckInUpdateStage
+  val halfMissIdx = WireDefault(0.U(log2Up(nMshrs).W))
+  val isHalfMissInCrit = WireDefault(false.B)
+  when(halfMissCheckInUpdateStage) {
+    halfMissIdx := updateStageMshrIdx
+    isHalfMissInCrit := updateStageIsCrit
+  } .elsewhen (halfMissCheckInMissFifoCrit._1) {
+   halfMissIdx := halfMissCheckInMissFifoCrit._2
+   isHalfMissInCrit := true.B
+  } .elsewhen (halfMissCheckInMissFifoNonCrit._1) {
+   halfMissIdx := halfMissCheckInMissFifoNonCrit._2
+   isHalfMissInCrit := false.B
+  }
 
   val coreIdReg = PipelineReg(io.rep.coreId, 0.U, !io.stall)
   val reqValidReg = PipelineReg(io.rep.reqValid, false.B, !io.stall)
   val isHalfMissReg = PipelineReg(isHalfMiss, false.B, !io.stall)
   val halfMissIdxReg = PipelineReg(halfMissIdx, 0.U, !io.stall)
-  val halfMissInCritReg = PipelineReg(updateStageIsCrit || halfMissCheckInMissFifoCrit._1, false.B, !io.stall)
+  val halfMissInCritReg = PipelineReg(isHalfMissInCrit, false.B, !io.stall)
   val reqIdReg = PipelineReg(io.rep.reqId, 0.U, !io.stall)
   val reqRwReg = PipelineReg(io.rep.reqRw, false.B, !io.stall)
   val wDataReg = PipelineReg(io.rep.wData, 0.U, !io.stall)
@@ -154,18 +164,14 @@ class Rep(nCores: Int, nSets: Int, nWays: Int, nMshrs: Int, reqIdWidth: Int, tag
 
   val validAndDirtyBits2 = updateValidAndDirtyBits(validBitsReg, dirtyBitsReg, setTagsReg, indexReg, useInvalidate = false)
   val isHit = checkIfHit(validAndDirtyBits2._1, validAndDirtyBits2._3, tagReg) // Long combinational path // TODO: Move one pipeline register back instead
-
-  updateStageIndex := indexReg
-  updateStageTag := tagReg
-  updateStageValid := reqValidReg
-  updateStageIsHit := isHit._1
+  val isHalfMissInUpdateStage = isHalfMissReg && !(!halfMissInCritReg && io.repPol.updateCoreReachedLimit) // If the core has reached limit and there is already a request in the non-critical q then we turn it into a full new request
 
   val repWay = io.repPol.replaceWay
   val repWayValid = io.repPol.isValid
   val isRepDirty = validAndDirtyBits2._2(repWay)
   val isRepLineValid = validAndDirtyBits2._1(repWay)
   val dirtyTag = validAndDirtyBits2._3(repWay)
-  val evict = reqValidReg && (!isHit._1 && repWayValid && !isHalfMissReg) && !io.stall
+  val evict = reqValidReg && (!isHit._1 && repWayValid && !isHalfMissInUpdateStage) && !io.stall
 
   // Replacement policy connections
 
@@ -184,7 +190,7 @@ class Rep(nCores: Int, nSets: Int, nWays: Int, nMshrs: Int, reqIdWidth: Int, tag
   io.repPol.nonCritWbEntryIsCrit := io.nonCritWbEntryIsCrit
 
   // Push request or a command to the miss fifo
-  io.isMissPushCrit := halfMissInCritReg || io.repPol.updateCoreReachedLimit
+  io.isMissPushCrit := (isHalfMissInUpdateStage && halfMissInCritReg) || io.repPol.updateCoreReachedLimit
   updateStageIsCrit := io.repPol.updateCoreReachedLimit && reqValidReg
 
   // Miss fifo connections
@@ -197,13 +203,13 @@ class Rep(nCores: Int, nSets: Int, nWays: Int, nMshrs: Int, reqIdWidth: Int, tag
   io.missFifoPush.pushReqEntry.incidentCoreId := coreIdReg
   io.missFifoPush.pushReqEntry.isCrit := io.repPol.updateCoreIsCrit
 
-  io.missFifoPush.pushCmd := isHalfMissReg && reqValidReg && !isHit._1 && !io.stall // Push a half miss command
+  io.missFifoPush.pushCmd := isHalfMissInUpdateStage && reqValidReg && !isHit._1 && !io.stall // Push a half miss command
   io.missFifoPush.mshrIdx := halfMissIdxReg
   io.missFifoPush.pushCmdEntry.reqId := reqIdReg
   io.missFifoPush.pushCmdEntry.coreId := coreIdReg
   io.missFifoPush.pushCmdEntry.blockOffset := blockOffsetReg
 
-  io.missFifoPush.updateByteEn := (isHalfMissReg && reqValidReg && !isHit._1 && reqRwReg && !io.stall) // Update a byte mask if it is a write request and a half miss
+  io.missFifoPush.updateByteEn := (isHalfMissInUpdateStage && reqValidReg && !isHit._1 && reqRwReg && !io.stall) // Update a byte mask if it is a write request and a half miss
   io.missFifoPush.updateByteEnVal := byteEnReg
   io.missFifoPush.updateByteEnCol := blockOffsetReg
   io.missFifoPush.updateByteEnRow := halfMissIdxReg
@@ -233,7 +239,7 @@ class Rep(nCores: Int, nSets: Int, nWays: Int, nMshrs: Int, reqIdWidth: Int, tag
   io.read.wData := wDataReg
   io.read.byteEn := blockByteMask((blockWidth / 8) -1, 0)
   io.read.repValid := repWayValid
-  io.read.repWay := Mux(isHalfMissReg, Mux(halfMissInCritReg, io.missCritInfo.replacementWays(halfMissIdxReg), io.missNonCritInfo.replacementWays(halfMissIdxReg)), repWay) // If it is a half miss we give the replacement way of the full miss for a write request
+  io.read.repWay := Mux(isHalfMissInUpdateStage, Mux(halfMissInCritReg, io.missCritInfo.replacementWays(halfMissIdxReg), io.missNonCritInfo.replacementWays(halfMissIdxReg)), repWay) // If it is a half miss we give the replacement way of the full miss for a write request
   io.read.isHit := isHit._1
   io.read.hitWay := isHit._2
   io.read.isRepDirty := isRepDirty
@@ -251,15 +257,22 @@ class Rep(nCores: Int, nSets: Int, nWays: Int, nMshrs: Int, reqIdWidth: Int, tag
   io.invalidate.way := invalidateWay
   io.invalidate.index := invalidateIndex
 
+  // Forwarding signals to the previous stage
+  updateStageIndex := indexReg
+  updateStageTag := tagReg
+  updateStageValid := reqValidReg
+  updateStageIsHit := isHit._1
+  updateStageMshrIdx := Mux(evict, Mux(io.repPol.updateCoreReachedLimit, io.missCritInfo.wrPtr, io.missNonCritInfo.wrPtr), halfMissIdxReg)
+
   // ---------------- Stalls due to hazards ----------------
 
   // If the replacement way is dirty but the line is not valid---stall the pipeline
   val stallDueToDirtyInvalid = reqValidReg && (!isHit._1 && isRepDirty && !isRepLineValid)
   io.dirtyInvalidStall := stallDueToDirtyInvalid
 
   // If a single mshr register is full of commands then we stall the pipeline until the line is brought in
-  val cmdCapacityNonCrit = io.missNonCritInfo.fullCmds(halfMissIdxReg) && io.missNonCritInfo.validMSHRs(halfMissIdxReg) && isHalfMissReg && !isHit._1
-  val cmdCapacityCrit = io.missCritInfo.fullCmds(halfMissIdxReg) && io.missCritInfo.validMSHRs(halfMissIdxReg) && isHalfMissReg && !isHit._1
+  val cmdCapacityNonCrit = io.missNonCritInfo.fullCmds(halfMissIdxReg) && io.missNonCritInfo.validMSHRs(halfMissIdxReg) && isHalfMissInUpdateStage && !isHit._1
+  val cmdCapacityCrit = io.missCritInfo.fullCmds(halfMissIdxReg) && io.missCritInfo.validMSHRs(halfMissIdxReg) && isHalfMissInUpdateStage && !isHit._1
   val halfMissCapacity = Mux(halfMissInCritReg, cmdCapacityCrit, cmdCapacityNonCrit)
   io.halfMissCapacity := halfMissCapacity
 }

src/main/scala/caches/hardware/reppol/TimeoutReplacementPolicy.scala

@@ -117,7 +117,7 @@ class TimeoutReplacementPolicy(nWays: Int, nSets: Int, nCores: Int, basePolicy:
   timeoutAlgo.io.decIdxTimers := timerMemory.io.rTimers1
   timeoutAlgo.io.updateIdxTimers := timerMemory.io.rTimers2
   decIdx := timeoutAlgo.io.decIdx
-  timerMemWrEn := true.B // TODO: ???
+  timerMemWrEn := true.B // TODO: Should write enable always be high since we are always decrementing something ???
   timerMemWrData := timeoutAlgo.io.wTimers
   timerMemWrIdx := timeoutAlgo.io.wIdx
 

src/test/scala/caches/hardware/pipelined/OcpCacheWrapperTest.scala

@@ -44,7 +44,7 @@ class OcpCacheWrapperTest extends AnyFlatSpec with ChiselScalatestTester {
       memDataWidth = memDataWidth,
       memBurstLen = memBurstLen,
       l2Cache = l2CacheGen
-    )).withAnnotations(Seq(WriteVcdAnnotation, VerilatorBackendAnnotation)) { dut =>
+    )).withAnnotations(Seq(WriteFstAnnotation, VerilatorBackendAnnotation)) { dut =>
       // Default assignments
       for (i <- 0 until nCores) {
         dut.io.cores(i).M.Cmd.poke(OcpCmd.IDLE)

src/test/scala/caches/hardware/pipelined/cache/SharedPipelinedCacheBitPlruTest.scala

@@ -8,7 +8,7 @@ class SharedPipelinedCacheBitPlruTest extends AnyFlatSpec with ChiselScalatestTe
   "SharedPipelinedCache" should "process pipelined requests for 8 ways, 128 sets, with bit plru policy" in {
     val cache = generateDut(CacheConfigs.config64BitPlru)
 
-    test(cache._1.apply()).withAnnotations(Seq(WriteVcdAnnotation, VerilatorBackendAnnotation)) { dut =>
+    test(cache._1.apply()).withAnnotations(Seq(WriteFstAnnotation, VerilatorBackendAnnotation)) { dut =>
       defaultAssignments(dut, cache._2)
 
       performTestActions(
@@ -29,7 +29,7 @@ class SharedPipelinedCacheBitPlruTest extends AnyFlatSpec with ChiselScalatestTe
   "SharedPipelinedCache" should "work with mshr entries that are full of cmds" in {
     val cache = generateDut(CacheConfigs.config64BitPlru)
 
-    test(cache._1.apply()).withAnnotations(Seq(WriteVcdAnnotation, VerilatorBackendAnnotation)) { dut =>
+    test(cache._1.apply()).withAnnotations(Seq(WriteFstAnnotation, VerilatorBackendAnnotation)) { dut =>
       defaultAssignments(dut, cache._2)
 
       // Issue the first set of requests

src/test/scala/caches/hardware/pipelined/cache/SharedPipelinedCacheContWithAllEvents.scala

@@ -8,7 +8,7 @@ class SharedPipelinedCacheContWithAllEvents extends AnyFlatSpec with ChiselScala
   "SharedPipelinedCache" should "work with all contention events" in {
     val cache = generateDut(CacheConfigs.config64ContMimPrecWb)
 
-    test(cache._1.apply()).withAnnotations(Seq(WriteVcdAnnotation, VerilatorBackendAnnotation)) { dut =>
+    test(cache._1.apply()).withAnnotations(Seq(WriteFstAnnotation, VerilatorBackendAnnotation)) { dut =>
       defaultAssignments(dut, cache._2)
 
       // Issue the first set of requests
@@ -19,7 +19,7 @@ class SharedPipelinedCacheContWithAllEvents extends AnyFlatSpec with ChiselScala
         cache._3,
         cache._4,
         cache._5,
-        600,
+        1000,
         printResults = PRINT_RESULTS
       )
 

src/test/scala/caches/hardware/pipelined/cache/SharedPipelinedCacheContentionTest.scala

@@ -8,7 +8,7 @@ class SharedPipelinedCacheContentionTest extends AnyFlatSpec with ChiselScalates
   "SharedPipelinedCache" should "process pipelined requests for 8 ways, 128 sets, with contention policy" in {
     val cache = generateDut(CacheConfigs.config64Cont)
 
-    test(cache._1.apply()).withAnnotations(Seq(WriteVcdAnnotation, VerilatorBackendAnnotation)) { dut =>
+    test(cache._1.apply()).withAnnotations(Seq(WriteFstAnnotation, VerilatorBackendAnnotation)) { dut =>
       defaultAssignments(dut, cache._2)
 
       // Issue the first set of requests

src/test/scala/caches/hardware/pipelined/cache/SharedPipelinedCacheStressTest.scala

@@ -8,7 +8,7 @@ class SharedPipelinedCacheStressTest extends AnyFlatSpec with ChiselScalatestTes
   "SharedPipelinedCache" should "handle stress test with bit plru policy" in {
     val cache = generateDut(CacheConfigs.config64BitPlru)
 
-    test(cache._1.apply()).withAnnotations(Seq(WriteVcdAnnotation, VerilatorBackendAnnotation)) { dut =>
+    test(cache._1.apply()).withAnnotations(Seq(WriteFstAnnotation, VerilatorBackendAnnotation)) { dut =>
       defaultAssignments(dut, cache._2)
 
       performTestActions(

src/test/scala/caches/hardware/pipelined/cache/SharedPipelinedCacheTest.scala

@@ -26,6 +26,8 @@ case class CacheRequest(
                          expectedData: Option[String] = None
                        ) extends TestAction
 
+// TODO: Should add an optional parameter that says that a response for a request should be received after a response to some other request has been received
+
 case class Stall(stallCycles: Int = 0) extends TestAction()
 
 case class ExpectFinishedRejectedResponse(coreId: Int, reqId: Int, expectedData: String) extends TestAction()
@@ -379,10 +381,13 @@ object Tests {
     CacheRequest(coreId = 3, reqId = 13, tag = 39, index = 74, blockOffset = 3, rw = false, expectedData = Some("b638aaa4ef343eee6a4757cb65a2f78c")), // MISS, way: 3, contention event, critical wb, reach contention limit for core 1
     CacheRequest(coreId = 1, reqId = 14, tag = 57, index = 74, blockOffset = 2, rw = false, expectedData = Some("26f4756810b9c7b7fc87a234ac62fee6")), // MISS, way: 2,
     CacheRequest(coreId = 2, reqId = 15, tag = 41, index = 74, blockOffset = 1, rw = false, expectedData = Some("8f2a3009871c1b8fb22ed80f63229d0f")), // MISS, way: 3,
-    CacheRequest(coreId = 0, reqId = 16, tag = 8, index = 74, blockOffset = 0, rw = false, expectedData = Some("e83fb23952953ff164bdb8d5685d2bd3"), rejected = true), // MISS, way: rejected
+    CacheRequest(coreId = 0, reqId = 16, tag = 41, index = 72, blockOffset = 1, rw = false, expectedData = Some("abbd90af6dbb29366ec5bd141df45023")), // MISS, way: 0,
+    CacheRequest(coreId = 1, reqId = 17, tag = 41, index = 72, blockOffset = 0, rw = false, expectedData = Some("a64a45812e63b4001eafac68edee5dd6")), // MISS, way: 1, not a half-miss since the core reached contention limit
+    CacheRequest(coreId = 2, reqId = 18, tag = 41, index = 72, blockOffset = 2, rw = false, expectedData = Some("b1a10cf29e0b684ae2dd8277b34d19f1")), // MISS, way: 2, not a half-miss since the core reached contention limit
+    CacheRequest(coreId = 0, reqId = 19, tag = 8, index = 74, blockOffset = 0, rw = false, expectedData = Some("e83fb23952953ff164bdb8d5685d2bd3"), rejected = true), // MISS, way: rejected
     Stall(300),
     PerformSchedulerOperation(2, false),
-    ExpectFinishedRejectedResponse(coreId = 0, reqId = 16, expectedData = "e83fb23952953ff164bdb8d5685d2bd3")
+    ExpectFinishedRejectedResponse(coreId = 0, reqId = 19, expectedData = "e83fb23952953ff164bdb8d5685d2bd3")
   )
 }
 

src/test/scala/caches/hardware/pipelined/cache/SharedPipelinedCacheTestMissQ.scala

@@ -8,7 +8,7 @@ class SharedPipelinedCacheTestMissQ extends AnyFlatSpec with ChiselScalatestTest
   "SharedPipelinedCache" should "work with miss-q and precedent events for 8 ways and 128 sets" in {
     val cache = generateDut(CacheConfigs.config64ContMimPrec)
 
-    test(cache._1.apply()).withAnnotations(Seq(WriteVcdAnnotation, VerilatorBackendAnnotation)) { dut =>
+    test(cache._1.apply()).withAnnotations(Seq(WriteFstAnnotation, VerilatorBackendAnnotation)) { dut =>
       defaultAssignments(dut, cache._2)
 
       // Issue the first set of requests

src/test/scala/caches/hardware/pipelined/cache/SharedPipelinedCacheTimeoutTest.scala

@@ -8,7 +8,7 @@ class SharedPipelinedCacheTimeoutTest extends AnyFlatSpec with ChiselScalatestTe
   "SharedPipelinedCache" should "process pipelined requests for 8 ways, 128 sets, with timeout policy" in {
     val cache = generateDut(CacheConfigs.config64TimeOut)
 
-    test(cache._1.apply()).withAnnotations(Seq(WriteVcdAnnotation, VerilatorBackendAnnotation)) { dut =>
+    test(cache._1.apply()).withAnnotations(Seq(WriteFstAnnotation, VerilatorBackendAnnotation)) { dut =>
       defaultAssignments(dut, cache._2)
 
       // Issue the first set of requests