Add additional pipeline stages

Author: ArijusGrotuzas

quartus/SharedPipelinedCacheSynthTop/SharedPipelinedCacheSynthTop.qsf

@@ -70,6 +70,5 @@ set_location_assignment PIN_Y2 -to clock
 set_location_assignment PIN_M23 -to reset
 
 
-set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
+set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

src/main/scala/caches/hardware/pipelined/MissFifo.scala

@@ -26,8 +26,8 @@ class MshrInfoIO(nCores: Int, nMshrs: Int, nWays: Int, indexWidth: Int, tagWidth
   val currentTags = Output(Vec(nMshrs, UInt(tagWidth.W)))
   val replacementWays = Output(Vec(nMshrs, UInt(log2Up(nWays).W)))
   val incidentCoreIds = Output(Vec(nMshrs, UInt(log2Up(nCores).W)))
-  val isCritCores = Output(Vec(nMshrs, Bool()))
-  val validMSHRs = Output(Vec(nMshrs, Bool()))
+  val critMshrs = Output(Vec(nMshrs, Bool()))
+  val validMshrs = Output(Vec(nMshrs, Bool()))
   val fullCmds = Output(Vec(nMshrs, Bool()))
   val wrPtr = Output(UInt(log2Ceil(nMshrs).W))
   val elementCnt = Output(UInt(log2Up(nMshrs + 1).W))
@@ -36,7 +36,6 @@ class MshrInfoIO(nCores: Int, nMshrs: Int, nWays: Int, indexWidth: Int, tagWidth
 class MshrPushIO(nCores: Int, nMshrs: Int, nWays: Int, reqIdWidth: Int, tagWidth: Int, indexWidth: Int, blockOffsetWidth: Int, subBlockWidth: Int) extends Bundle() {
   // For inserting a new MSHR entry
   val pushReq = Input(Bool())
-  val withCmd = Input(Bool()) // If true, the pushReqEntry will be pushed with a command
   val pushReqEntry = new LineRequestIO(nCores, nWays, tagWidth, indexWidth, subBlockWidth)
   // For pushing new command into MSHR entry
   val pushCmd = Input(Bool())
@@ -234,7 +233,6 @@ class CmdMshrQueue(nCmds: Int, nCores: Int, nMshrs: Int, reqIdWidth: Int, blockO
 
   val io = IO(new Bundle {
     val push = Input(Bool())
-    val withCmd = Input(Bool())
     val update = Input(Bool())
     val rdPtr = Input(UInt(log2Up(nMshrs).W))
     val wrPtr = Input(UInt(log2Up(nMshrs).W))
@@ -249,7 +247,7 @@ class CmdMshrQueue(nCmds: Int, nCores: Int, nMshrs: Int, reqIdWidth: Int, blockO
   val cntRegs = RegInit(VecInit(Seq.fill(nMshrs)(0.U((log2Up(nCmds) + 1).W))))
 
   when(io.push) {
-    cntRegs(io.wrPtr) := Mux(io.withCmd, 1.U, 0.U)
+    cntRegs(io.wrPtr) := 1.U
   }.elsewhen(io.update) {
     cntRegs(io.updtPtr) := cntRegs(io.updtPtr) + 1.U
   }
@@ -260,7 +258,7 @@ class CmdMshrQueue(nCmds: Int, nCores: Int, nMshrs: Int, reqIdWidth: Int, blockO
   cmdBlockQueue.io.update := io.update
   cmdBlockQueue.io.rdPtr := io.rdPtr
   cmdBlockQueue.io.wrPtr := io.wrPtr
-  cmdBlockQueue.io.wrData := Mux(io.withCmd, io.wrData, 0.U)
+  cmdBlockQueue.io.wrData := io.wrData
   cmdBlockQueue.io.updtPtr := io.updtPtr
   cmdBlockQueue.io.updtBlockIdx := cntRegs(io.updtPtr)
   cmdBlockQueue.io.updtData := io.updtData
@@ -295,7 +293,6 @@ class MshrQueue(nCores: Int, nCmds: Int, nMshrs: Int, nWays: Int, reqIdWidth: In
   reqQueue.io.pop := io.pop.pop
 
   cmdQueue.io.push := io.push.pushReq
-  cmdQueue.io.withCmd := io.push.withCmd
   cmdQueue.io.update := io.push.pushCmd
   cmdQueue.io.rdPtr := reqQueue.io.rdPtr
   cmdQueue.io.wrPtr := reqQueue.io.wrPtr
@@ -320,12 +317,12 @@ class MshrQueue(nCores: Int, nCmds: Int, nMshrs: Int, nWays: Int, reqIdWidth: In
   io.push.full := reqQueue.io.full
 
   io.info.wrPtr := reqQueue.io.wrPtr
-  io.info.validMSHRs := validMshrs
+  io.info.validMshrs := validMshrs
   io.info.currentTags := reqQueue.io.currentTags
   io.info.currentIndexes := reqQueue.io.currentIndexes
   io.info.replacementWays := reqQueue.io.replacementWays
   io.info.incidentCoreIds := reqQueue.io.incidentCoreIds
-  io.info.isCritCores := reqQueue.io.isCritCores
+  io.info.critMshrs := reqQueue.io.isCritCores
   io.info.fullCmds := cmdQueue.io.full
   io.info.elementCnt := queueElementCntReg
 
@@ -335,53 +332,67 @@ class MshrQueue(nCores: Int, nCmds: Int, nMshrs: Int, nWays: Int, reqIdWidth: In
   io.pop.cmds := cmdQueue.io.rdCmds
 }
 
-class MissFifo(nCores: Int, nCmds: Int, nMshrs: Int, nWays: Int, reqIdWidth: Int, tagWidth: Int, indexWidth: Int, blockOffsetWidth: Int, subBlockWidth: Int, blockWidth: Int) extends Module {
+class MissFifo(nCores: Int, nCmds: Int, nMshrs: Int, nWays: Int, reqIdWidth: Int, tagWidth: Int, indexWidth: Int, blockOffsetWidth: Int, subBlockWidth: Int, blockWidth: Int, enCritMisses: Boolean = false) extends Module {
   val io = IO(new MissFifoIO(nCores, nMshrs, nCmds, nWays, reqIdWidth, tagWidth, indexWidth, blockOffsetWidth, blockWidth, subBlockWidth))
 
-  val critQueue = Module(new MshrQueue(nCores, nCmds, nMshrs, nWays, reqIdWidth, tagWidth, indexWidth, blockOffsetWidth, subBlockWidth, blockWidth))
-  val nonCritQueue = Module(new MshrQueue(nCores, nCmds, nMshrs, nWays, reqIdWidth, tagWidth, indexWidth, blockOffsetWidth, subBlockWidth, blockWidth))
-
-  // De-multiplex the push interface to the two queues
-  val mshrPushDemux = Module(new MshrPushDemux(nCores, nCmds, nWays, reqIdWidth, tagWidth, indexWidth, blockOffsetWidth, blockWidth))
-
-  mshrPushDemux.io.sel := io.pushCrit
-  mshrPushDemux.io.in <> io.push
-  nonCritQueue.io.push <> mshrPushDemux.io.out1
-  critQueue.io.push <> mshrPushDemux.io.out2
-
-  // Multiplex between the two queues for popping
-  val mshrPopDemux = Module(new MshrPopMux(nCores, nCmds, nWays, reqIdWidth, tagWidth, indexWidth, blockOffsetWidth, blockWidth))
-
-  // Choose to always pop the critical queue as long as it is not empty
-  mshrPopDemux.io.sel := io.popQSel
-  mshrPopDemux.io.in1 <> nonCritQueue.io.pop
-  mshrPopDemux.io.in2 <> critQueue.io.pop
-  io.pop <> mshrPopDemux.io.out
-
-  io.critInfo <> critQueue.io.info
-  io.nonCritInfo <> nonCritQueue.io.info
-
-  // Since the critical queue is always given priority over non-critical queue, a hazards occurs when a replacement policy
-  // instructs a non-critical request to evict a way that then a critical request that has reached contention limit is
-  // told to evict too. For instance, a non-critical request can evict way 2, so it is pushed to non-critical fifo; then
-  // a critical request whose core has reached contention limit is told to evict the same way: 2 (most likely since any
-  // other ways are already owned by critical cores); then the critical way evicts this line first followed by a
-  // non-critical way evicting this line later on. This creates a additional contention, since if this line is later on
-  // needed by a critical core, it will have to refetch again, thus resulting in two line accesses from the main memory
-  // for a critical core.
-  // NOTE: This is a rather rare case.
-
-  val anyMatchingReqsInNonCrit = VecInit(Seq.fill(nMshrs)(false.B))
-  val critPopValid = !critQueue.io.pop.empty
-  for (mshrIdx <- 0 until nMshrs) {
-    val nonCritValid = nonCritQueue.io.info.validMSHRs(mshrIdx)
-    val conflict = critPopValid && nonCritValid && nonCritQueue.io.info.currentIndexes(mshrIdx) === critQueue.io.pop.popEntry.index && nonCritQueue.io.info.replacementWays(mshrIdx) === critQueue.io.pop.popEntry.replaceWay
-    anyMatchingReqsInNonCrit(mshrIdx) := conflict
-  }
+  if (enCritMisses) {
+    val critQueue = Module(new MshrQueue(nCores, nCmds, nMshrs, nWays, reqIdWidth, tagWidth, indexWidth, blockOffsetWidth, subBlockWidth, blockWidth))
+    val nonCritQueue = Module(new MshrQueue(nCores, nCmds, nMshrs, nWays, reqIdWidth, tagWidth, indexWidth, blockOffsetWidth, subBlockWidth, blockWidth))
+
+    // De-multiplex the push interface to the two queues
+    val mshrPushDemux = Module(new MshrPushDemux(nCores, nCmds, nWays, reqIdWidth, tagWidth, indexWidth, blockOffsetWidth, blockWidth))
+
+    mshrPushDemux.io.sel := io.pushCrit
+    mshrPushDemux.io.in <> io.push
+    nonCritQueue.io.push <> mshrPushDemux.io.out1
+    critQueue.io.push <> mshrPushDemux.io.out2
+
+    // Multiplex between the two queues for popping
+    val mshrPopDemux = Module(new MshrPopMux(nCores, nCmds, nWays, reqIdWidth, tagWidth, indexWidth, blockOffsetWidth, blockWidth))
+
+    // Choose to always pop the critical queue as long as it is not empty
+    mshrPopDemux.io.sel := io.popQSel
+    mshrPopDemux.io.in1 <> nonCritQueue.io.pop
+    mshrPopDemux.io.in2 <> critQueue.io.pop
+    io.pop <> mshrPopDemux.io.out
+
+    io.critInfo <> critQueue.io.info
+    io.nonCritInfo <> nonCritQueue.io.info
+
+    // Since the critical queue is always given priority over non-critical queue, a hazards occurs when a replacement policy
+    // instructs a non-critical request to evict a way that then a critical request that has reached contention limit is
+    // told to evict too. For instance, a non-critical request can evict way 2, so it is pushed to non-critical fifo; then
+    // a critical request whose core has reached contention limit is told to evict the same way: 2 (most likely since any
+    // other ways are already owned by critical cores); then the critical way evicts this line first followed by a
+    // non-critical way evicting this line later on. This creates a additional contention, since if this line is later on
+    // needed by a critical core, it will have to refetch again, thus resulting in two line accesses from the main memory
+    // for a critical core.
+    // NOTE: This is a rather rare case.
+
+    val anyMatchingReqsInNonCrit = VecInit(Seq.fill(nMshrs)(false.B))
+    val critPopValid = !critQueue.io.pop.empty
+    for (mshrIdx <- 0 until nMshrs) {
+      val nonCritValid = nonCritQueue.io.info.validMshrs(mshrIdx)
+      val conflict = critPopValid && nonCritValid && nonCritQueue.io.info.currentIndexes(mshrIdx) === critQueue.io.pop.popEntry.index && nonCritQueue.io.info.replacementWays(mshrIdx) === critQueue.io.pop.popEntry.replaceWay
+      anyMatchingReqsInNonCrit(mshrIdx) := conflict
+    }
+
+    val queueConflict = anyMatchingReqsInNonCrit.reduce((x, y) => x || y)
 
-  val queueConflict = anyMatchingReqsInNonCrit.reduce((x, y) => x || y)
+    io.full := critQueue.io.push.full || nonCritQueue.io.push.full
+    io.critEmpty := critQueue.io.pop.empty || queueConflict
+    io.nonCritEmpty := nonCritQueue.io.pop.empty
+  } else {
+    val nonCritQueue = Module(new MshrQueue(nCores, nCmds, nMshrs, nWays, reqIdWidth, tagWidth, indexWidth, blockOffsetWidth, subBlockWidth, blockWidth))
 
-  io.full := critQueue.io.push.full || nonCritQueue.io.push.full
-  io.critEmpty := critQueue.io.pop.empty || queueConflict
-  io.nonCritEmpty := nonCritQueue.io.pop.empty
+    nonCritQueue.io.push <> io.push
+    io.pop <> nonCritQueue.io.pop
+
+    io.critInfo <> 0.U.asTypeOf(io.critInfo)
+    io.nonCritInfo <> nonCritQueue.io.info
+
+    io.full := nonCritQueue.io.push.full
+    io.critEmpty := true.B
+    io.nonCritEmpty := nonCritQueue.io.pop.empty
+  }
 }

src/main/scala/caches/hardware/pipelined/SharedPipelinedCache.scala

@@ -62,21 +62,21 @@ class SharedPipelinedCache(
     case None => nWays
   }
 
-  val missQueue = Module(new MissFifo(nCores, halfMissCmdCnt, mshrCnt, nWays, reqIdWidth, tagWidth, indexWidth, blockOffsetWidth, bytesPerSubBlock * 8, bytesPerBlock * 8))
-  val wbQueue = Module(new WriteBackFifo(mshrCnt, tagWidth, indexWidth, bytesPerBlock * 8))
-  val updateLogic = Module(new UpdateUnit(nCores, nWays, reqIdWidth, tagWidth, indexWidth, bytesPerBlock * 8, bytesPerSubBlock * 8))
   val repPol = Module(l2RepPolicy())
+  val missQueue = Module(new MissFifo(nCores, halfMissCmdCnt, mshrCnt, nWays, reqIdWidth, tagWidth, indexWidth, blockOffsetWidth, bytesPerSubBlock * 8, bytesPerBlock * 8, enCritMisses = repPol.includeCriticalMissQ()))
+  val wbQueue = Module(new WriteBackFifo(mshrCnt, tagWidth, indexWidth, bytesPerBlock * 8, enCritWb = repPol.includeCriticalWbQ()))
+  val updateLogic = Module(new UpdateUnit(nCores, nWays, reqIdWidth, tagWidth, indexWidth, bytesPerBlock * 8, bytesPerSubBlock * 8))
 
   val schedulerDataWidth = repPol.getSchedulerDataWidth
   val l2CacheBytesPerSubBlock = bytesPerSubBlock
 
   val invalidateLine = WireDefault(false.B)
+  val insertBubble = WireDefault(false.B)
   val invalidateWay = WireDefault(0.U(log2Up(nWays).W))
   val invalidateIndex = WireDefault(0.U(indexWidth.W))
   val missFifoCmdCapacity = WireDefault(false.B)
   val repDirtyInvalidStall = WireDefault(false.B)
   val writeMissHazard = WireDefault(false.B)
-  val memIntPopWb = WireDefault(false.B)
 
   println(
     s"L2 Cache Configuration: " +
@@ -106,7 +106,7 @@ class SharedPipelinedCache(
   val coreReqArbiter = Module(new CoreReqArbiter(nCores = nCores, addrWidth = addressWidth, dataWidth = bytesPerSubBlock * 8, reqIdWidth = reqIdWidth))
 
   val pipeStall = updateLogic.io.stall || missQueue.io.full || missFifoCmdCapacity || repDirtyInvalidStall || writeMissHazard
-  val reqAccept = !pipeStall
+  val reqAccept = !pipeStall && !insertBubble
 
   // Connect core request and rejection queue to the core request multiplexer that feeds into the cache pipeline
   coreReqArbiter.io.req1 <> io.core.req
@@ -117,10 +117,11 @@ class SharedPipelinedCache(
 
   // Connect replacement policy with the rejection queue
   repPol.io.scheduler <> io.scheduler
+  insertBubble := repPol.io.control.insertBubble
 
   // ---------------- Decode ----------------
   val decLogic = Module(new Dec(nCores = nCores, nWays = nWays, reqIdWidth = reqIdWidth, tagWidth = tagWidth, indexWidth = indexWidth, blockOffWidth = blockOffsetWidth, byteOffWidth = byteOffsetWidth, subBlockWidth = bytesPerSubBlock * 8))
-  decLogic.io.stall := pipeStall
+  decLogic.io.stall := pipeStall || insertBubble
   decLogic.io.dec.coreId := coreReqArbiter.io.outCoreID
   decLogic.io.dec.reqValid := coreReqArbiter.io.out.reqId.valid
   decLogic.io.dec.reqId := coreReqArbiter.io.out.reqId.bits
@@ -130,9 +131,8 @@ class SharedPipelinedCache(
   decLogic.io.dec.byteEn := coreReqArbiter.io.out.byteEn
 
   // ---------------- Tag and Dirty Lookup ----------------
-
   val tagLogic = Module(new Tag(nCores = nCores, nSets = nSets, nWays = nWays, reqIdWidth = reqIdWidth, tagWidth = tagWidth, indexWidth = indexWidth, blockOffWidth = blockOffsetWidth, subBlockWidth = bytesPerSubBlock * 8))
-  tagLogic.io.stall := pipeStall
+  tagLogic.io.stall := pipeStall || insertBubble
   tagLogic.io.tag <> decLogic.io.tag
   tagLogic.io.tagCtrl <> updateLogic.io.tagUpdate
   tagLogic.io.invalidate.invalidate := invalidateLine
@@ -141,8 +141,7 @@ class SharedPipelinedCache(
   tagLogic.io.setLineValid := updateLogic.io.setValidLine
 
   // ---------------- Replacement ----------------
-
-  val repLogic = Module(new Rep(nCores = nCores, nSets = nSets, nWays = nWays, nMshrs = mshrCnt, reqIdWidth = reqIdWidth, tagWidth = tagWidth, indexWidth = indexWidth, blockWidth = bytesPerBlock * 8, subBlockWidth = bytesPerSubBlock * 8))
+  val repLogic = Module(new Rep(nCores = nCores, nSets = nSets, nWays = nWays, nMshrs = mshrCnt, reqIdWidth = reqIdWidth, tagWidth = tagWidth, indexWidth = indexWidth, blockWidth = bytesPerBlock * 8, subBlockWidth = bytesPerSubBlock * 8, useInvalidate = !repPol.isInstanceOf[ContentionReplacementPolicy]))
   repLogic.io.stall := pipeStall
   repLogic.io.rep <> tagLogic.io.rep
   repLogic.io.missFifoPush <> missQueue.io.push
@@ -151,20 +150,17 @@ class SharedPipelinedCache(
   repLogic.io.repPolCtrl <> repPol.io.control
   repLogic.io.repPolInfo <> repPol.io.info
   repLogic.io.setLineValid := updateLogic.io.setValidLine
-  repLogic.io.nonCritWbPop := memIntPopWb
-  repLogic.io.nonCritWbEntryIsCrit := wbQueue.io.isFirstInQCrit
   invalidateLine := repLogic.io.invalidate.invalidate
   invalidateWay := repLogic.io.invalidate.way
   invalidateIndex := repLogic.io.invalidate.index
   missQueue.io.pushCrit := repLogic.io.isMissPushCrit
   missFifoCmdCapacity := repLogic.io.halfMissCapacity
-  repDirtyInvalidStall := repLogic.io.dirtyInvalidStall
+  repDirtyInvalidStall := repLogic.io.evictionLineBusy
   rejectionQueue.io.push := repLogic.io.pushReject
   rejectionQueue.io.pushEntry := repLogic.io.pushRejectEntry
-  writeMissHazard := repLogic.io.writeMissHazard
+  repLogic.io.wbInfo <> wbQueue.io.wbInfo
 
   // ---------------- Read ----------------
-
   val readLogic = Module(new Read(memSizeInBytes = sizeInBytes, nCores = nCores, nWays = nWays, reqIdWidth = reqIdWidth, tagWidth = tagWidth, indexWidth = indexWidth, blockOffWidth = blockOffsetWidth, blockWidth = bytesPerBlock * 8, subBlockWidth = bytesPerSubBlock * 8))
   readLogic.io.stall := pipeStall
   readLogic.io.read <> repLogic.io.read
@@ -175,7 +171,6 @@ class SharedPipelinedCache(
   wbQueue.io.pushCrit := readLogic.io.wbQueuePushCrit
 
   // ---------------- Update ----------------
-
   val memInterface = Module(new MemoryInterface(nCores, nWays, halfMissCmdCnt, reqIdWidth, tagWidth, indexWidth, blockOffsetWidth, bytesPerBlock * 8, bytesPerSubBlock * 8, beatSize = memBeatSize, burstLen = memBurstLen))
   memInterface.io.missFifo <> missQueue.io.pop
   memInterface.io.missCritEmpty := missQueue.io.critEmpty
@@ -184,7 +179,6 @@ class SharedPipelinedCache(
   memInterface.io.wbCritEmpty := wbQueue.io.critEmpty
   memInterface.io.wbNonCritEmpty := wbQueue.io.nonCritEmpty
   memInterface.io.memController <> io.mem
-  memIntPopWb := memInterface.io.wbFifo.pop
   missQueue.io.popQSel := memInterface.io.popQSel
   wbQueue.io.popQSel := memInterface.io.popQSel