Define OCP interfaces locally

Author: ArijusGrotuzas

quartus/SharedPipelinedCacheDe2115Top/.gitignore

@@ -5,10 +5,9 @@
 # a cloned repository to be used (usually) immediately without regenerating
 # Altera IP blocks.
 
-# Need to keep all HDL files and timing constraint files
-# *.vhd
-# *.v
-# *.sdc
+# Ignore HDL files since these are always generated by chisel
+*.vhd
+*.v
 
 # ignore Quartus II generated folders
 *_sim

quartus/SharedPipelinedCacheSynthTop/.gitignore

@@ -5,10 +5,9 @@
 # a cloned repository to be used (usually) immediately without regenerating
 # Altera IP blocks.
 
-# Need to keep all HDL files and timing constraint files
-# *.vhd
-# *.v
-# *.sdc
+# Ignore HDL files since these are always generated by chisel
+*.vhd
+*.v
 
 # ignore Quartus II generated folders
 *_sim

src/main/scala/caches/hardware/ocp/Ocp.scala

@@ -0,0 +1,31 @@
+package caches.hardware.ocp
+
+import chisel3._
+
+// Constants for MCmd
+object OcpCmd {
+  val IDLE = "b000".U(3.W)
+  val WR = "b001".U(3.W)
+  val RD = "b010".U(3.W)
+}
+
+// Constants for SResp
+object OcpResp {
+  val NULL = "b00".U(2.W)
+  val DVA = "b01".U(2.W)
+  val FAIL = "b10".U(2.W)
+  val ERR = "b11".U(2.W)
+}
+
+// Signals generated by master
+class OcpMasterSignals(val addrWidth: Int, val dataWidth: Int) extends Bundle() {
+  val Cmd = Output(UInt(3.W))
+  val Addr = Output(UInt(addrWidth.W))
+  val Data = Output(UInt(dataWidth.W))
+}
+
+// Signals generated by slave
+class OcpSlaveSignals(val dataWidth: Int) extends Bundle() {
+  val Resp = Input(UInt(2.W))
+  val Data = Input(UInt(dataWidth.W))
+}

src/main/scala/caches/hardware/ocp/OcpBurst.scala

@@ -0,0 +1,39 @@
+package caches.hardware.ocp
+
+import chisel3._
+
+// Burst masters provide handshake signals
+class OcpBurstMasterSignals(addrWidth: Int, dataWidth: Int)
+  extends OcpMasterSignals(addrWidth, dataWidth) {
+  val DataValid = Output(UInt(1.W))
+  val DataByteEn = Output(UInt((dataWidth / 8).W))
+
+  // This does not really clone, but Data.clone doesn't either
+  override def clone() = {
+    val res = new OcpBurstMasterSignals(addrWidth, dataWidth)
+    res.asInstanceOf[this.type]
+  }
+}
+
+// Burst slaves provide handshake signal
+class OcpBurstSlaveSignals(dataWidth: Int)
+  extends OcpSlaveSignals(dataWidth) {
+  val CmdAccept = Input(UInt(1.W))
+  val DataAccept = Input(UInt(1.W))
+}
+
+// Master port
+class OcpBurstMasterPort(addrWidth: Int, dataWidth: Int, burstLen: Int) extends Bundle() {
+  val burstLength = burstLen
+  // Clk is implicit in Chisel
+  val M = Output(new OcpBurstMasterSignals(addrWidth, dataWidth))
+  val S = Input(new OcpBurstSlaveSignals(dataWidth))
+}
+
+// Slave port is reverse of master port
+class OcpBurstSlavePort(val addrWidth: Int, val dataWidth: Int, val burstLen: Int) extends Bundle() {
+  val burstLength = burstLen
+  // Clk is implicit in Chisel
+  val M = Input(new OcpBurstMasterSignals(addrWidth, dataWidth))
+  val S = Output(new OcpBurstSlaveSignals(dataWidth))
+}

src/main/scala/caches/hardware/ocp/OcpCore.scala

@@ -0,0 +1,16 @@
+package caches.hardware.ocp
+
+import chisel3._
+
+// Masters include a byte-enable signal
+class OcpCoreMasterSignals(override val addrWidth: Int, override val dataWidth: Int)
+  extends OcpMasterSignals(addrWidth, dataWidth) {
+  val ByteEn = UInt((dataWidth / 8).W)
+}
+
+// Slave port is reverse of master port
+class OcpCoreSlavePort(val addrWidth: Int, val dataWidth: Int) extends Bundle() {
+  val M = Input(new OcpCoreMasterSignals(addrWidth, dataWidth))
+  val S = Output(new OcpSlaveSignals(dataWidth))
+}
+

src/main/scala/caches/hardware/pipelined/CacheMemToOcpBurstMasterAdapter.scala

@@ -1,6 +1,6 @@
 package caches.hardware.pipelined
 
-import ocp._
+import caches.hardware.ocp._
 import chisel3._
 import chisel3.util._
 
@@ -22,7 +22,7 @@ class CacheMemToOcpBurstMasterAdapter(addrWidth: Int, dataWidth: Int, burstLen:
   val wBurstCountReg = RegInit(0.U(log2Up(burstLen).W))
   val wAddrDelayReg = RegInit(0.U(addrWidth.W))
 
-  val mCmd = WireDefault(ocp.OcpCmd.IDLE)
+  val mCmd = WireDefault(OcpCmd.IDLE)
   val mAddr = WireDefault(0.U(addrWidth.W))
   val mDataByteEn = WireDefault(0.U((dataWidth / 8).W))
   val rAddrReady = WireDefault(false.B)
@@ -33,14 +33,14 @@ class CacheMemToOcpBurstMasterAdapter(addrWidth: Int, dataWidth: Int, burstLen:
     is(sIdle) {
 
       when(io.cache.rChannel.rAddr.valid) {
-        mCmd := ocp.OcpCmd.RD
+        mCmd := OcpCmd.RD
         mAddr := io.cache.rChannel.rAddr.bits
 
         when(io.ocpBurst.S.CmdAccept.asBool) {
           rAddrReady := true.B
           stateReg := sReadBurst
         }
-      } .elsewhen (io.cache.wChannel.wAddr.valid) {
+      }.elsewhen(io.cache.wChannel.wAddr.valid) {
         wAddrReady := true.B // Need to force the memory interface to enter a state where it provides valid data
         wAddrDelayReg := io.cache.wChannel.wAddr.bits
 
@@ -50,7 +50,7 @@ class CacheMemToOcpBurstMasterAdapter(addrWidth: Int, dataWidth: Int, burstLen:
 
     is(sReadBurst) {
       val nextBurstCount = WireDefault(0.U(log2Up(burstLen).W))
-      nextBurstCount := Mux(io.ocpBurst.S.Resp === ocp.OcpResp.DVA, rBurstCountReg + 1.U, rBurstCountReg)
+      nextBurstCount := Mux(io.ocpBurst.S.Resp === OcpResp.DVA, rBurstCountReg + 1.U, rBurstCountReg)
 
       when(rBurstCountReg === (burstLen - 1).U) {
         rLast := true.B
@@ -62,7 +62,7 @@ class CacheMemToOcpBurstMasterAdapter(addrWidth: Int, dataWidth: Int, burstLen:
     }
 
     is(sWriteDelay) {
-      mCmd := ocp.OcpCmd.WR
+      mCmd := OcpCmd.WR
       mAddr := wAddrDelayReg
       mDataByteEn := (math.pow(2, dataWidth / 8) - 1).toInt.U
 
@@ -86,7 +86,7 @@ class CacheMemToOcpBurstMasterAdapter(addrWidth: Int, dataWidth: Int, burstLen:
     }
 
     is(sWriteAccept) {
-      when(io.ocpBurst.S.Resp === ocp.OcpResp.DVA) {
+      when(io.ocpBurst.S.Resp === OcpResp.DVA) {
         stateReg := sIdle
       }
     }
@@ -99,7 +99,7 @@ class CacheMemToOcpBurstMasterAdapter(addrWidth: Int, dataWidth: Int, burstLen:
   io.ocpBurst.M.DataValid := io.cache.wChannel.wData.valid
 
   io.cache.rChannel.rAddr.ready := rAddrReady
-  io.cache.rChannel.rData.valid := io.ocpBurst.S.Resp === ocp.OcpResp.DVA
+  io.cache.rChannel.rData.valid := io.ocpBurst.S.Resp === OcpResp.DVA
   io.cache.rChannel.rData.bits := io.ocpBurst.S.Data
   io.cache.rChannel.rLast := rLast
 

src/main/scala/caches/hardware/pipelined/OcpBurstSlaveToCacheRequestAdapter.scala

@@ -1,11 +1,11 @@
 package caches.hardware.pipelined
 
-import ocp._
+import caches.hardware.ocp._
 import chisel3._
 import chisel3.util._
 
 class OcpBurstSlaveToCacheRequestAdapter(addrWidth: Int, dataWidth: Int, burstLen: Int) extends Module {
-  val io = IO(new Bundle{
+  val io = IO(new Bundle {
     val ocpBurst = new OcpBurstSlavePort(addrWidth, dataWidth, burstLen)
     val corePort = Flipped(new CacheCorePortIO(addrWidth, dataWidth * burstLen, reqIdWidth = 1))
   })
@@ -22,7 +22,7 @@ class OcpBurstSlaveToCacheRequestAdapter(addrWidth: Int, dataWidth: Int, burstLe
   val dateByteEnRegs = RegInit(VecInit(Seq.fill(burstLen)(0.U((dataWidth / 8).W))))
 
   // Default signal assignments
-  val ocpSResp = WireDefault(ocp.OcpResp.NULL)
+  val ocpSResp = WireDefault(OcpResp.NULL)
   val ocpSData = WireDefault(0.U(dataWidth.W))
   val ocpSCmdAccept = WireDefault(0.U(1.W))
   val ocpSDataAccept = WireDefault(0.U(1.W))
@@ -35,11 +35,11 @@ class OcpBurstSlaveToCacheRequestAdapter(addrWidth: Int, dataWidth: Int, burstLe
   switch(stateReg) {
     is(sIdle) {
 
-      when(io.ocpBurst.M.Cmd === ocp.OcpCmd.RD) {
+      when(io.ocpBurst.M.Cmd === OcpCmd.RD) {
         ocpSCmdAccept := 1.U
         addrReg := io.ocpBurst.M.Addr
         stateReg := sWaitReadAccept
-      } .elsewhen (io.ocpBurst.M.Cmd === ocp.OcpCmd.WR) {
+      }.elsewhen(io.ocpBurst.M.Cmd === OcpCmd.WR) {
         // Need to latch rest of the data over multiple cycles
         ocpSDataAccept := 1.U
         ocpSCmdAccept := 1.U
@@ -79,7 +79,7 @@ class OcpBurstSlaveToCacheRequestAdapter(addrWidth: Int, dataWidth: Int, burstLe
         nextDataCount := 0.U
       }
 
-      ocpSResp := ocp.OcpResp.DVA
+      ocpSResp := OcpResp.DVA
       ocpSData := dataRegs(dataCountReg)
       dataCountReg := nextDataCount
     }
@@ -113,9 +113,9 @@ class OcpBurstSlaveToCacheRequestAdapter(addrWidth: Int, dataWidth: Int, burstLe
       }
     }
 
-    is (sWaitWriteResp) {
+    is(sWaitWriteResp) {
       when(io.corePort.resp.reqId.valid) {
-        ocpSResp := ocp.OcpResp.DVA
+        ocpSResp := OcpResp.DVA
         stateReg := sIdle
       }
     }

src/main/scala/caches/hardware/pipelined/OcpCacheWrapper.scala

@@ -1,9 +1,8 @@
 package caches.hardware.pipelined
 
-import ocp._
+import caches.hardware.ocp._
 import chisel3._
 import chisel3.util._
-import caches.hardware.util.Constants.CONTENTION_LIMIT_WIDTH
 
 class OcpCacheWrapperPort(
                            nCores: Int,
@@ -20,14 +19,14 @@ class OcpCacheWrapperPort(
 }
 
 class OcpCacheWrapper(
-                                nCores: Int,
-                                addrWidth: Int,
-                                coreDataWidth: Int,
-                                coreBurstLen: Int,
-                                memDataWidth: Int,
-                                memBurstLen: Int,
-                                l2Cache: () => SharedPipelinedCache
-                              ) extends Module {
+                       nCores: Int,
+                       addrWidth: Int,
+                       coreDataWidth: Int,
+                       coreBurstLen: Int,
+                       memDataWidth: Int,
+                       memBurstLen: Int,
+                       l2Cache: () => SharedPipelinedCache
+                     ) extends Module {
 
   val cache = Module(l2Cache())
   val l2SchedulerDataWidth = cache.schedulerDataWidth

src/main/scala/caches/hardware/pipelined/OcpCoreSlaveToSchedulerAdapter.scala

@@ -1,9 +1,9 @@
 package caches.hardware.pipelined
 
-import caches.hardware.reppol.{SchedulerCmd, SchedulerControlIO}
+import caches.hardware.ocp._
+import caches.hardware.reppol._
 import chisel3._
 import chisel3.util._
-import ocp.OcpCoreSlavePort
 
 class OcpCoreSlaveToSchedulerAdapter(nCores: Int, dataWidth: Int) extends Module() {
   val io = IO(new Bundle {
@@ -15,22 +15,22 @@ class OcpCoreSlaveToSchedulerAdapter(nCores: Int, dataWidth: Int) extends Module
   val addr = RegNext(io.core.M.Addr, 0.U)
   val wData = RegNext(io.core.M.Data, 0.U)
 
-  val sResp = WireDefault(ocp.OcpResp.NULL)
+  val sResp = WireDefault(OcpResp.NULL)
   val sData = WireDefault(0.U(dataWidth.W))
 
-  when(cmd === ocp.OcpCmd.WR || cmd === ocp.OcpCmd.RD) {
-    sResp := ocp.OcpResp.DVA
+  when(cmd === OcpCmd.WR || cmd === OcpCmd.RD) {
+    sResp := OcpResp.DVA
   }
 
   val schCmd = WireDefault(SchedulerCmd.NULL)
   switch(cmd) {
-    is(ocp.OcpCmd.IDLE) {
+    is(OcpCmd.IDLE) {
       schCmd := SchedulerCmd.NULL
     }
-    is(ocp.OcpCmd.WR) {
+    is(OcpCmd.WR) {
       schCmd := SchedulerCmd.WR
     }
-    is(ocp.OcpCmd.RD) {
+    is(OcpCmd.RD) {
       schCmd := SchedulerCmd.RD
     }
   }