Cleanup hardware modules

Author: ArijusGrotuzas

src/main/scala/caches/hardware/pipelined/MemoryInterface.scala

@@ -99,8 +99,6 @@ class MemoryInterface(nCores: Int, nWays: Int, nHalfMissCmds: Int, reqIdWidth: I
   val missFifoPop = WireDefault(false.B)
   val updateLogicValid = WireDefault(false.B)
   val updateLogicValidCmd = WireDefault(false.B)
-  val cacheRData = WireDefault(0.U(blockWidth.W))
-  val cacheRespStatus = WireDefault(0.U(1.W))
 
   switch(stateReg) {
     is(sIdle) {

src/main/scala/caches/hardware/pipelined/RejectionQueue.scala

@@ -41,5 +41,5 @@ class RejectionQueue(nCores: Int, addrWidth: Int, dataWidth: Int, reqIdWidth: In
   io.popCoreId := popData(coreIdWidth - 1 + reqIdWidth + addrWidth + (dataWidth / 8) + dataWidth + 1, reqIdWidth + addrWidth + (dataWidth / 8) + dataWidth + 1)
 
   io.full := !rejectQueue.io.enq.ready
-  io.popEntry.reqId.valid := rejectQueue.io.deq.valid // && popCountReg =/= 0.U
+  io.popEntry.reqId.valid := rejectQueue.io.deq.valid
 }

src/main/scala/caches/hardware/pipelined/SharedPipelinedCacheTestTop.scala

@@ -3,6 +3,7 @@ package caches.hardware.pipelined
 import chisel3._
 import chisel3.util._
 import caches.hardware.reppol._
+import caches.hardware.util.DummyDRAM
 
 class SharedCachePort(nCores: Int, reqIdWidth: Int, addrWidth: Int, dataWidth: Int) extends Bundle {
   val cores = Vec(nCores, new CacheCorePortIO(addrWidth, dataWidth, reqIdWidth))
@@ -53,7 +54,7 @@ class SharedPipelinedCacheTestTop(
   })
 
   // The dummy memory is sub-block addressable
-  val memory = Module(new DummyMemory(addressWidth - log2Ceil(memBeatSize), bytesPerBlock * 8, memBeatSize, memBurstLen, dataFile))
+  val memory = Module(new DummyDRAM(addressWidth - log2Ceil(memBeatSize), bytesPerBlock * 8, memBeatSize, memBurstLen, dataFile))
 
   for (coreIdx <- 0 until nCores) {
     arbiter.io.ports(coreIdx).reqId <> io.requests.cores(coreIdx).req.reqId

src/main/scala/caches/hardware/reppol/ContentionReplacementPolicy.scala

@@ -3,7 +3,7 @@ package caches.hardware.reppol
 import chisel3._
 import chisel3.util._
 import caches.hardware.util.Constants.CONTENTION_LIMIT_WIDTH
-import caches.hardware.util.{MemBlock, PipelineReg, UpdateSingleVecElem}
+import caches.hardware.util.{MemBlock, PipelineReg}
 
 class LineAssignmentsArray(nWays: Int, nSets: Int, nCores: Int) extends Module() {
   val io = IO(new Bundle {
@@ -188,26 +188,4 @@ class ContentionReplacementPolicy(
   io.control.replacementSet := VecInit(Seq.fill(nWays)(0.U(log2Up(nWays).W)))
   io.control.updateCoreReachedLimit := coreTable.io.rCritCores(io.control.updateCoreId) && (coreTable.io.rLimits(io.control.updateCoreId) === 0.U)
   io.control.updateCoreIsCrit := coreTable.io.rCritCores(io.control.updateCoreId)
-}
-
-object ContentionReplacementPolicy extends App {
-  //  val l2Size = 262144 // 256 KiB
-  //  val l2Size = 16384 // 16 KiB
-  val l2Size = 131072 // 128 KiB
-  val l2Ways = 8
-  val nCores = 4
-  val l2BytesPerBlock = 64
-  val l2nSets = l2Size / (l2Ways * l2BytesPerBlock)
-
-  val plruL2RepPolicy = () => new BitPlruReplacementPolicy(l2Ways, l2nSets, nCores)
-
-  (new chisel3.stage.ChiselStage).emitVerilog(
-    new ContentionReplacementPolicy(
-      l2Ways,
-      l2nSets,
-      nCores,
-      plruL2RepPolicy
-    ),
-    Array("--target-dir", "generated")
-  )
 }

src/main/scala/caches/hardware/util/Constants.scala

@@ -1,8 +1,6 @@
 package caches.hardware.util
 
 object Constants {
-  val ADDRESS_WIDTH = 32
-
   val CONTENTION_LIMIT_WIDTH = 11 // If the maximum limit is 100k and assuming a single L2 cache miss latency is 60 cc, then we need only 11 bits to represent the maximum contention limit count
 
   val TIMEOUT_LIMIT_WIDTH = 16 // Assuming one sets timers are ticked down each cycle, and default size includes 512 sets, each timer is decremented every 512 cycles, giving a max timer at 500k using 10 bits

src/main/scala/caches/hardware/pipelined/DummyMemory.scala renamed to src/main/scala/caches/hardware/util/DummyDRAM.scala

@@ -1,10 +1,10 @@
-package caches.hardware.pipelined
+package caches.hardware.util
 
-import caches.hardware.util.MemBlock
+import caches.hardware.pipelined.CacheMemoryControllerIO
 import chisel3._
 import chisel3.util._
 
-class DummyMemory(addrWidth: Int, blockWidth: Int, beatSize: Int, burstLen: Int, dataFile: Option[String] = None) extends Module {
+class DummyDRAM(addrWidth: Int, blockWidth: Int, beatSize: Int, burstLen: Int, dataFile: Option[String] = None) extends Module {
   require((blockWidth * 8) > beatSize, "Block width must be greater than beat size.")
 
   val io = IO(Flipped(new CacheMemoryControllerIO(addrWidth, beatSize)))

src/main/scala/caches/hardware/util/MemBlock.scala

@@ -24,15 +24,6 @@ class TwoReadMemBlockIO(depth: Int, width: Int) extends Bundle {
   val readData2 = Output(UInt(width.W))
 }
 
-class MaskedMemBlockIO(depth: Int, width: Int, maskElemWidth: Int) extends Bundle {
-  val readAddr = Input(UInt(log2Up(depth).W))
-  val writeAddr = Input(UInt(log2Up(depth).W))
-  val writeData = Input(UInt(width.W))
-  val wrEn = Input(Bool())
-  val byteEn = Input(Vec(width / maskElemWidth, Bool()))
-  val readData = Output(UInt(width.W))
-}
-
 /**
  * General purpose synchronous memory block.
  *
@@ -86,63 +77,6 @@ class MemBlock(depth: Int, width: Int, forward: Boolean = true, stallReg: Boolea
   }
 }
 
-/**
- * General purpose synchronous memory block with mask.
- *
- * @param depth Number of memory entries
- * @param width Memory entry width in bits
- * @param maskElemWidth Width of bits that a single mask bool value covers in the input data
- * @param forward Whether to include forwarding registers or not
- * @param dataFile Hex datafile for initializing the memory block
- */
-class MaskedMemBlock(depth: Int, width: Int, maskElemWidth: Int, forward: Boolean = true, dataFile: Option[String] = None) extends Module {
-  val io = IO(new MaskedMemBlockIO(depth, width, maskElemWidth))
-
-  val mem = SyncReadMem(depth, Vec(width / maskElemWidth, UInt(maskElemWidth.W)), SyncReadMem.ReadFirst)
-
-  // Initialize memory block from a file
-  if (dataFile.isDefined) {
-    val file = dataFile.get
-
-    if (file.trim().nonEmpty) { // If not empty path
-      loadMemoryFromFileInline(mem, file)
-    } else {
-      println(s"Warning: The provided initialization file path is incorrect: $file")
-    }
-  }
-
-  val writeDataAsVec = UIntToVec(io.writeData, width, maskElemWidth)
-
-  // Write
-  when(io.wrEn) {
-    mem.write(io.writeAddr, writeDataAsVec, io.byteEn)
-  }
-
-  // Read
-  val readDataAsVec = mem.read(io.readAddr)
-
-  if (forward) {
-    val writeByteMaskReg = RegNext(io.byteEn)
-    val writeDataReg = RegNext(writeDataAsVec)
-    val forwardSelReg = RegNext((io.writeAddr === io.readAddr) && io.wrEn)
-
-    // If forwarding then we need to combine the old data with the write data using the byte mask
-    val forwardDataAsVec = VecInit(Seq.fill(width / 8)(0.U(8.W)))
-    for (i <- 0 until forwardDataAsVec.length) {
-      when(writeByteMaskReg(i)) {
-        forwardDataAsVec(i) := writeDataReg(i)
-      } .otherwise {
-        forwardDataAsVec(i) := readDataAsVec(i)
-      }
-    }
-
-    io.readData := Mux(forwardSelReg, writeDataAsVec.asUInt, readDataAsVec.asUInt)
-  } else {
-    // No forwarding, just output the read data
-    io.readData := readDataAsVec.asUInt
-  }
-}
-
 /**
  * General purpose synchronous memory block with two read ports.
  *