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1 parent 64e3d46 commit 04fd101Copy full SHA for 04fd101
src/main/scala/arbiter/ArbiterTree.scala
@@ -2,6 +2,7 @@ package arbiter
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import chisel3._
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import chisel3.util._
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+import chisel3.experimental.ChiselEnum
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// Only one will be ready, as we cannot take two values
src/main/scala/debug/UartDebug.scala
@@ -3,6 +3,7 @@ package debug
import chisel.lib.uart._
/**
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* Poor mans debugger, using a UART instead of JTAG.
src/main/scala/spi/SpiMaster.scala
@@ -2,6 +2,8 @@ package spi
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class SpiIO extends Bundle {
val ncs = Output(Bool())
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