soc: fix tests and PipeConRV

Author: schoeberl

README.md

@@ -204,7 +204,7 @@ To analyze memory issues (e.g., increase the heap size with Xmx) use a ```.sbtop
  * [ ] Get one-way memory back in here
  * [ ] AXI wrapper
 
-OCP Wrapper like this:
+OCP Wrapper like this (we have a different one, should check the difference)
 
 ```scala
 class S4nocOCPWrapper(nrCores: Int, txFifo: Int, rxFifo: Int) extends CmpDevice(nrCores) {

src/main/scala/s4noc/S4NoCTop.scala

@@ -13,13 +13,13 @@ import soc._
   */
 class S4NoCTop(conf: Config) extends Module  {
   val io = IO(new Bundle {
-    val cpuPorts = Vec(conf.n, new PipeConIO(conf.width))
+    val cpuPorts = Vec(conf.n, new PipeConIO(4)) // TODO: shall we use MultiCoreDevice here?
     val cycCnt = Output(UInt(32.W))
   })
 
   val s4noc = Module(new S4NoC(conf))
   for (i <- 0 until conf.n) {
-    val ci = Module(new PipeConS4NoC(conf.width, Entry(UInt(conf.width.W))))
+    val ci = Module(new PipeConS4NoC(4, Entry(UInt(conf.width.W))))
     s4noc.io.networkPort(i) <> ci.rv
     io.cpuPorts(i) <> ci.cpuPort
   }

src/main/scala/soc/PipeConRV.scala

@@ -72,8 +72,11 @@ class PipeConRV[T <: Data](private val addrWidth: Int, private val dt: T, s4noc:
           stateReg := writeWait
         }
          */
-        txDataReg := cpuPort.wrData
-        txS4NocReg.data := cpuPort.wrData
+        if (s4noc) {
+          txS4NocReg.data := cpuPort.wrData
+        } else {
+          txDataReg := cpuPort.wrData
+        }
         stateReg := writeWait
       }
     }

src/test/scala/soc/PipeConRVTest.scala

@@ -11,7 +11,7 @@ class PipeConRVTest() extends AnyFlatSpec with ChiselScalatestTester {
   behavior of "The CpuInterfaceRV"
 
   it should "do something" in {
-    test(new PipeConRV(4, UInt(32.W))) {
+    test(new PipeConRV(4, UInt(32.W))).withAnnotations(Seq(WriteVcdAnnotation)) {
       d => {
 
         def step() = d.clock.step()
@@ -25,6 +25,9 @@ class PipeConRVTest() extends AnyFlatSpec with ChiselScalatestTester {
         step()
         cp.ack.expect(false.B)
 
+        // useful default
+        cp.wrMask.poke(0xf.U)
+
         // two cycle write into tx register
         // TODO: should be a single cycle operation when the tx channel is ready
         cp.address.poke(4.U)
@@ -67,12 +70,13 @@ class PipeConRVTest() extends AnyFlatSpec with ChiselScalatestTester {
         assert(helper.read(0) == 2)
         tx.ready.poke(true.B)
         assert(helper.read(0) == 3)
+        step()
 
-        helper.write(0, 0xcafe)
+        helper.write(4, 0xcafe)
         tx.bits.expect(0xcafe)
 
         rx.bits.poke(123)
-        assert(helper.read(1) == 123)
+        assert(helper.read(4) == 123)
       }
     }
   }
@@ -92,11 +96,11 @@ class PipeConRVTest() extends AnyFlatSpec with ChiselScalatestTester {
       val helper = new MemoryMappedIOHelper(d.cpuPort, d.clock)
 
       // should get back the data at some time
-      helper.write(1, 0x1234)
+      helper.write(4, 0x1234)
       var ok = false
       for (i <- 0 until 10 if !ok) {
         if (helper.rxAvail) {
-          assert(helper.read(1) == 0x1234)
+          assert(helper.read(4) == 0x1234)
           ok = true
         }
       }
@@ -204,8 +208,8 @@ class PipeConRVTest() extends AnyFlatSpec with ChiselScalatestTester {
     cpif.rx <> fifo.io.deq
   }
 
-  it should "do work with a S4NOC Entry" in {
-    test(new MyModule3()).withAnnotations(Seq(WriteVcdAnnotation)) {
+  it should "work with a S4NOC Entry" in {
+    test(new MyModule3()) {
       d => {
         val helper = new MemoryMappedIOHelper(d.cpuPort, d.clock)