spi: more experiments

Author: schoeberl

7series.txt

@@ -18,5 +18,5 @@ puts [irscan xc7.tap 0x09]
 puts [drscan xc7.tap 32 0]  
 
 puts "Programming FPGA..."
-pld load 0 build/WildcatTop.bit
+pld load 0 build/BitBang.bit
 exit

Makefile

@@ -34,10 +34,17 @@ synth:
 
 cp-bit:
 	-mkdir build
-	scp [email protected]:~/source/wildcat/build/$(HW).bit build
+	scp [email protected]:~/t-crest/soc-comm/build/$(HW).bit build
 # Configure the Basys3 or NexysA7 board with open source tools
 config:
 	openocd -f 7series.txt
 
+# serial port on Mac
+listen:
+	ls /dev/tty.*
+	screen /dev/tty.usbserial-210292B408601 115200
+
+# stop with Ctrl+A and Ctrl+\
+
 clean:
 	git clean -fd

src/main/scala/spi/BitBang.scala

@@ -26,7 +26,7 @@ class BitBang(frequ: Int) extends Module {
   io.tx := tx.io.txd
   rx.io.rxd := io.rx
 
-  tx.io.channel.bits := '0'.U + io.sw
+  tx.io.channel.bits := '0'.U + io.miso
   tx.io.channel.valid := rx.io.channel.valid
   rx.io.channel.ready := true.B
   val regVal = RegEnable('0'.U + rx.io.channel.bits(3, 0), rx.io.channel.valid)

src/main/scala/spi/SpiMaster.scala

@@ -16,7 +16,7 @@ class SpiMaster extends Module {
   })
 
   object State extends ChiselEnum {
-    val idle, tx1, tx2, rx1, rx2 = Value
+    val start, idle, tx1, tx2, rx1, rx2 = Value
   }
   import State._
   val state = RegInit(idle)
@@ -25,34 +25,49 @@ class SpiMaster extends Module {
   val mosiReg = RegInit(0.U(8.W))
   val misoReg = RegInit(0.U(8.W))
   val bitsReg = RegInit(0.U(8.W))
-  val cntReg = RegInit(0.U(8.W))
+  val cntReg = RegInit(0.U(32.W))
+  val CNT_MAX = 9000.U
 
 
   spi.ncs := 1.U
   spi.sclk := x
   spi.mosi := mosiReg(7)
   io.dataOut := misoReg
 
-  val JTAG_ID = 0x9f.U
+  // val JTAG_ID = 0x90.U
+  val JTAG_ID = 0xab.U
+  val RD_STATUS = 0x05.U
   val RDSR = 0x05.U
   val READ = 0x03.U
 
   switch(state) {
+    is(start) {
+      spi.ncs := 1.U
+      spi.sclk := 0.U
+      cntReg := cntReg + 1.U
+      when(cntReg === CNT_MAX) {
+        state := idle
+        cntReg := 0.U
+      }
+    }
     is(idle) {
       spi.ncs := 1.U
       spi.sclk := 0.U
-      when(true.B) {
+      cntReg := cntReg + 1.U
+      when(cntReg === CNT_MAX) {
+        // when data is available
         state := tx1
         bitsReg := 7.U
         cntReg := 0.U
         mosiReg := JTAG_ID
       }
+
     }
     is(tx1) {
       spi.ncs := 0.U
       spi.sclk := 0.U
       cntReg := cntReg + 1.U
-      when(cntReg === 3.U) {
+      when(cntReg === CNT_MAX) {
         state := tx2
         cntReg := 0.U
       }
@@ -61,7 +76,7 @@ class SpiMaster extends Module {
       spi.ncs := 0.U
       spi.sclk := 1.U
       cntReg := cntReg + 1.U
-      when(cntReg === 3.U) {
+      when(cntReg === CNT_MAX) {
         state := tx1
         cntReg := 0.U
         mosiReg := mosiReg(6, 0) ## 0.U // io.dataIn(7))
@@ -75,7 +90,7 @@ class SpiMaster extends Module {
       spi.ncs := 0.U
       spi.sclk := 0.U
       cntReg := cntReg + 1.U
-      when(cntReg === 3.U) {
+      when(cntReg === CNT_MAX) {
         state := rx2
         cntReg := 0.U
         bitsReg := bitsReg - 1.U
@@ -88,7 +103,7 @@ class SpiMaster extends Module {
       spi.ncs := 0.U
       spi.sclk := 1.U
       cntReg := cntReg + 1.U
-      when(cntReg === 3.U) {
+      when(cntReg === CNT_MAX) {
         state := rx1
         cntReg := 0.U
         bitsReg := bitsReg - 1.U

src/test/scala/spi/TestSpiMaster.scala

@@ -74,15 +74,19 @@ class TopTest extends Module {
 }
 class TestSpiMaster extends AnyFlatSpec with ChiselScalatestTester {
 
+  /*
   "SpiMaster" should "work" in {
     test(new SpiMaster).withAnnotations(Seq(WriteVcdAnnotation)) { dut =>
       dut.clock.step(20)
     }
   }
 
+   */
+
   "TopTest" should "work" in {
     test(new TopTest).withAnnotations(Seq(WriteVcdAnnotation, IcarusBackendAnnotation)) { dut =>
-      dut.clock.step(400)
+      dut.clock.setTimeout(1500001)
+      dut.clock.step(1500000)
     }
   }
 }