Switch to Chisel 3.6 and Scala 2.13

Author: schoeberl

README.md

@@ -177,11 +177,13 @@ sbt "Test / run s4noc.PerformanceTest"
 
 #### TODO (S4NOC)
 
+ * NetworkTest and LatencyTest disabled, as they (now) run too long
  * Share testing code between ideal and concrete NIs
  * Play with configuration
  * Check memory FIFO if it is memory in an FPGA
  * Should also check how much HW the translation is, probably nothing. Max 4 LUTs for a table for 16 cores
  * Play with FIFO buffer variations
+ * Have Raw tester with Verilator annotation
 
 To analyze memory issues (e.g., increase the heap size with Xmx) use a ```.sbtopts``` with
 ```

build.sbt

@@ -1,4 +1,4 @@
-scalaVersion := "2.12.13"
+scalaVersion := "2.13.14"
 
 scalacOptions ++= Seq(
   "-deprecation",
@@ -7,19 +7,19 @@ scalacOptions ++= Seq(
   "-language:reflectiveCalls",
 )
 
-val chiselVersion = "3.5.5"
+val chiselVersion = "3.6.1"
 addCompilerPlugin("edu.berkeley.cs" %% "chisel3-plugin" % chiselVersion cross CrossVersion.full)
 libraryDependencies += "edu.berkeley.cs" %% "chisel3" % chiselVersion
-libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.5.5"
+libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.6.2"
 
 // For FIFO buffers
-libraryDependencies += "edu.berkeley.cs" % "ip-contributions" % "0.5.1"
+libraryDependencies += "edu.berkeley.cs" % "ip-contributions" % "0.6.1"
 
 // library name
 name := "soc-comm"
 
 // library version
-version := "0.1.5"
+version := "0.1.6"
 
 // groupId, SCM, license information
 organization := "io.github.t-crest"

src/main/scala/arbiter/ArbiterTree.scala

@@ -1,8 +1,6 @@
 package arbiter
 
 import chisel3._
-// TODO: which Chisel version moves this into chisel3.util._?
-import chisel3.experimental.ChiselEnum
 import chisel3.util._
 
 

src/main/scala/noc/Butterfly.scala

@@ -82,5 +82,5 @@ class Butterfly extends Module {
 }
 
 object Butterfly extends App {
-  (new chisel3.stage.ChiselStage).emitVerilog(new Butterfly(), Array("--target-dir", "generated"))
+  emitVerilog(new Butterfly(), Array("--target-dir", "generated"))
 }

src/main/scala/s4noc/S4Router.scala

@@ -45,5 +45,5 @@ class S4Router[T <: Data](schedule: Array[Array[Int]], dt: T) extends Module {
 }
 
 object S4Router extends App {
-  (new chisel3.stage.ChiselStage).emitVerilog(new S4Router(Schedule.genRandomSchedule(7), UInt(32.W)), Array("--target-dir", "generated"))
+  emitVerilog(new S4Router(Schedule.genRandomSchedule(7), UInt(32.W)), Array("--target-dir", "generated"))
 }

src/main/scala/s4noc/Schedule.scala

@@ -103,7 +103,7 @@ class Schedule(val n: Int) {
     schedule.foreach(a => {
       s += "( "
       a.foreach(v => {
-        s += v + " "
+        s += s"$v "
       })
       s += ")\n"
     })

src/main/scala/s4noc/ScheduleHardware.scala

@@ -37,5 +37,5 @@ class ScheduleHardware[T <: Data](schedule: Array[Array[Int]], dt: T) extends Mo
 }
 
 object ScheduleHardware extends App {
-  (new chisel3.stage.ChiselStage).emitVerilog(new ScheduleHardware(Schedule(args(0).toInt).schedule, UInt(32.W)), Array("--target-dir", "generated"))
+  emitVerilog(new ScheduleHardware(Schedule(args(0).toInt).schedule, UInt(32.W)), Array("--target-dir", "generated"))
 }

src/main/scala/s4noc/ScheduleTable.scala

@@ -414,8 +414,8 @@ object ScheduleTable {
       "                                                                                                                                                          eel|"
 
   def main(args: Array[String]): Unit = {
-    var cnt = Source.fromFile(args(0)).getLines.length
-    val lines = Source.fromFile(args(0)).getLines
+    var cnt = Source.fromFile(args(0)).getLines().length
+    val lines = Source.fromFile(args(0)).getLines()
     for (l <- lines) {
       val end = if (cnt > 1) " +" else ""
       println("    \"" + l + "l|\"" + end)

src/test/scala/noc/ButterflyTester.scala

@@ -12,7 +12,7 @@ class ButterflyTester extends AnyFlatSpec with ChiselScalatestTester {
       c.io.inPorts(3).port(0).data.poke(7.U)
       for (i <- 0 until 10) {
         c.clock.step(1)
-        println(c.io.outPorts(0).port(3).data.peek.litValue)
+        println(c.io.outPorts(0).port(3).data.peekInt())
       }
       c.io.outPorts(0).port(3).data.expect(7.U)
     }

src/test/scala/s4noc/LatencyTest.scala

@@ -7,7 +7,7 @@ import soc._
 /**
   * Do some performance/latency tests.
   */
-class LatencyTest extends AnyFlatSpec with ChiselScalatestTester {
+class LatencyTest(dontRun: String) extends AnyFlatSpec with ChiselScalatestTester {
 
   behavior of "S4NoC"
 
@@ -33,7 +33,7 @@ class LatencyTest extends AnyFlatSpec with ChiselScalatestTester {
         assert(d.toInt == data(i))
       }
       println("" + CNT + " words sent")
-      println("Bandwidth = " + (d.io.cycCnt.peek.litValue.toFloat / CNT) + " clock cycles per word")
+      println("Bandwidth = " + (d.io.cycCnt.peekInt().toFloat / CNT) + " clock cycles per word")
 
       th.join()
     }