spi: load words from Flash

Author: schoeberl

src/main/scala/spi/SerialSpiTest.scala

@@ -249,10 +249,20 @@ object SerialSpiTest extends App {
   val data = s.getBytes
   // spi.programFlash(1, 0, data)
   // Thread.sleep(1000)
+  val prog = Array(0x11100093, 0x22200113, 0x002081b3)
+  val by = new Array[Byte](12)
+  for (i <- 0 until prog.length) {
+    for (j <- 0 until 4) {
+      val b = prog(i) >> (8 * j) & 0xff
+      println(f"$b%02x")
+      by(i * 4 + j) = b.toByte
+    }
+  }
+  // spi.programFlash(1, 0, by)
 
   val buf = new Array[Byte](20)
-  // spi.readMemory(0, buf)
-  // println(new String(buf))
+  spi.readMemory(0, buf)
+  println(new String(buf))
   /*
   for (i <- 0 until 20) {
     print(spi.readMemory(i).toChar)

src/main/scala/spi/SpiMaster.scala

@@ -15,7 +15,7 @@ class SpiMaster extends Module {
 
   val io = IO(new Bundle {
     val readAddr = Flipped(Decoupled(UInt(24.W)))
-    val readData = Decoupled(UInt(8.W))
+    val readData = Decoupled(UInt(32.W))
   })
 
   object State extends ChiselEnum {
@@ -25,7 +25,7 @@ class SpiMaster extends Module {
   val state = RegInit(idle)
 
   val mosiReg = RegInit(0.U(32.W))
-  val misoReg = RegInit(0.U(8.W))
+  val misoReg = RegInit(0.U(32.W))
   val bitsReg = RegInit(0.U(8.W))
   val cntReg = RegInit(0.U(32.W))
   val CNT_MAX = 1.U
@@ -36,7 +36,8 @@ class SpiMaster extends Module {
   spi.ncs := 1.U
   spi.sclk := 0.U
   spi.mosi := mosiReg(31)
-  io.readData.bits := misoReg
+  // little endian return
+  io.readData.bits := misoReg(7, 0) ## misoReg(15, 8) ## misoReg(23, 16) ## misoReg(31, 24)
   io.readData.valid := false.B
   io.readAddr.ready := false.B
 
@@ -89,7 +90,7 @@ class SpiMaster extends Module {
         bitsReg := bitsReg - 1.U
         when(bitsReg === 0.U) {
           state := rx1
-          bitsReg := 7.U
+          bitsReg := 31.U
         }
       }
     }
@@ -99,7 +100,7 @@ class SpiMaster extends Module {
       spi.sclk := 0.U
       cntReg := cntReg + 1.U
       when(cntReg === CNT_MAX) {
-        misoReg := misoReg(6, 0) ## spi.miso
+        misoReg := misoReg(30, 0) ## spi.miso
         state := rx2
         cntReg := 0.U
       }

src/test/scala/spi/FlashTest.scala

@@ -38,7 +38,7 @@ class FlashTest() extends AnyFlatSpec with ChiselScalatestTester {
         // println("bit: " + bit)
         c.spi.miso.poke(bit)
       }
-      def readByte(addr: Int) = {
+      def readWord(addr: Int) = {
         c.io.readData.ready.poke(true.B)
 
         c.io.readAddr.valid.poke(true.B)
@@ -55,23 +55,22 @@ class FlashTest() extends AnyFlatSpec with ChiselScalatestTester {
 
          */
         var ready = false
-        var ch = ' '
+        var v = 0
         while(!ready) {
           echoPins()
           c.clock.step()
           if (c.io.readData.valid.peekBoolean()) {
             ready = true
-            ch = c.io.readData.bits.peekInt().toChar
+            v = c.io.readData.bits.peekInt().toInt
           }
         }
         c.clock.step()
-        ch
+        v
       }
-      for (i <- 0 until 10) {
-        val c = readByte(i)
-        print(c)
+      for (i <- 0 until 3) {
+        val v = readWord(i*4)
+        println(f"Read 0x$v%08x")
       }
-      println()
     }
   }