soc: rename classes

Author: schoeberl

src/main/scala/s4noc/S4NoCTop.scala

@@ -13,7 +13,7 @@ import soc._
   */
 class S4NoCTop(conf: Config) extends Module  {
   val io = IO(new Bundle {
-    val cpuPorts = Vec(conf.n, new PipeConIO(4)) // TODO: shall we use MultiCoreDevice here?
+    val cpuPorts = Vec(conf.n, new PipeCon(4)) // TODO: shall we use MultiCoreDevice here?
     val cycCnt = Output(UInt(32.W))
   })
 

src/main/scala/soc/PipeCon.scala

@@ -0,0 +1,19 @@
+package soc
+
+import chisel3._
+/**
+ * A simple IO interface, as seen from the slave.
+ * ack is used for acknowledgement in the following clock cycle, or later. (like OCPcore in Patmos).
+ * Can be used to stall the CPU.
+ *
+ * @param addrWidth width of the address part
+ */
+class PipeCon(private val addrWidth: Int) extends Bundle {
+  val address = Input(UInt(addrWidth.W))
+  val rd = Input(Bool())
+  val wr = Input(Bool())
+  val rdData = Output(UInt(32.W))
+  val wrData = Input(UInt(32.W))
+  val wrMask = Input(UInt(4.W))
+  val ack = Output(Bool())
+}

src/main/scala/soc/PipeConDevice.scala

@@ -8,7 +8,7 @@ import chisel3._
   */
 abstract class PipeConDevice(addrWidth: Int) extends Module {
 
-  val cpuPort = IO(new PipeConIO(addrWidth))
+  val cpuPort = IO(new PipeCon(addrWidth))
 
   assert(addrWidth >= 2, "Address width needs some size for byte addresses")
 }

src/main/scala/soc/ports.scala

@@ -11,25 +11,8 @@ package soc
 import chisel3._
 import chisel3.util.DecoupledIO
 
-/**
-  * A simple IO interface, as seen from the slave.
-  * ack is used for acknowledgement in the following clock cycle, or later. (like OCPcore in Patmos).
-  * Can be used to stall the CPU.
-  *
-  * @param addrWidth width of the address part
-  */
-class PipeConIO(private val addrWidth: Int) extends Bundle {
-  val address = Input(UInt(addrWidth.W))
-  val rd = Input(Bool())
-  val wr = Input(Bool())
-  val rdData = Output(UInt(32.W))
-  val wrData = Input(UInt(32.W))
-  val wrMask = Input(UInt(4.W))
-  val ack = Output(Bool())
-}
-
 abstract class MultiCoreDevice(nrCores: Int, addrWidth: Int) extends Module {
-  val ports = IO(Vec(nrCores, new PipeConIO(addrWidth)))
+  val ports = IO(Vec(nrCores, new PipeCon(addrWidth)))
 }
 
 /**

src/main/scala/wishbone/Wrapper.scala

@@ -1,7 +1,7 @@
 package wishbone
 
 import chisel3._
-import soc.PipeConIO
+import soc.PipeCon
 
 /**
   * A Wishbone wrapper for the our PipeCon interface.
@@ -11,7 +11,7 @@ class Wrapper(addrWidth: Int) extends WishboneDevice(addrWidth) {
 
   // TODO: rename to PipeConIO at some point
   val cpuIf = IO(new Bundle {
-    val cpuPort = Flipped(new PipeConIO(addrWidth))
+    val cpuPort = Flipped(new PipeCon(addrWidth))
   })
   val cp = cpuIf.cpuPort
   val wb = io.port

src/test/scala/soc/MemoryMappedIOHelper.scala

@@ -7,7 +7,7 @@ import chiseltest._
  * @param mmio
  * @param clock
  */
-class MemoryMappedIOHelper(mmio: PipeConIO, clock: Clock) {
+class MemoryMappedIOHelper(mmio: PipeCon, clock: Clock) {
 
   private var clockCnt = 0
 

src/test/scala/soc/PipeConDeviceRVTest.scala

@@ -116,8 +116,8 @@ class PipeConDeviceRVTest() extends AnyFlatSpec with ChiselScalatestTester {
   // Connect two CPU interfaces to two FIFOs
   class MyModule2() extends Module {
     val io = IO(new Bundle {
-      val cpA = new PipeConIO(4)
-      val cpB = new PipeConIO(4)
+      val cpA = new PipeCon(4)
+      val cpB = new PipeCon(4)
     })
     val cpifA = Module(new PipeConDeviceRV(4, UInt(32.W)))
     val cpifB = Module(new PipeConDeviceRV(4, UInt(32.W)))