spi: some renaming

Author: schoeberl

src/main/scala/spi/SerialSpiTest.scala renamed to src/main/scala/spi/SerialSpiDriver.scala

@@ -5,10 +5,11 @@ import com.fazecast.jSerialComm._
 import chiseltest._
 
 /**
- * A simple test for SPI communication.
+ * A simple driver for SPI communication via the serial port and the debug interface.
+ * USed from this App, the FlashTest with testing the controller, and should be used by Wildcat in simulation.
  * @param id (Adx, Flash, SRAM)
  */
-class SerialSpiTest(id: Int, portName: String = "/dev/tty.usbserial-210292B408601") {
+class SerialSpiDriver(id: Int, portName: String = "/dev/tty.usbserial-210292B408601") {
 
   // TODO: fix the hard coded port name
   val port = SerialPort.getCommPort(portName)
@@ -230,31 +231,31 @@ class SerialSpiTest(id: Int, portName: String = "/dev/tty.usbserial-210292B40860
     readStatusRegister()
   }
 
-  def echoPinsOuter(sck: Int, mosi: Int, ncs: Int) = {
-    // println(s"ncs: $ncs, mosi: $mosi, sck: $sck")
+  /**
+   * Watch SPI output pins in simulation and forward them via the serial port debugger to the real Flash.
+   * And the other way around, read the MISO pin from the Flash and forward it to the SPI input pin in simulation.
+   * @param spi
+   */
+  def echoPins(spi: SpiIO) = {
+    val sck = spi.sclk.peekInt().toInt
+    val mosi = spi.mosi.peekInt().toInt
+    val ncs = spi.ncs.peekInt().toInt
     val bits = (ncs << 2) | (mosi << 1) | sck
     val s = "w4" + (bits + '0').toChar + "4\r"
     writeReadSerial(s)
     val rx = writeReadSerial("r")
     // '8' is MISO bit set
     val bit = if (rx(8 - 1) == '8') 1 else 0
-    // println("rx: " + rx)
-    // println("bit: " + bit)
-    bit
-  }
-
-  def echoPins(spi: SpiIO) = {
-    val sck = spi.sclk.peekInt().toInt
-    val mosi = spi.mosi.peekInt().toInt
-    val ncs = spi.ncs.peekInt().toInt
-    val bit = echoPinsOuter(sck, mosi, ncs)
     spi.miso.poke(bit)
   }
 }
 
-object SerialSpiTest extends App {
+/**
+ * Test SPI components and program the Flash.
+ */
+object SerialSpiDriver extends App {
 
-  val spi = new SerialSpiTest(1) // Flash
+  val spi = new SerialSpiDriver(1) // Flash
 
   spi.csLow()
   print(spi.writeReadSerial("r"))
@@ -298,7 +299,7 @@ object SerialSpiTest extends App {
 
 
   println("SRAM test")
-  val sram = new SerialSpiTest(2) // SRAM
+  val sram = new SerialSpiDriver(2) // SRAM
   sram.readJedecIdWait()
   sram.readMemory(0)
   sram.writeSram(0, 0x55)

src/test/scala/spi/FlashTest.scala

@@ -1,19 +1,17 @@
 package spi
 
 import chisel3._
-import chisel3.util._
 import chiseltest._
 import org.scalatest.flatspec.AnyFlatSpec
-import spi.SerialSpiTest.spi
 
 class FlashTest() extends AnyFlatSpec with ChiselScalatestTester {
   behavior of "FlashTest"
 
   it should "test the flash" in {
 
-    var spiDriver: SerialSpiTest = null
+    var spiDriver: SerialSpiDriver = null
     try {
-      spiDriver = new SerialSpiTest(1)
+      spiDriver = new SerialSpiDriver(1)
     } catch {
       case e: Exception => {
         println("Serial port not available")
@@ -23,17 +21,7 @@ class FlashTest() extends AnyFlatSpec with ChiselScalatestTester {
 
     test(new SpiMaster) { c =>
 
-      /*
-      def echoPins() = {
-        val sck = c.spi.sclk.peekInt().toInt
-        val mosi = c.spi.mosi.peekInt().toInt
-        val ncs = c.spi.ncs.peekInt().toInt
-        val bit = spiDriver.echoPinsOuter(sck, mosi, ncs)
-        c.spi.miso.poke(bit)
-      }
-
-       */
-      def readWord(addr: Int) = {
+      def readWord(addr: Int): Int = {
         c.io.readData.ready.poke(true.B)
 
         c.io.readAddr.valid.poke(true.B)