Start with UART debugger

Author: schoeberl

src/main/scala/debug/UartDebug.scala

@@ -5,26 +5,32 @@ import chisel3._
 import chisel3.util._
 
 /**
-  * This is the top level to for the UART output and a test blinking LED.
+  * Poor mans debugger, using a UART instead of JTAG.
   */
-class UartDebug(frequ: Int) extends Module {
+class UartDebug(frequ: Int, baudRate: Int = 115200) extends Module {
   val io = IO(new Bundle {
     val rx = Input(Bool())
     val tx = Output(Bool())
     val dout = Output(UInt(32.W))
     val din = Input(UInt(32.W))
   })
 
-  val tx = Module(new BufferedTx(100000000, 115200))
-  val rx = Module(new Rx(100000000, 115200))
+  val tx = Module(new BufferedTx(100000000, baudRate))
+  val rx = Module(new Rx(100000000, baudRate))
 
   io.tx := tx.io.txd
   rx.io.rxd := io.rx
 
+  tx.io.channel.bits := rx.io.channel.bits + 1.U
+  tx.io.channel.valid := rx.io.channel.valid
+  rx.io.channel.ready := tx.io.channel.ready
 
+  io.dout := 0x1234.U
+  when (tx.io.channel.valid && tx.io.channel.ready) {
+    io.dout := tx.io.channel.bits
+  }
 }
 
-// generate Verilog
 object UartDebug extends App {
   emitVerilog(new UartDebug(100000000),  Array("--target-dir", "generated"))
 }

src/test/scala/debug/UartDebugTest.scala

@@ -0,0 +1,43 @@
+package debug
+
+import chisel.lib.uart._
+import chisel3._
+import chisel3.util._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+
+class UartDebugTestTop extends Module {
+  val io = IO(new Bundle {
+    val inRx = new UartIO()
+    val outTx = Flipped(new UartIO())
+    val dout = Output(UInt(32.W))
+    val din = Input(UInt(32.W))
+  })
+
+  val tx = Module(new BufferedTx(100000000, 100000000/16))
+  val rx = Module(new Rx(100000000, 100000000/16))
+
+  io.outTx <> tx.io.channel
+  io.inRx <> rx.io.channel
+
+  val dbg = Module(new UartDebug(100000000, 100000000/16))
+
+  dbg.io.rx := tx.io.txd
+  rx.io.rxd := dbg.io.tx
+  io.dout := dbg.io.dout
+  dbg.io.din := io.din
+}
+
+class UartDebugTest extends AnyFlatSpec with ChiselScalatestTester {
+  "UartDebug" should "work" in {
+    test(new UartDebugTestTop()).withAnnotations(Seq(WriteVcdAnnotation)) { dut =>
+      dut.io.din.poke(0xabcd.U)
+      dut.clock.setTimeout(10001)
+      dut.io.outTx.valid.poke(true.B)
+      dut.io.outTx.bits.poke(0x42.U)
+      dut.clock.step(10)
+      dut.io.outTx.valid.poke(false.B)
+      dut.clock.step(1000)
+    }
+  }
+}

src/test/scala/spi/TestSpiMaster.scala

@@ -72,7 +72,7 @@ class TopTest extends Module {
 
   io.dout := ctrl.io.dataOut
 }
-class TestSpiMaster extends AnyFlatSpec with ChiselScalatestTester {
+class TestSpiMaster(doNotRun: String) extends AnyFlatSpec with ChiselScalatestTester {
 
   /*
   "SpiMaster" should "work" in {