spi: controller can read JTAD ID from Flash

Author: schoeberl

src/main/scala/spi/SerialSpiTest.scala

@@ -34,7 +34,8 @@ class SerialSpiTest(id: Int, portName: String = "/dev/tty.usbserial-210292B40860
       }
     }
     // print("Received: " + ret)
-    // Thread.sleep(100)
+
+    Thread.sleep(10)
     ret
   }
 
@@ -203,7 +204,6 @@ class SerialSpiTest(id: Int, portName: String = "/dev/tty.usbserial-210292B40860
 
 object SerialSpiTest extends App {
 
-
   val spi = new SerialSpiTest(1) // Flash
 
   spi.csLow()
@@ -232,7 +232,6 @@ object SerialSpiTest extends App {
   }
   println()
    */
-
   print(spi.writeReadSerial(spi.setCmd(4))) // all CS high
   spi.out.close()
   spi.port.closePort()

src/main/scala/spi/SpiMaster.scala

@@ -21,7 +21,7 @@ class SpiMaster extends Module {
   })
 
   object State extends ChiselEnum {
-    val start, idle, tx1, tx2, rx1, rx2, done = Value
+    val start, idle, tx1, tx2, rx1, rx2, done1, done2 = Value
   }
   import State._
   val state = RegInit(idle)
@@ -98,10 +98,10 @@ class SpiMaster extends Module {
       spi.sclk := 0.U
       cntReg := cntReg + 1.U
       when(cntReg === CNT_MAX) {
-        misoReg := misoReg(7, 1) ## spi.miso
+        misoReg := misoReg(6, 0) ## spi.miso
+        printf(cf"HW Data is shifting in: $misoReg \n")
         state := rx2
         cntReg := 0.U
-        bitsReg := bitsReg - 1.U
       }
     }
     is(rx2) {
@@ -113,17 +113,29 @@ class SpiMaster extends Module {
         cntReg := 0.U
         bitsReg := bitsReg - 1.U
         when(bitsReg === 0.U) {
-          state := done
+          state := done1
         }
       }
     }
-    is(done) {
+    is(done1) {
+      printf("done\n")
+      spi.ncs := 0.U
+      spi.sclk := 0.U
+      cntReg := cntReg + 1.U
+      io.dataReady := true.B
+      printf(cf"HW Data is $misoReg \n")
+      when(cntReg === CNT_MAX) {
+        state := done2
+        cntReg := 0.U
+      }
+    }
+    is(done2) {
       spi.ncs := 1.U
       spi.sclk := 0.U
       cntReg := cntReg + 1.U
       io.dataReady := true.B
       when(cntReg === CNT_MAX) {
-        state := start
+        state := done2
         cntReg := 0.U
       }
     }

src/test/scala/spi/FlashTest.scala

@@ -11,18 +11,21 @@ class FlashTest extends AnyFlatSpec with ChiselScalatestTester {
 
   it should "test the flash" in {
     val spi = new SerialSpiTest(1)
-    spi.csLow()
-    print(spi.writeReadSerial("r"))
-    spi.csHigh()
     test(new SpiMaster) { c =>
-      for(i <- 0 until 1000) {
+      for(i <- 0 until 200) {
         val sck = c.spi.sclk.peekInt()
         val mosi = c.spi.mosi.peekInt()
         val ncs = c.spi.ncs.peekInt()
-        // println(s"sck: $sck, mosi: $mosi, ncs: $ncs")
+        // println(s"ncs: $ncs, mosi: $mosi, sck: $sck")
         val bits = (ncs << 2) | (mosi << 1) | sck
         val s = "w4" + (bits + '0').toChar + "4\r"
         spi.writeReadSerial(s)
+        val rx = spi.writeReadSerial("r")
+        // '8' is MISO bit set
+        val bit = if (rx(8 - 1) == '8') 1 else 0
+        // println("rx: " + rx)
+        // println("bit: " + bit)
+        c.spi.miso.poke(bit)
         println(s)
         c.clock.step()
         // println("dout: " + c.io.dataOut.peekInt())