Change to byte addressing

Author: schoeberl

README.md

@@ -135,11 +135,11 @@ provide a standard mapping for the ```PipeCon```, the ```PipeConRV```:
  * CPU interface to two ready/valid channels (one for transmit/tx, one for receive/rx).
  * IO mapping as in the classic PC serial port (UART)
  * 0: status (control): bit 0 tx ready, bit 1 rx data available
- * 1: write into txd and read from rxd
+ * 4: write into txd and read from rxd
 
 Additionally, for the S4NOC we provide following port:
 
- * 2: write receiver, read sender (S4NOC specific)
+ * 8: write receiver, read sender (S4NOC specific)
 
 
 
@@ -193,7 +193,7 @@ To analyze memory issues (e.g., increase the heap size with Xmx) use a ```.sbtop
 ## TODO
 
  * [x] Use and document the PipeCon, direction from slave
-   * Or stick to the CpuInterface as it is and rename it
+ * [ ] Use a better name for the PipeCon interface (not io)
  * [ ] Wrapper for OCP (in Patmos)
  * [ ] Integrate a simple multicore device with T-CREST
    * A multicore "Hello World"
@@ -221,7 +221,7 @@ class S4nocOCPWrapper(nrCores: Int, txFifo: Int, rxFifo: Int) extends CmpDevice(
       OcpResp.DVA, OcpResp.NULL)
 
     // addresses are in words
-    s4noc.io.cpuPorts(i).addr := io.cores(i).M.Addr >> 2
+    s4noc.io.cpuPorts(i).addr := io.cores(i).M.Addr
     s4noc.io.cpuPorts(i).wrData := io.cores(i).M.Data
     s4noc.io.cpuPorts(i).wr := io.cores(i).M.Cmd === OcpCmd.WR
     s4noc.io.cpuPorts(i).rd := io.cores(i).M.Cmd === OcpCmd.RD

src/main/scala/s4noc/PipeConS4NoC.scala

@@ -0,0 +1,9 @@
+package s4noc
+
+import chisel3._
+
+import soc._
+
+class PipeConS4NoC[T <: Data](private val addrWidth: Int, private val dt: T) extends PipeConRV(addrWidth, dt, true){
+
+}

src/main/scala/s4noc/S4NoCTop.scala

@@ -5,7 +5,7 @@ import soc._
 
 
 /**
-  * Top level of the S4NOC with CPU interfaces.
+  * Top level of the S4NOC with PipeCon CPU interfaces.
   *
   * Author: Martin Schoeberl ([email protected])
   * license see LICENSE
@@ -19,7 +19,7 @@ class S4NoCTop(conf: Config) extends Module  {
 
   val s4noc = Module(new S4NoC(conf))
   for (i <- 0 until conf.n) {
-    val ci = Module(new PipeConRV(conf.width, Entry(UInt(conf.width.W)), true))
+    val ci = Module(new PipeConS4NoC(conf.width, Entry(UInt(conf.width.W))))
     s4noc.io.networkPort(i) <> ci.rv
     io.cpuPorts(i) <> ci.io.cpuPort
   }

src/main/scala/soc/HardwareLock.scala

@@ -13,7 +13,7 @@ import chisel3._
   *
   * Could be extended to a multicore lock.
   */
-class HardwareLock() extends PipeCon(0) {
+class HardwareLock() extends PipeCon(2) {
 
   val lockReg = RegInit(false.B)
   val ackReg = RegInit(false.B)

src/main/scala/soc/HelloDevice.scala

@@ -5,14 +5,14 @@ import chisel3._
 /**
   * An minimal IO device.
   * It contains a single register to write and read at address 0
-  * and the read-only core ID at address 1.
+  * and the read-only core ID at address 4.
   *
   * @param coreId
   */
-class HelloDevice(coreId: Int) extends PipeCon(2) {
+class HelloDevice(coreId: Int) extends PipeCon(3) {
 
-  // TODO: following five lines are duplicated in CpuInterfaceRV, back to CpuInterface?
-  val addrReg = RegInit(0.U(2.W))
+  // TODO: following five lines are duplicated in PipeConRV, back to PipeCon class?
+  val addrReg = RegInit(0.U(3.W))
   val ackReg = RegInit(false.B)
   when (cp.rd) {
     addrReg := cp.address
@@ -25,10 +25,10 @@ class HelloDevice(coreId: Int) extends PipeCon(2) {
     reg := cp.wrData
   }
   ackReg := cp.wr || cp.rd
-  cp.rdData := Mux(addrReg === 1.U, nr, reg)
+  cp.rdData := Mux(addrReg === 4.U, nr, reg)
 }
 
-class MultiCoreHello(nrCores: Int) extends MultiCoreDevice(nrCores, 2) {
+class MultiCoreHello(nrCores: Int) extends MultiCoreDevice(nrCores, 3) {
 
   for(i <- 0 until nrCores) {
     val d = Module(new HelloDevice(i))

src/main/scala/soc/PipeCon.scala

@@ -11,6 +11,7 @@ abstract class PipeCon(addrWidth: Int) extends Module {
     val cpuPort = new PipeConIO(addrWidth)
   })
   val cp = io.cpuPort
+  assert(addrWidth >= 2, "Address width needs some size for byte addresses")
 }
 
 

src/main/scala/soc/PipeConRV.scala

@@ -8,12 +8,13 @@ import s4noc.Entry
   * CPU interface to two ready/valid channels.
   * IO mapping as in classic PC serial port
   * 0: status (control): bit 0 transmit ready, bit 1 rx data available
-  * 1: txd and rxd
-  * 2: write receiver, read sender
+  * 4: txd and rxd
+ * S4NOC:
+  * 8: write receiver, read sender
   * TODO: compare with Chisel book version
   * TODO: make it generic and do a subtype for s4noc
   */
-class PipeConRV[T <: Data](private val addrWidth: Int, private val dt: T, s4noc: Boolean = false ) extends PipeCon(addrWidth) {
+class PipeConRV[T <: Data](private val addrWidth: Int, private val dt: T, s4noc: Boolean = false) extends PipeCon(addrWidth) {
 
   val rv = IO(new ReadyValidChannelsIO(dt))
 
@@ -52,7 +53,7 @@ class PipeConRV[T <: Data](private val addrWidth: Int, private val dt: T, s4noc:
   def idleReaction() = {
     when (cp.wr) {
       // printf("Write %d to %d\n", cp.wrData, cp.address)
-      when (cp.address === 2.U) {
+      when (cp.address === 8.U) {
         txDestReg := cp.wrData
         ackReg := true.B
       } .otherwise {
@@ -70,7 +71,7 @@ class PipeConRV[T <: Data](private val addrWidth: Int, private val dt: T, s4noc:
       when (cp.address === 0.U) {
         stateReg := readStatus
         ackReg := true.B
-      } .elsewhen (cp.address === 2.U) {
+      } .elsewhen (cp.address === 8.U) {
         stateReg := readSource
         ackReg := true.B
       } .otherwise {

src/main/scala/wishbone/Wrapper.scala

@@ -11,12 +11,12 @@ class Wrapper(addrWidth: Int) extends WishboneDevice(addrWidth) {
 
   // TODO: rename to PipeConIO at some point
   val cpuIf = IO(new Bundle {
-    val cpuPort = Flipped(new PipeConIO(addrWidth-2))
+    val cpuPort = Flipped(new PipeConIO(addrWidth))
   })
   val cp = cpuIf.cpuPort
   val wb = io.port
 
-  cp.address := wb.addr >> 2
+  cp.address := wb.addr
   cp.wrData := wb.wrData
   cp.wrMask := "b1111".U
   wb.rdData := cp.rdData

src/test/scala/soc/HelloTest.scala

@@ -59,7 +59,7 @@ class HelloTest extends AnyFlatSpec with ChiselScalatestTester {
         cp.ack.expect(true.B)
         cp.rdData.expect(0xabcd.U)
         //test CPU ID
-        cp.address.poke(0x1.U)
+        cp.address.poke(0x4.U)
         step()
         cp.rdData.expect(3.U)
         cp.ack.expect(true.B)
@@ -114,9 +114,9 @@ class HelloTest extends AnyFlatSpec with ChiselScalatestTester {
         cp(0).rdData.expect(123.U)
         cp(1).rdData.expect(456.U)
         cp(2).rdData.expect(789.U)
-        cp(0).address.poke(1.U)
-        cp(1).address.poke(1.U)
-        cp(2).address.poke(1.U)
+        cp(0).address.poke(4.U)
+        cp(1).address.poke(4.U)
+        cp(2).address.poke(4.U)
         step()
         cp(0).rdData.expect(0.U)
         cp(1).rdData.expect(1.U)
@@ -133,11 +133,11 @@ class HelloTest extends AnyFlatSpec with ChiselScalatestTester {
         val helper = new MemoryMappedIOHelper(dut.cp, dut.clock)
 
         helper.setTimeOut(10)
-        helper.read(1)
+        helper.read(4)
         step()
         step()
         // println(helper.read(0))
-        // println(helper.read(1))
+        // println(helper.read(4))
         step()
         step()
         helper.write(0, 123)

src/test/scala/soc/MemoryMappedIOHelper.scala

@@ -51,12 +51,12 @@ class MemoryMappedIOHelper(mmio: PipeConIO, clock: Clock) {
     waitForAck()
   }
 
-  def setDest(n: Int) = write(2, n)
-  def getSender() = read(2)
+  def setDest(n: Int) = write(8, n)
+  def getSender() = read(8)
 
   // send and receive without status check, may block
-  def send(data: BigInt) = write(1, data)
-  def receive = read(1)
+  def send(data: BigInt) = write(4, data)
+  def receive = read(4)
 
   // The following functions use the IO mapping with status bits add address 0 and data at address 1
   def txRdy = (read(0) & 0x01) != 0