soc: rename classes

Author: schoeberl

src/main/scala/s4noc/PipeConDeviceS4NoC.scala

@@ -0,0 +1,9 @@
+package s4noc
+
+import chisel3._
+
+import soc._
+
+class PipeConDeviceS4NoC[T <: Data](private val addrWidth: Int, private val dt: T) extends PipeConDeviceRV(addrWidth, dt, true){
+
+}

src/main/scala/s4noc/PipeConS4NoC.scala

@@ -19,7 +19,7 @@ class S4NoCTop(conf: Config) extends Module  {
 
   val s4noc = Module(new S4NoC(conf))
   for (i <- 0 until conf.n) {
-    val ci = Module(new PipeConS4NoC(4, Entry(UInt(conf.width.W))))
+    val ci = Module(new PipeConDeviceS4NoC(4, Entry(UInt(conf.width.W))))
     s4noc.io.networkPort(i) <> ci.rv
     io.cpuPorts(i) <> ci.cpuPort
   }

src/main/scala/s4noc/S4NoCTop.scala

@@ -13,7 +13,7 @@ import chisel3._
   *
   * Could be extended to a multicore lock.
   */
-class HardwareLock() extends PipeCon(2) {
+class HardwareLock() extends PipeConDevice(2) {
 
   val lockReg = RegInit(false.B)
   val ackReg = RegInit(false.B)

src/main/scala/soc/HardwareLock.scala

@@ -9,7 +9,7 @@ import chisel3._
   *
   * @param coreId
   */
-class HelloDevice(coreId: Int) extends PipeCon(3) {
+class HelloDevice(coreId: Int) extends PipeConDevice(3) {
 
   // TODO: following five lines are duplicated in PipeConRV, back to PipeCon class?
   val addrReg = RegInit(0.U(3.W))

src/main/scala/soc/HelloDevice.scala

@@ -6,7 +6,7 @@ import chisel3._
   * Just a CPU interface, without any additional connection.
   *
   */
-abstract class PipeCon(addrWidth: Int) extends Module {
+abstract class PipeConDevice(addrWidth: Int) extends Module {
 
   val cpuPort = IO(new PipeConIO(addrWidth))
 

src/main/scala/soc/PipeCon.scala renamed to src/main/scala/soc/PipeConDevice.scala

@@ -15,7 +15,7 @@ import s4noc.Entry
   * TODO: make it generic and do a subtype for s4noc
   * TODO: have some better tests
   */
-class PipeConRV[T <: Data](private val addrWidth: Int, private val dt: T, s4noc: Boolean = false) extends PipeCon(addrWidth) {
+class PipeConDeviceRV[T <: Data](private val addrWidth: Int, private val dt: T, s4noc: Boolean = false) extends PipeConDevice(addrWidth) {
 
   val rv = IO(new ReadyValidChannelsIO(dt))
 

src/main/scala/soc/PipeConRV.scala renamed to src/main/scala/soc/PipeConDeviceRV.scala

@@ -7,11 +7,11 @@ import chiseltest._
 import org.scalatest.flatspec.AnyFlatSpec
 import s4noc.Entry
 
-class PipeConRVTest() extends AnyFlatSpec with ChiselScalatestTester {
+class PipeConDeviceRVTest() extends AnyFlatSpec with ChiselScalatestTester {
   behavior of "The CpuInterfaceRV"
 
   it should "do something" in {
-    test(new PipeConRV(4, UInt(32.W))).withAnnotations(Seq(WriteVcdAnnotation)) {
+    test(new PipeConDeviceRV(4, UInt(32.W))).withAnnotations(Seq(WriteVcdAnnotation)) {
       d => {
 
         def step() = d.clock.step()
@@ -82,8 +82,8 @@ class PipeConRVTest() extends AnyFlatSpec with ChiselScalatestTester {
   }
 
   // Connect a CPU interface to a FIFO
-  class MyModule() extends PipeCon(4) {
-    val cpif = Module(new PipeConRV(4, UInt(32.W)))
+  class MyModule() extends PipeConDevice(4) {
+    val cpif = Module(new PipeConDeviceRV(4, UInt(32.W)))
     val fifo = Module(new BubbleFifo(UInt(32.W), 4))
     cpuPort <> cpif.cpuPort
     cpif.tx <> fifo.io.enq
@@ -119,8 +119,8 @@ class PipeConRVTest() extends AnyFlatSpec with ChiselScalatestTester {
       val cpA = new PipeConIO(4)
       val cpB = new PipeConIO(4)
     })
-    val cpifA = Module(new PipeConRV(4, UInt(32.W)))
-    val cpifB = Module(new PipeConRV(4, UInt(32.W)))
+    val cpifA = Module(new PipeConDeviceRV(4, UInt(32.W)))
+    val cpifB = Module(new PipeConDeviceRV(4, UInt(32.W)))
     val fifoA = Module(new MemFifo(UInt(32.W), 4))
     val fifoB = Module(new MemFifo(UInt(32.W), 4))
 
@@ -200,8 +200,8 @@ class PipeConRVTest() extends AnyFlatSpec with ChiselScalatestTester {
   }
 
   // Connect a CPU interface to a FIFO with Entry
-  class MyModule3() extends PipeCon(4) {
-    val cpif = Module(new PipeConRV(4, Entry(UInt(32.W)), true))
+  class MyModule3() extends PipeConDevice(4) {
+    val cpif = Module(new PipeConDeviceRV(4, Entry(UInt(32.W)), true))
     val fifo = Module(new BubbleFifo(Entry(UInt(32.W)), 4))
     cpuPort <> cpif.cpuPort
     cpif.tx <> fifo.io.enq