SPI controller reads the Flash

Author: schoeberl

src/main/scala/spi/SerialSpiTest.scala

@@ -35,7 +35,7 @@ class SerialSpiTest(id: Int, portName: String = "/dev/tty.usbserial-210292B40860
     }
     // print("Received: " + ret)
 
-    Thread.sleep(10)
+    // Thread.sleep(10)
     ret
   }
 

src/main/scala/spi/SpiMaster.scala

@@ -14,10 +14,8 @@ class SpiMaster extends Module {
   val spi = IO(new SpiIO)
 
   val io = IO(new Bundle {
-    val dataOut = Output(UInt(8.W))
-    val dataIn = Input(UInt(8.W))
-    val dataValid = Input(Bool())
-    val dataReady = Output(Bool())
+    val readAddr = Flipped(Decoupled(UInt(24.W)))
+    val readData = Decoupled(UInt(8.W))
   })
 
   object State extends ChiselEnum {
@@ -26,19 +24,21 @@ class SpiMaster extends Module {
   import State._
   val state = RegInit(idle)
 
-  val mosiReg = RegInit(0.U(8.W))
+  val mosiReg = RegInit(0.U(32.W))
   val misoReg = RegInit(0.U(8.W))
   val bitsReg = RegInit(0.U(8.W))
   val cntReg = RegInit(0.U(32.W))
   val CNT_MAX = 1.U
 
 
   // TODO: should those signals be in a register? Probably better timing
+  // at least SCLK
   spi.ncs := 1.U
   spi.sclk := 0.U
-  spi.mosi := mosiReg(7)
-  io.dataOut := misoReg
-  io.dataReady := false.B
+  spi.mosi := mosiReg(31)
+  io.readData.bits := misoReg
+  io.readData.valid := false.B
+  io.readAddr.ready := false.B
 
   val JTAG_ID = 0x9f.U
   val RD_STATUS = 0x05.U
@@ -60,13 +60,14 @@ class SpiMaster extends Module {
       spi.sclk := 0.U
       cntReg := cntReg + 1.U
       when(cntReg === CNT_MAX) {
-        // + when data is available
-        state := tx1
-        bitsReg := 7.U
-        cntReg := 0.U
-        mosiReg := JTAG_ID
+        io.readAddr.ready := true.B
+        when(io.readAddr.valid) {
+          state := tx1
+          bitsReg := 31.U
+          cntReg := 0.U
+          mosiReg := READ ## io.readAddr.bits
+        }
       }
-
     }
     is(tx1) {
       spi.ncs := 0.U
@@ -84,7 +85,7 @@ class SpiMaster extends Module {
       when(cntReg === CNT_MAX) {
         state := tx1
         cntReg := 0.U
-        mosiReg := mosiReg(6, 0) ## 0.U // io.dataIn(7))
+        mosiReg := mosiReg << 1
         bitsReg := bitsReg - 1.U
         when(bitsReg === 0.U) {
           state := rx1
@@ -99,7 +100,6 @@ class SpiMaster extends Module {
       cntReg := cntReg + 1.U
       when(cntReg === CNT_MAX) {
         misoReg := misoReg(6, 0) ## spi.miso
-        printf(cf"HW Data is shifting in: $misoReg \n")
         state := rx2
         cntReg := 0.U
       }
@@ -118,12 +118,9 @@ class SpiMaster extends Module {
       }
     }
     is(done1) {
-      printf("done\n")
       spi.ncs := 0.U
       spi.sclk := 0.U
       cntReg := cntReg + 1.U
-      io.dataReady := true.B
-      printf(cf"HW Data is $misoReg \n")
       when(cntReg === CNT_MAX) {
         state := done2
         cntReg := 0.U
@@ -133,10 +130,9 @@ class SpiMaster extends Module {
       spi.ncs := 1.U
       spi.sclk := 0.U
       cntReg := cntReg + 1.U
-      io.dataReady := true.B
-      when(cntReg === CNT_MAX) {
-        state := done2
-        cntReg := 0.U
+      io.readData.valid := true.B
+      when(io.readData.ready) {
+        state := idle
       }
     }
   }

src/test/scala/spi/FlashTest.scala

@@ -6,13 +6,24 @@ import chiseltest._
 import org.scalatest.flatspec.AnyFlatSpec
 import spi.SerialSpiTest.spi
 
-class FlashTest(dontRun: String) extends AnyFlatSpec with ChiselScalatestTester {
+class FlashTest() extends AnyFlatSpec with ChiselScalatestTester {
   behavior of "FlashTest"
 
   it should "test the flash" in {
-    val spi = new SerialSpiTest(1)
+
+    var spi: SerialSpiTest = null
+    try {
+      spi = new SerialSpiTest(1)
+    } catch {
+      case e: Exception => {
+        println("Serial port not available")
+        cancel()
+      }
+    }
+
     test(new SpiMaster) { c =>
-      for(i <- 0 until 200) {
+
+      def echoPins() = {
         val sck = c.spi.sclk.peekInt()
         val mosi = c.spi.mosi.peekInt()
         val ncs = c.spi.ncs.peekInt()
@@ -26,13 +37,41 @@ class FlashTest(dontRun: String) extends AnyFlatSpec with ChiselScalatestTester
         // println("rx: " + rx)
         // println("bit: " + bit)
         c.spi.miso.poke(bit)
-        println(s)
+      }
+      def readByte(addr: Int) = {
+        c.io.readData.ready.poke(true.B)
+
+        c.io.readAddr.valid.poke(true.B)
+        c.io.readAddr.bits.poke(addr.U)
+        echoPins()
         c.clock.step()
-        // println("dout: " + c.io.dataOut.peekInt())
-        if (c.io.dataReady.peekBoolean()) {
-          println("Data is " + c.io.dataOut.peekInt())
+        /*
+        while(!c.io.readAddr.ready.peekBoolean()) {
+          c.io.readAddr.valid.poke(true.B)
+          echoPins()
+          c.clock.step()
+        }
+        c.io.readAddr.valid.poke(false.B)
+
+         */
+        var ready = false
+        var ch = ' '
+        while(!ready) {
+          echoPins()
+          c.clock.step()
+          if (c.io.readData.valid.peekBoolean()) {
+            ready = true
+            ch = c.io.readData.bits.peekInt().toChar
+          }
         }
+        c.clock.step()
+        ch
+      }
+      for (i <- 0 until 10) {
+        val c = readByte(i)
+        print(c)
       }
+      println()
     }
   }
 

src/test/scala/spi/TestSpiMaster.scala

@@ -67,10 +67,10 @@ class TopTest extends Module {
   flash.io.HOLDNeg := true.B
   ctrl.spi.miso := flash.io.SO
 
-  ctrl.io.dataIn := 0.U
-  ctrl.io.dataValid := false.B
+  ctrl.io.readAddr.bits := 0.U
+  ctrl.io.readAddr.valid := false.B
 
-  io.dout := ctrl.io.dataOut
+  io.dout := ctrl.io.readData.bits
 }
 class TestSpiMaster(doNotRun: String) extends AnyFlatSpec with ChiselScalatestTester {