Use UartDebug in BitBang

Author: schoeberl

7series.txt

@@ -18,5 +18,5 @@ puts [irscan xc7.tap 0x09]
 puts [drscan xc7.tap 32 0]  
 
 puts "Programming FPGA..."
-pld load 0 build/UartDebug.bit
+pld load 0 build/BitBang.bit
 exit

Makefile

@@ -27,7 +27,7 @@ vcd:
 synpath:
 	source /home/shared/Xilinx/Vivado/2017.4/settings64.sh
 
-HW = UartDebug
+HW = BitBang
 
 synth:
 	./vivado_synth.sh -t $(HW) -p xc7a100tcsg324-1 -x nexysA7.xdc -o build generated/$(HW).v

src/main/scala/debug/UartDebug.scala

@@ -157,7 +157,3 @@ class UartDebug(frequ: Int, baudRate: Int = 115200) extends Module {
   }
   io.dout := doutReg
 }
-
-object UartDebug extends App {
-  emitVerilog(new UartDebug(100000000),  Array("--target-dir", "generated"))
-}

src/main/scala/spi/BitBang.scala

@@ -4,6 +4,8 @@ import chisel.lib.uart._
 import chisel3._
 import chisel3.util._
 
+import debug._
+
 /**
   * This is the top level to for the UART output and a test blinking LED.
   */
@@ -20,17 +22,17 @@ class BitBang(frequ: Int) extends Module {
   })
   io.led := io.sw
 
-  val tx = Module(new BufferedTx(100000000, 115200))
-  val rx = Module(new Rx(100000000, 115200))
+  val dbg = Module(new UartDebug(100000000, 115200))
+
+  dbg.io.rx := io.rx
+  io.tx := dbg.io.tx
+
+  dbg.io.din := ~dbg.io.dout
 
-  io.tx := tx.io.txd
-  rx.io.rxd := io.rx
+  val regVal = RegInit(0.U(3.W))
 
-  tx.io.channel.bits := '0'.U + io.miso
-  tx.io.channel.valid := rx.io.channel.valid
-  rx.io.channel.ready := true.B
-  val regVal = RegEnable('0'.U + rx.io.channel.bits(3, 0), rx.io.channel.valid)
-  io.led := io.miso ## regVal(2, 0)
+  regVal := dbg.io.dout(2, 0)
+  io.led := io.miso ## dbg.io.dout(2, 0)
 
   io.sck := regVal(0)
   io.mosi := regVal(1)