Towards newer Chisel versions

Author: schoeberl

src/main/scala/arbiter/ArbiterTree.scala

@@ -2,7 +2,6 @@ package arbiter
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.ChiselEnum
 
 
 // Only one will be ready, as we cannot take two values

src/main/scala/debug/UartDebug.scala

@@ -3,7 +3,6 @@ package debug
 import chisel.lib.uart._
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.ChiselEnum
 
 /**
   * Poor mans debugger, using a UART instead of JTAG.

src/main/scala/s4noc/Network.scala

@@ -7,7 +7,7 @@
 package s4noc
 
 import chisel3._
-import Const._
+import s4noc.Const._
 
 /**
  * Create and connect a n x n NoC.

src/main/scala/s4noc/S4Router.scala

@@ -23,11 +23,11 @@ class S4Router[T <: Data](schedule: Array[Array[Int]], dt: T) extends Module {
 
   // Just convert schedule table to a Chisel type table
   // unused slot is -1, convert to 0.U
-  val sched = Wire(Vec(schedule.length, Vec(Const.NR_OF_PORTS, UInt(3.W))))
+  val sched = Wire(Vec(schedule.length, Vec(s4noc.Const.NR_OF_PORTS, UInt(3.W))))
   for (i <- 0 until schedule.length) {
-    for (j <- 0 until Const.NR_OF_PORTS) {
+    for (j <- 0 until s4noc.Const.NR_OF_PORTS) {
       val s = schedule(i)(j)
-      val v = if (s == -1) Const.INVALID else s
+      val v = if (s == -1) s4noc.Const.INVALID else s
       sched(i)(j) := v.U(3.W)
     }
   }
@@ -38,9 +38,9 @@ class S4Router[T <: Data](schedule: Array[Array[Int]], dt: T) extends Module {
   // TODO: test if this movement of the register past the schedule table works, better here a register
   // val currentSched = RegNext(sched(regCounter))
 
-  for (j <- 0 until Const.NR_OF_PORTS) {
+  for (j <- 0 until s4noc.Const.NR_OF_PORTS) {
     io.ports(j).out.data := RegNext(io.ports(currentSched(j)).in.data)
-    io.ports(j).out.valid := RegNext(Mux(currentSched(j) === Const.INVALID.U, false.B, io.ports(currentSched(j)).in.valid), init = false.B)
+    io.ports(j).out.valid := RegNext(Mux(currentSched(j) === s4noc.Const.INVALID.U, false.B, io.ports(currentSched(j)).in.valid), init = false.B)
   }
 }
 

src/main/scala/s4noc/ScheduleHardware.scala

@@ -15,23 +15,23 @@ import chisel3.util._
 class ScheduleHardware[T <: Data](schedule: Array[Array[Int]], dt: T) extends Module {
   val io = IO(new Bundle() {
     val in = Input(UInt(16.W))
-    val out = Output(Vec(Const.NR_OF_PORTS, UInt(3.W)))
+    val out = Output(Vec(s4noc.Const.NR_OF_PORTS, UInt(3.W)))
   })
 
   // Just convert schedule table to a Chisel type table
   // unused slot is -1, convert to 0.U
-  val sched = Wire(Vec(schedule.length, Vec(Const.NR_OF_PORTS, UInt(3.W))))
+  val sched = Wire(Vec(schedule.length, Vec(s4noc.Const.NR_OF_PORTS, UInt(3.W))))
   for (i <- 0 until schedule.length) {
-    for (j <- 0 until Const.NR_OF_PORTS) {
+    for (j <- 0 until s4noc.Const.NR_OF_PORTS) {
       val s = schedule(i)(j)
-      val v = if (s == -1) Const.INVALID else s
+      val v = if (s == -1) s4noc.Const.INVALID else s
       sched(i)(j) := v.U(3.W)
     }
   }
 
   val currentSched = sched(io.in)
 
-  for (j <- 0 until Const.NR_OF_PORTS) {
+  for (j <- 0 until s4noc.Const.NR_OF_PORTS) {
     io.out(j) := currentSched(j)
   }
 }

src/main/scala/spi/SpiMaster.scala

@@ -2,7 +2,6 @@ package spi
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.ChiselEnum
 
 
 class SpiIO extends Bundle {

src/test/scala/s4noc/NetworkCompare.scala

@@ -13,7 +13,7 @@ import chiseltest._
 import org.scalatest.flatspec.AnyFlatSpec
 
 
-import Const._
+import s4noc.Const._
 
 /**
  * A manually connected 2x2 NoC for testing.