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LoongArchLSXInstrInfo.td
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//===- LoongArchLSXInstrInfo.td - LoongArch LSX instructions -*- tablegen -*-=//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file describes the SIMD extension instructions.
//
//===----------------------------------------------------------------------===//
def SDT_LoongArchVreplve : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
SDTCisInt<1>, SDTCisVec<1>,
SDTCisSameAs<0, 1>, SDTCisInt<2>]>;
def SDT_LoongArchVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
def SDT_LoongArchVShuf : SDTypeProfile<1, 3, [SDTCisVec<0>,
SDTCisInt<1>, SDTCisVec<1>,
SDTCisSameAs<0, 2>,
SDTCisSameAs<2, 3>]>;
def SDT_LoongArchV2R : SDTypeProfile<1, 2, [SDTCisVec<0>,
SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
def SDT_LoongArchV1RUimm: SDTypeProfile<1, 2, [SDTCisVec<0>,
SDTCisSameAs<0,1>, SDTCisVT<2, i64>]>;
def SDT_LoongArchVreplgr2vr : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<0>, SDTCisInt<1>]>;
def SDT_LoongArchVFRECIPE : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
def SDT_LoongArchVFRSQRTE : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
def SDT_LoongArchVLDREPL : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisPtrTy<1>]>;
// Target nodes.
def loongarch_vreplve : SDNode<"LoongArchISD::VREPLVE", SDT_LoongArchVreplve>;
def loongarch_vall_nonzero : SDNode<"LoongArchISD::VALL_NONZERO",
SDT_LoongArchVecCond>;
def loongarch_vany_nonzero : SDNode<"LoongArchISD::VANY_NONZERO",
SDT_LoongArchVecCond>;
def loongarch_vall_zero : SDNode<"LoongArchISD::VALL_ZERO",
SDT_LoongArchVecCond>;
def loongarch_vany_zero : SDNode<"LoongArchISD::VANY_ZERO",
SDT_LoongArchVecCond>;
def loongarch_vpick_sext_elt : SDNode<"LoongArchISD::VPICK_SEXT_ELT",
SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>>;
def loongarch_vpick_zext_elt : SDNode<"LoongArchISD::VPICK_ZEXT_ELT",
SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>>;
def loongarch_vshuf: SDNode<"LoongArchISD::VSHUF", SDT_LoongArchVShuf>;
def loongarch_vpickev: SDNode<"LoongArchISD::VPICKEV", SDT_LoongArchV2R>;
def loongarch_vpickod: SDNode<"LoongArchISD::VPICKOD", SDT_LoongArchV2R>;
def loongarch_vpackev: SDNode<"LoongArchISD::VPACKEV", SDT_LoongArchV2R>;
def loongarch_vpackod: SDNode<"LoongArchISD::VPACKOD", SDT_LoongArchV2R>;
def loongarch_vilvl: SDNode<"LoongArchISD::VILVL", SDT_LoongArchV2R>;
def loongarch_vilvh: SDNode<"LoongArchISD::VILVH", SDT_LoongArchV2R>;
def loongarch_vshuf4i: SDNode<"LoongArchISD::VSHUF4I", SDT_LoongArchV1RUimm>;
def loongarch_vreplvei: SDNode<"LoongArchISD::VREPLVEI", SDT_LoongArchV1RUimm>;
def loongarch_vreplgr2vr: SDNode<"LoongArchISD::VREPLGR2VR", SDT_LoongArchVreplgr2vr>;
def loongarch_vfrecipe: SDNode<"LoongArchISD::FRECIPE", SDT_LoongArchVFRECIPE>;
def loongarch_vfrsqrte: SDNode<"LoongArchISD::FRSQRTE", SDT_LoongArchVFRSQRTE>;
def loongarch_vslli : SDNode<"LoongArchISD::VSLLI", SDT_LoongArchV1RUimm>;
def loongarch_vsrli : SDNode<"LoongArchISD::VSRLI", SDT_LoongArchV1RUimm>;
def loongarch_vbsll : SDNode<"LoongArchISD::VBSLL", SDT_LoongArchV1RUimm>;
def loongarch_vbsrl : SDNode<"LoongArchISD::VBSRL", SDT_LoongArchV1RUimm>;
def loongarch_vldrepl
: SDNode<"LoongArchISD::VLDREPL",
SDT_LoongArchVLDREPL, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def immZExt1 : ImmLeaf<i64, [{return isUInt<1>(Imm);}]>;
def immZExt2 : ImmLeaf<i64, [{return isUInt<2>(Imm);}]>;
def immZExt3 : ImmLeaf<i64, [{return isUInt<3>(Imm);}]>;
def immZExt4 : ImmLeaf<i64, [{return isUInt<4>(Imm);}]>;
def immZExt8 : ImmLeaf<i64, [{return isUInt<8>(Imm);}]>;
class VecCond<SDPatternOperator OpNode, ValueType TyNode,
RegisterClass RC = LSX128>
: Pseudo<(outs GPR:$rd), (ins RC:$vj),
[(set GPR:$rd, (OpNode (TyNode RC:$vj)))]> {
let hasSideEffects = 0;
let mayLoad = 0;
let mayStore = 0;
let usesCustomInserter = 1;
}
def vsplat_imm_eq_1 : PatFrags<(ops), [(build_vector)], [{
APInt Imm;
EVT EltTy = N->getValueType(0).getVectorElementType();
if (N->getOpcode() == ISD::BITCAST)
N = N->getOperand(0).getNode();
return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&
Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
}]>;
def vsplati8_imm_eq_7 : PatFrags<(ops), [(build_vector)], [{
APInt Imm;
EVT EltTy = N->getValueType(0).getVectorElementType();
if (N->getOpcode() == ISD::BITCAST)
N = N->getOperand(0).getNode();
return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&
Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 7;
}]>;
def vsplati16_imm_eq_15 : PatFrags<(ops), [(build_vector)], [{
APInt Imm;
EVT EltTy = N->getValueType(0).getVectorElementType();
if (N->getOpcode() == ISD::BITCAST)
N = N->getOperand(0).getNode();
return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&
Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 15;
}]>;
def vsplati32_imm_eq_31 : PatFrags<(ops), [(build_vector)], [{
APInt Imm;
EVT EltTy = N->getValueType(0).getVectorElementType();
if (N->getOpcode() == ISD::BITCAST)
N = N->getOperand(0).getNode();
return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&
Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 31;
}]>;
def vsplati64_imm_eq_63 : PatFrags<(ops), [(build_vector)], [{
APInt Imm;
EVT EltTy = N->getValueType(0).getVectorElementType();
if (N->getOpcode() == ISD::BITCAST)
N = N->getOperand(0).getNode();
return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&
Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 63;
}]>;
def vsplatf32_fpimm_eq_1
: PatFrags<(ops), [(bitconvert (v4i32 (build_vector))),
(bitconvert (v8i32 (build_vector)))], [{
APInt Imm;
EVT EltTy = N->getValueType(0).getVectorElementType();
N = N->getOperand(0).getNode();
return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&
Imm.getBitWidth() == EltTy.getSizeInBits() &&
Imm == APFloat(+1.0f).bitcastToAPInt();
}]>;
def vsplatf64_fpimm_eq_1
: PatFrags<(ops), [(bitconvert (v2i64 (build_vector))),
(bitconvert (v4i64 (build_vector)))], [{
APInt Imm;
EVT EltTy = N->getValueType(0).getVectorElementType();
N = N->getOperand(0).getNode();
return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&
Imm.getBitWidth() == EltTy.getSizeInBits() &&
Imm == APFloat(+1.0).bitcastToAPInt();
}]>;
def vsplati8imm7 : PatFrag<(ops node:$reg),
(and node:$reg, vsplati8_imm_eq_7)>;
def vsplati16imm15 : PatFrag<(ops node:$reg),
(and node:$reg, vsplati16_imm_eq_15)>;
def vsplati32imm31 : PatFrag<(ops node:$reg),
(and node:$reg, vsplati32_imm_eq_31)>;
def vsplati64imm63 : PatFrag<(ops node:$reg),
(and node:$reg, vsplati64_imm_eq_63)>;
foreach N = [3, 4, 5, 6, 8] in
def SplatPat_uimm#N : ComplexPattern<vAny, 1, "selectVSplatImm<"#N#">",
[build_vector, bitconvert], [], 2>;
foreach N = [5] in
def SplatPat_simm#N : ComplexPattern<vAny, 1, "selectVSplatImm<"#N#", true>",
[build_vector, bitconvert]>;
def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2",
[build_vector, bitconvert]>;
def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2",
[build_vector, bitconvert]>;
def muladd : PatFrag<(ops node:$vd, node:$vj, node:$vk),
(add node:$vd, (mul node:$vj, node:$vk))>;
def mulsub : PatFrag<(ops node:$vd, node:$vj, node:$vk),
(sub node:$vd, (mul node:$vj, node:$vk))>;
def lsxsplati8 : PatFrag<(ops node:$e0),
(v16i8 (build_vector node:$e0, node:$e0,
node:$e0, node:$e0,
node:$e0, node:$e0,
node:$e0, node:$e0,
node:$e0, node:$e0,
node:$e0, node:$e0,
node:$e0, node:$e0,
node:$e0, node:$e0))>;
def lsxsplati16 : PatFrag<(ops node:$e0),
(v8i16 (build_vector node:$e0, node:$e0,
node:$e0, node:$e0,
node:$e0, node:$e0,
node:$e0, node:$e0))>;
def lsxsplati32 : PatFrag<(ops node:$e0),
(v4i32 (build_vector node:$e0, node:$e0,
node:$e0, node:$e0))>;
def lsxsplati64 : PatFrag<(ops node:$e0),
(v2i64 (build_vector node:$e0, node:$e0))>;
def lsxsplatf32 : PatFrag<(ops node:$e0),
(v4f32 (build_vector node:$e0, node:$e0,
node:$e0, node:$e0))>;
def lsxsplatf64 : PatFrag<(ops node:$e0),
(v2f64 (build_vector node:$e0, node:$e0))>;
def to_valid_timm : SDNodeXForm<timm, [{
auto CN = cast<ConstantSDNode>(N);
return CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(N), Subtarget->getGRLenVT());
}]>;
// FP immediate of VLDI patterns.
def f32imm_vldi : PatLeaf<(fpimm), [{
const auto &TLI =
*static_cast<const LoongArchTargetLowering*>(getTargetLowering());
return TLI.isFPImmVLDILegal(N->getValueAPF(), MVT::f32);
}]>;
def f64imm_vldi : PatLeaf<(fpimm), [{
const auto &TLI =
*static_cast<const LoongArchTargetLowering*>(getTargetLowering());
return TLI.isFPImmVLDILegal(N->getValueAPF(), MVT::f64);
}]>;
def to_f32imm_vldi : SDNodeXForm<fpimm, [{
uint64_t x = N->getValueAPF().bitcastToAPInt().getZExtValue();
x = (0b11011 << 8) | (((x >> 24) & 0xc0) ^ 0x40) | ((x >> 19) & 0x3f);
return CurDAG->getSignedTargetConstant(SignExtend32<13>(x), SDLoc(N),
MVT::i32);
}]>;
def to_f64imm_vldi : SDNodeXForm<fpimm, [{
uint64_t x = N->getValueAPF().bitcastToAPInt().getZExtValue();
x = (0b11100 << 8) | (((x >> 56) & 0xc0) ^ 0x40) | ((x >> 48) & 0x3f);
return CurDAG->getSignedTargetConstant(SignExtend32<13>(x), SDLoc(N),
MVT::i32);
}]>;
//===----------------------------------------------------------------------===//
// Instruction class templates
//===----------------------------------------------------------------------===//
class LSX1RI13_VI<bits<32> op, Operand ImmOpnd = simm13>
: Fmt1RI13_VI<op, (outs LSX128:$vd), (ins ImmOpnd:$imm13), "$vd, $imm13">;
class LSX2R_VV<bits<32> op>
: Fmt2R_VV<op, (outs LSX128:$vd), (ins LSX128:$vj), "$vd, $vj">;
class LSX2R_VR<bits<32> op>
: Fmt2R_VR<op, (outs LSX128:$vd), (ins GPR:$rj), "$vd, $rj">;
class LSX2R_CV<bits<32> op>
: Fmt2R_CV<op, (outs CFR:$cd), (ins LSX128:$vj), "$cd, $vj">;
class LSX2RI1_VVI<bits<32> op, Operand ImmOpnd = uimm1>
: Fmt2RI1_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm1),
"$vd, $vj, $imm1">;
class LSX2RI1_RVI<bits<32> op, Operand ImmOpnd = uimm1>
: Fmt2RI1_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm1),
"$rd, $vj, $imm1">;
class LSX2RI2_VVI<bits<32> op, Operand ImmOpnd = uimm2>
: Fmt2RI2_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm2),
"$vd, $vj, $imm2">;
class LSX2RI2_RVI<bits<32> op, Operand ImmOpnd = uimm2>
: Fmt2RI2_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm2),
"$rd, $vj, $imm2">;
class LSX2RI3_VVI<bits<32> op, Operand ImmOpnd = uimm3>
: Fmt2RI3_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm3),
"$vd, $vj, $imm3">;
class LSX2RI3_RVI<bits<32> op, Operand ImmOpnd = uimm3>
: Fmt2RI3_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm3),
"$rd, $vj, $imm3">;
class LSX2RI4_VVI<bits<32> op, Operand ImmOpnd = uimm4>
: Fmt2RI4_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm4),
"$vd, $vj, $imm4">;
class LSX2RI4_RVI<bits<32> op, Operand ImmOpnd = uimm4>
: Fmt2RI4_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm4),
"$rd, $vj, $imm4">;
class LSX2RI5_VVI<bits<32> op, Operand ImmOpnd = uimm5>
: Fmt2RI5_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm5),
"$vd, $vj, $imm5">;
class LSX2RI6_VVI<bits<32> op, Operand ImmOpnd = uimm6>
: Fmt2RI6_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm6),
"$vd, $vj, $imm6">;
class LSX2RI8_VVI<bits<32> op, Operand ImmOpnd = uimm8>
: Fmt2RI8_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm8),
"$vd, $vj, $imm8">;
class LSX2RI8I1_VRII<bits<32> op, Operand ImmOpnd = simm8,
Operand IdxOpnd = uimm1>
: Fmt2RI8I1_VRII<op, (outs),
(ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm1),
"$vd, $rj, $imm8, $imm1">;
class LSX2RI8I2_VRII<bits<32> op, Operand ImmOpnd = simm8,
Operand IdxOpnd = uimm2>
: Fmt2RI8I2_VRII<op, (outs),
(ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm2),
"$vd, $rj, $imm8, $imm2">;
class LSX2RI8I3_VRII<bits<32> op, Operand ImmOpnd = simm8,
Operand IdxOpnd = uimm3>
: Fmt2RI8I3_VRII<op, (outs),
(ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm3),
"$vd, $rj, $imm8, $imm3">;
class LSX2RI8I4_VRII<bits<32> op, Operand ImmOpnd = simm8,
Operand IdxOpnd = uimm4>
: Fmt2RI8I4_VRII<op, (outs),
(ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm4),
"$vd, $rj, $imm8, $imm4">;
class LSX3R_VVV<bits<32> op>
: Fmt3R_VVV<op, (outs LSX128:$vd), (ins LSX128:$vj, LSX128:$vk),
"$vd, $vj, $vk">;
class LSX3R_VVR<bits<32> op>
: Fmt3R_VVR<op, (outs LSX128:$vd), (ins LSX128:$vj, GPR:$rk),
"$vd, $vj, $rk">;
class LSX4R_VVVV<bits<32> op>
: Fmt4R_VVVV<op, (outs LSX128:$vd),
(ins LSX128:$vj, LSX128:$vk, LSX128:$va),
"$vd, $vj, $vk, $va">;
let Constraints = "$vd = $dst" in {
class LSX2RI1_VVRI<bits<32> op, Operand ImmOpnd = uimm1>
: Fmt2RI1_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm1),
"$vd, $rj, $imm1">;
class LSX2RI2_VVRI<bits<32> op, Operand ImmOpnd = uimm2>
: Fmt2RI2_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm2),
"$vd, $rj, $imm2">;
class LSX2RI3_VVRI<bits<32> op, Operand ImmOpnd = uimm3>
: Fmt2RI3_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm3),
"$vd, $rj, $imm3">;
class LSX2RI4_VVRI<bits<32> op, Operand ImmOpnd = uimm4>
: Fmt2RI4_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm4),
"$vd, $rj, $imm4">;
class LSX2RI4_VVVI<bits<32> op, Operand ImmOpnd = uimm4>
: Fmt2RI4_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm4),
"$vd, $vj, $imm4">;
class LSX2RI5_VVVI<bits<32> op, Operand ImmOpnd = uimm5>
: Fmt2RI5_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm5),
"$vd, $vj, $imm5">;
class LSX2RI6_VVVI<bits<32> op, Operand ImmOpnd = uimm6>
: Fmt2RI6_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm6),
"$vd, $vj, $imm6">;
class LSX2RI7_VVVI<bits<32> op, Operand ImmOpnd = uimm7>
: Fmt2RI7_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm7),
"$vd, $vj, $imm7">;
class LSX2RI8_VVVI<bits<32> op, Operand ImmOpnd = uimm8>
: Fmt2RI8_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm8),
"$vd, $vj, $imm8">;
class LSX3R_VVVV<bits<32> op>
: Fmt3R_VVV<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, LSX128:$vk),
"$vd, $vj, $vk">;
} // Constraints = "$vd = $dst"
class LSX2RI9_Load<bits<32> op, Operand ImmOpnd = simm9_lsl3>
: Fmt2RI9_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm9),
"$vd, $rj, $imm9">;
class LSX2RI10_Load<bits<32> op, Operand ImmOpnd = simm10_lsl2>
: Fmt2RI10_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm10),
"$vd, $rj, $imm10">;
class LSX2RI11_Load<bits<32> op, Operand ImmOpnd = simm11_lsl1>
: Fmt2RI11_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm11),
"$vd, $rj, $imm11">;
class LSX2RI12_Load<bits<32> op, Operand ImmOpnd = simm12_addlike>
: Fmt2RI12_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm12),
"$vd, $rj, $imm12">;
class LSX2RI12_Store<bits<32> op, Operand ImmOpnd = simm12_addlike>
: Fmt2RI12_VRI<op, (outs), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm12),
"$vd, $rj, $imm12">;
class LSX3R_Load<bits<32> op>
: Fmt3R_VRR<op, (outs LSX128:$vd), (ins GPR:$rj, GPR:$rk),
"$vd, $rj, $rk">;
class LSX3R_Store<bits<32> op>
: Fmt3R_VRR<op, (outs), (ins LSX128:$vd, GPR:$rj, GPR:$rk),
"$vd, $rj, $rk">;
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
let hasSideEffects = 0, Predicates = [HasExtLSX] in {
let mayLoad = 0, mayStore = 0 in {
def VADD_B : LSX3R_VVV<0x700a0000>;
def VADD_H : LSX3R_VVV<0x700a8000>;
def VADD_W : LSX3R_VVV<0x700b0000>;
def VADD_D : LSX3R_VVV<0x700b8000>;
def VADD_Q : LSX3R_VVV<0x712d0000>;
def VSUB_B : LSX3R_VVV<0x700c0000>;
def VSUB_H : LSX3R_VVV<0x700c8000>;
def VSUB_W : LSX3R_VVV<0x700d0000>;
def VSUB_D : LSX3R_VVV<0x700d8000>;
def VSUB_Q : LSX3R_VVV<0x712d8000>;
def VADDI_BU : LSX2RI5_VVI<0x728a0000>;
def VADDI_HU : LSX2RI5_VVI<0x728a8000>;
def VADDI_WU : LSX2RI5_VVI<0x728b0000>;
def VADDI_DU : LSX2RI5_VVI<0x728b8000>;
def VSUBI_BU : LSX2RI5_VVI<0x728c0000>;
def VSUBI_HU : LSX2RI5_VVI<0x728c8000>;
def VSUBI_WU : LSX2RI5_VVI<0x728d0000>;
def VSUBI_DU : LSX2RI5_VVI<0x728d8000>;
def VNEG_B : LSX2R_VV<0x729c3000>;
def VNEG_H : LSX2R_VV<0x729c3400>;
def VNEG_W : LSX2R_VV<0x729c3800>;
def VNEG_D : LSX2R_VV<0x729c3c00>;
def VSADD_B : LSX3R_VVV<0x70460000>;
def VSADD_H : LSX3R_VVV<0x70468000>;
def VSADD_W : LSX3R_VVV<0x70470000>;
def VSADD_D : LSX3R_VVV<0x70478000>;
def VSADD_BU : LSX3R_VVV<0x704a0000>;
def VSADD_HU : LSX3R_VVV<0x704a8000>;
def VSADD_WU : LSX3R_VVV<0x704b0000>;
def VSADD_DU : LSX3R_VVV<0x704b8000>;
def VSSUB_B : LSX3R_VVV<0x70480000>;
def VSSUB_H : LSX3R_VVV<0x70488000>;
def VSSUB_W : LSX3R_VVV<0x70490000>;
def VSSUB_D : LSX3R_VVV<0x70498000>;
def VSSUB_BU : LSX3R_VVV<0x704c0000>;
def VSSUB_HU : LSX3R_VVV<0x704c8000>;
def VSSUB_WU : LSX3R_VVV<0x704d0000>;
def VSSUB_DU : LSX3R_VVV<0x704d8000>;
def VHADDW_H_B : LSX3R_VVV<0x70540000>;
def VHADDW_W_H : LSX3R_VVV<0x70548000>;
def VHADDW_D_W : LSX3R_VVV<0x70550000>;
def VHADDW_Q_D : LSX3R_VVV<0x70558000>;
def VHADDW_HU_BU : LSX3R_VVV<0x70580000>;
def VHADDW_WU_HU : LSX3R_VVV<0x70588000>;
def VHADDW_DU_WU : LSX3R_VVV<0x70590000>;
def VHADDW_QU_DU : LSX3R_VVV<0x70598000>;
def VHSUBW_H_B : LSX3R_VVV<0x70560000>;
def VHSUBW_W_H : LSX3R_VVV<0x70568000>;
def VHSUBW_D_W : LSX3R_VVV<0x70570000>;
def VHSUBW_Q_D : LSX3R_VVV<0x70578000>;
def VHSUBW_HU_BU : LSX3R_VVV<0x705a0000>;
def VHSUBW_WU_HU : LSX3R_VVV<0x705a8000>;
def VHSUBW_DU_WU : LSX3R_VVV<0x705b0000>;
def VHSUBW_QU_DU : LSX3R_VVV<0x705b8000>;
def VADDWEV_H_B : LSX3R_VVV<0x701e0000>;
def VADDWEV_W_H : LSX3R_VVV<0x701e8000>;
def VADDWEV_D_W : LSX3R_VVV<0x701f0000>;
def VADDWEV_Q_D : LSX3R_VVV<0x701f8000>;
def VADDWOD_H_B : LSX3R_VVV<0x70220000>;
def VADDWOD_W_H : LSX3R_VVV<0x70228000>;
def VADDWOD_D_W : LSX3R_VVV<0x70230000>;
def VADDWOD_Q_D : LSX3R_VVV<0x70238000>;
def VSUBWEV_H_B : LSX3R_VVV<0x70200000>;
def VSUBWEV_W_H : LSX3R_VVV<0x70208000>;
def VSUBWEV_D_W : LSX3R_VVV<0x70210000>;
def VSUBWEV_Q_D : LSX3R_VVV<0x70218000>;
def VSUBWOD_H_B : LSX3R_VVV<0x70240000>;
def VSUBWOD_W_H : LSX3R_VVV<0x70248000>;
def VSUBWOD_D_W : LSX3R_VVV<0x70250000>;
def VSUBWOD_Q_D : LSX3R_VVV<0x70258000>;
def VADDWEV_H_BU : LSX3R_VVV<0x702e0000>;
def VADDWEV_W_HU : LSX3R_VVV<0x702e8000>;
def VADDWEV_D_WU : LSX3R_VVV<0x702f0000>;
def VADDWEV_Q_DU : LSX3R_VVV<0x702f8000>;
def VADDWOD_H_BU : LSX3R_VVV<0x70320000>;
def VADDWOD_W_HU : LSX3R_VVV<0x70328000>;
def VADDWOD_D_WU : LSX3R_VVV<0x70330000>;
def VADDWOD_Q_DU : LSX3R_VVV<0x70338000>;
def VSUBWEV_H_BU : LSX3R_VVV<0x70300000>;
def VSUBWEV_W_HU : LSX3R_VVV<0x70308000>;
def VSUBWEV_D_WU : LSX3R_VVV<0x70310000>;
def VSUBWEV_Q_DU : LSX3R_VVV<0x70318000>;
def VSUBWOD_H_BU : LSX3R_VVV<0x70340000>;
def VSUBWOD_W_HU : LSX3R_VVV<0x70348000>;
def VSUBWOD_D_WU : LSX3R_VVV<0x70350000>;
def VSUBWOD_Q_DU : LSX3R_VVV<0x70358000>;
def VADDWEV_H_BU_B : LSX3R_VVV<0x703e0000>;
def VADDWEV_W_HU_H : LSX3R_VVV<0x703e8000>;
def VADDWEV_D_WU_W : LSX3R_VVV<0x703f0000>;
def VADDWEV_Q_DU_D : LSX3R_VVV<0x703f8000>;
def VADDWOD_H_BU_B : LSX3R_VVV<0x70400000>;
def VADDWOD_W_HU_H : LSX3R_VVV<0x70408000>;
def VADDWOD_D_WU_W : LSX3R_VVV<0x70410000>;
def VADDWOD_Q_DU_D : LSX3R_VVV<0x70418000>;
def VAVG_B : LSX3R_VVV<0x70640000>;
def VAVG_H : LSX3R_VVV<0x70648000>;
def VAVG_W : LSX3R_VVV<0x70650000>;
def VAVG_D : LSX3R_VVV<0x70658000>;
def VAVG_BU : LSX3R_VVV<0x70660000>;
def VAVG_HU : LSX3R_VVV<0x70668000>;
def VAVG_WU : LSX3R_VVV<0x70670000>;
def VAVG_DU : LSX3R_VVV<0x70678000>;
def VAVGR_B : LSX3R_VVV<0x70680000>;
def VAVGR_H : LSX3R_VVV<0x70688000>;
def VAVGR_W : LSX3R_VVV<0x70690000>;
def VAVGR_D : LSX3R_VVV<0x70698000>;
def VAVGR_BU : LSX3R_VVV<0x706a0000>;
def VAVGR_HU : LSX3R_VVV<0x706a8000>;
def VAVGR_WU : LSX3R_VVV<0x706b0000>;
def VAVGR_DU : LSX3R_VVV<0x706b8000>;
def VABSD_B : LSX3R_VVV<0x70600000>;
def VABSD_H : LSX3R_VVV<0x70608000>;
def VABSD_W : LSX3R_VVV<0x70610000>;
def VABSD_D : LSX3R_VVV<0x70618000>;
def VABSD_BU : LSX3R_VVV<0x70620000>;
def VABSD_HU : LSX3R_VVV<0x70628000>;
def VABSD_WU : LSX3R_VVV<0x70630000>;
def VABSD_DU : LSX3R_VVV<0x70638000>;
def VADDA_B : LSX3R_VVV<0x705c0000>;
def VADDA_H : LSX3R_VVV<0x705c8000>;
def VADDA_W : LSX3R_VVV<0x705d0000>;
def VADDA_D : LSX3R_VVV<0x705d8000>;
def VMAX_B : LSX3R_VVV<0x70700000>;
def VMAX_H : LSX3R_VVV<0x70708000>;
def VMAX_W : LSX3R_VVV<0x70710000>;
def VMAX_D : LSX3R_VVV<0x70718000>;
def VMAXI_B : LSX2RI5_VVI<0x72900000, simm5>;
def VMAXI_H : LSX2RI5_VVI<0x72908000, simm5>;
def VMAXI_W : LSX2RI5_VVI<0x72910000, simm5>;
def VMAXI_D : LSX2RI5_VVI<0x72918000, simm5>;
def VMAX_BU : LSX3R_VVV<0x70740000>;
def VMAX_HU : LSX3R_VVV<0x70748000>;
def VMAX_WU : LSX3R_VVV<0x70750000>;
def VMAX_DU : LSX3R_VVV<0x70758000>;
def VMAXI_BU : LSX2RI5_VVI<0x72940000>;
def VMAXI_HU : LSX2RI5_VVI<0x72948000>;
def VMAXI_WU : LSX2RI5_VVI<0x72950000>;
def VMAXI_DU : LSX2RI5_VVI<0x72958000>;
def VMIN_B : LSX3R_VVV<0x70720000>;
def VMIN_H : LSX3R_VVV<0x70728000>;
def VMIN_W : LSX3R_VVV<0x70730000>;
def VMIN_D : LSX3R_VVV<0x70738000>;
def VMINI_B : LSX2RI5_VVI<0x72920000, simm5>;
def VMINI_H : LSX2RI5_VVI<0x72928000, simm5>;
def VMINI_W : LSX2RI5_VVI<0x72930000, simm5>;
def VMINI_D : LSX2RI5_VVI<0x72938000, simm5>;
def VMIN_BU : LSX3R_VVV<0x70760000>;
def VMIN_HU : LSX3R_VVV<0x70768000>;
def VMIN_WU : LSX3R_VVV<0x70770000>;
def VMIN_DU : LSX3R_VVV<0x70778000>;
def VMINI_BU : LSX2RI5_VVI<0x72960000>;
def VMINI_HU : LSX2RI5_VVI<0x72968000>;
def VMINI_WU : LSX2RI5_VVI<0x72970000>;
def VMINI_DU : LSX2RI5_VVI<0x72978000>;
def VMUL_B : LSX3R_VVV<0x70840000>;
def VMUL_H : LSX3R_VVV<0x70848000>;
def VMUL_W : LSX3R_VVV<0x70850000>;
def VMUL_D : LSX3R_VVV<0x70858000>;
def VMUH_B : LSX3R_VVV<0x70860000>;
def VMUH_H : LSX3R_VVV<0x70868000>;
def VMUH_W : LSX3R_VVV<0x70870000>;
def VMUH_D : LSX3R_VVV<0x70878000>;
def VMUH_BU : LSX3R_VVV<0x70880000>;
def VMUH_HU : LSX3R_VVV<0x70888000>;
def VMUH_WU : LSX3R_VVV<0x70890000>;
def VMUH_DU : LSX3R_VVV<0x70898000>;
def VMULWEV_H_B : LSX3R_VVV<0x70900000>;
def VMULWEV_W_H : LSX3R_VVV<0x70908000>;
def VMULWEV_D_W : LSX3R_VVV<0x70910000>;
def VMULWEV_Q_D : LSX3R_VVV<0x70918000>;
def VMULWOD_H_B : LSX3R_VVV<0x70920000>;
def VMULWOD_W_H : LSX3R_VVV<0x70928000>;
def VMULWOD_D_W : LSX3R_VVV<0x70930000>;
def VMULWOD_Q_D : LSX3R_VVV<0x70938000>;
def VMULWEV_H_BU : LSX3R_VVV<0x70980000>;
def VMULWEV_W_HU : LSX3R_VVV<0x70988000>;
def VMULWEV_D_WU : LSX3R_VVV<0x70990000>;
def VMULWEV_Q_DU : LSX3R_VVV<0x70998000>;
def VMULWOD_H_BU : LSX3R_VVV<0x709a0000>;
def VMULWOD_W_HU : LSX3R_VVV<0x709a8000>;
def VMULWOD_D_WU : LSX3R_VVV<0x709b0000>;
def VMULWOD_Q_DU : LSX3R_VVV<0x709b8000>;
def VMULWEV_H_BU_B : LSX3R_VVV<0x70a00000>;
def VMULWEV_W_HU_H : LSX3R_VVV<0x70a08000>;
def VMULWEV_D_WU_W : LSX3R_VVV<0x70a10000>;
def VMULWEV_Q_DU_D : LSX3R_VVV<0x70a18000>;
def VMULWOD_H_BU_B : LSX3R_VVV<0x70a20000>;
def VMULWOD_W_HU_H : LSX3R_VVV<0x70a28000>;
def VMULWOD_D_WU_W : LSX3R_VVV<0x70a30000>;
def VMULWOD_Q_DU_D : LSX3R_VVV<0x70a38000>;
def VMADD_B : LSX3R_VVVV<0x70a80000>;
def VMADD_H : LSX3R_VVVV<0x70a88000>;
def VMADD_W : LSX3R_VVVV<0x70a90000>;
def VMADD_D : LSX3R_VVVV<0x70a98000>;
def VMSUB_B : LSX3R_VVVV<0x70aa0000>;
def VMSUB_H : LSX3R_VVVV<0x70aa8000>;
def VMSUB_W : LSX3R_VVVV<0x70ab0000>;
def VMSUB_D : LSX3R_VVVV<0x70ab8000>;
def VMADDWEV_H_B : LSX3R_VVVV<0x70ac0000>;
def VMADDWEV_W_H : LSX3R_VVVV<0x70ac8000>;
def VMADDWEV_D_W : LSX3R_VVVV<0x70ad0000>;
def VMADDWEV_Q_D : LSX3R_VVVV<0x70ad8000>;
def VMADDWOD_H_B : LSX3R_VVVV<0x70ae0000>;
def VMADDWOD_W_H : LSX3R_VVVV<0x70ae8000>;
def VMADDWOD_D_W : LSX3R_VVVV<0x70af0000>;
def VMADDWOD_Q_D : LSX3R_VVVV<0x70af8000>;
def VMADDWEV_H_BU : LSX3R_VVVV<0x70b40000>;
def VMADDWEV_W_HU : LSX3R_VVVV<0x70b48000>;
def VMADDWEV_D_WU : LSX3R_VVVV<0x70b50000>;
def VMADDWEV_Q_DU : LSX3R_VVVV<0x70b58000>;
def VMADDWOD_H_BU : LSX3R_VVVV<0x70b60000>;
def VMADDWOD_W_HU : LSX3R_VVVV<0x70b68000>;
def VMADDWOD_D_WU : LSX3R_VVVV<0x70b70000>;
def VMADDWOD_Q_DU : LSX3R_VVVV<0x70b78000>;
def VMADDWEV_H_BU_B : LSX3R_VVVV<0x70bc0000>;
def VMADDWEV_W_HU_H : LSX3R_VVVV<0x70bc8000>;
def VMADDWEV_D_WU_W : LSX3R_VVVV<0x70bd0000>;
def VMADDWEV_Q_DU_D : LSX3R_VVVV<0x70bd8000>;
def VMADDWOD_H_BU_B : LSX3R_VVVV<0x70be0000>;
def VMADDWOD_W_HU_H : LSX3R_VVVV<0x70be8000>;
def VMADDWOD_D_WU_W : LSX3R_VVVV<0x70bf0000>;
def VMADDWOD_Q_DU_D : LSX3R_VVVV<0x70bf8000>;
def VDIV_B : LSX3R_VVV<0x70e00000>;
def VDIV_H : LSX3R_VVV<0x70e08000>;
def VDIV_W : LSX3R_VVV<0x70e10000>;
def VDIV_D : LSX3R_VVV<0x70e18000>;
def VDIV_BU : LSX3R_VVV<0x70e40000>;
def VDIV_HU : LSX3R_VVV<0x70e48000>;
def VDIV_WU : LSX3R_VVV<0x70e50000>;
def VDIV_DU : LSX3R_VVV<0x70e58000>;
def VMOD_B : LSX3R_VVV<0x70e20000>;
def VMOD_H : LSX3R_VVV<0x70e28000>;
def VMOD_W : LSX3R_VVV<0x70e30000>;
def VMOD_D : LSX3R_VVV<0x70e38000>;
def VMOD_BU : LSX3R_VVV<0x70e60000>;
def VMOD_HU : LSX3R_VVV<0x70e68000>;
def VMOD_WU : LSX3R_VVV<0x70e70000>;
def VMOD_DU : LSX3R_VVV<0x70e78000>;
def VSAT_B : LSX2RI3_VVI<0x73242000>;
def VSAT_H : LSX2RI4_VVI<0x73244000>;
def VSAT_W : LSX2RI5_VVI<0x73248000>;
def VSAT_D : LSX2RI6_VVI<0x73250000>;
def VSAT_BU : LSX2RI3_VVI<0x73282000>;
def VSAT_HU : LSX2RI4_VVI<0x73284000>;
def VSAT_WU : LSX2RI5_VVI<0x73288000>;
def VSAT_DU : LSX2RI6_VVI<0x73290000>;
def VEXTH_H_B : LSX2R_VV<0x729ee000>;
def VEXTH_W_H : LSX2R_VV<0x729ee400>;
def VEXTH_D_W : LSX2R_VV<0x729ee800>;
def VEXTH_Q_D : LSX2R_VV<0x729eec00>;
def VEXTH_HU_BU : LSX2R_VV<0x729ef000>;
def VEXTH_WU_HU : LSX2R_VV<0x729ef400>;
def VEXTH_DU_WU : LSX2R_VV<0x729ef800>;
def VEXTH_QU_DU : LSX2R_VV<0x729efc00>;
def VSIGNCOV_B : LSX3R_VVV<0x712e0000>;
def VSIGNCOV_H : LSX3R_VVV<0x712e8000>;
def VSIGNCOV_W : LSX3R_VVV<0x712f0000>;
def VSIGNCOV_D : LSX3R_VVV<0x712f8000>;
def VMSKLTZ_B : LSX2R_VV<0x729c4000>;
def VMSKLTZ_H : LSX2R_VV<0x729c4400>;
def VMSKLTZ_W : LSX2R_VV<0x729c4800>;
def VMSKLTZ_D : LSX2R_VV<0x729c4c00>;
def VMSKGEZ_B : LSX2R_VV<0x729c5000>;
def VMSKNZ_B : LSX2R_VV<0x729c6000>;
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
def VLDI : LSX1RI13_VI<0x73e00000>;
}
def VAND_V : LSX3R_VVV<0x71260000>;
def VOR_V : LSX3R_VVV<0x71268000>;
def VXOR_V : LSX3R_VVV<0x71270000>;
def VNOR_V : LSX3R_VVV<0x71278000>;
def VANDN_V : LSX3R_VVV<0x71280000>;
def VORN_V : LSX3R_VVV<0x71288000>;
def VANDI_B : LSX2RI8_VVI<0x73d00000>;
def VORI_B : LSX2RI8_VVI<0x73d40000>;
def VXORI_B : LSX2RI8_VVI<0x73d80000>;
def VNORI_B : LSX2RI8_VVI<0x73dc0000>;
def VSLL_B : LSX3R_VVV<0x70e80000>;
def VSLL_H : LSX3R_VVV<0x70e88000>;
def VSLL_W : LSX3R_VVV<0x70e90000>;
def VSLL_D : LSX3R_VVV<0x70e98000>;
def VSLLI_B : LSX2RI3_VVI<0x732c2000>;
def VSLLI_H : LSX2RI4_VVI<0x732c4000>;
def VSLLI_W : LSX2RI5_VVI<0x732c8000>;
def VSLLI_D : LSX2RI6_VVI<0x732d0000>;
def VSRL_B : LSX3R_VVV<0x70ea0000>;
def VSRL_H : LSX3R_VVV<0x70ea8000>;
def VSRL_W : LSX3R_VVV<0x70eb0000>;
def VSRL_D : LSX3R_VVV<0x70eb8000>;
def VSRLI_B : LSX2RI3_VVI<0x73302000>;
def VSRLI_H : LSX2RI4_VVI<0x73304000>;
def VSRLI_W : LSX2RI5_VVI<0x73308000>;
def VSRLI_D : LSX2RI6_VVI<0x73310000>;
def VSRA_B : LSX3R_VVV<0x70ec0000>;
def VSRA_H : LSX3R_VVV<0x70ec8000>;
def VSRA_W : LSX3R_VVV<0x70ed0000>;
def VSRA_D : LSX3R_VVV<0x70ed8000>;
def VSRAI_B : LSX2RI3_VVI<0x73342000>;
def VSRAI_H : LSX2RI4_VVI<0x73344000>;
def VSRAI_W : LSX2RI5_VVI<0x73348000>;
def VSRAI_D : LSX2RI6_VVI<0x73350000>;
def VROTR_B : LSX3R_VVV<0x70ee0000>;
def VROTR_H : LSX3R_VVV<0x70ee8000>;
def VROTR_W : LSX3R_VVV<0x70ef0000>;
def VROTR_D : LSX3R_VVV<0x70ef8000>;
def VROTRI_B : LSX2RI3_VVI<0x72a02000>;
def VROTRI_H : LSX2RI4_VVI<0x72a04000>;
def VROTRI_W : LSX2RI5_VVI<0x72a08000>;
def VROTRI_D : LSX2RI6_VVI<0x72a10000>;
def VSLLWIL_H_B : LSX2RI3_VVI<0x73082000>;
def VSLLWIL_W_H : LSX2RI4_VVI<0x73084000>;
def VSLLWIL_D_W : LSX2RI5_VVI<0x73088000>;
def VEXTL_Q_D : LSX2R_VV<0x73090000>;
def VSLLWIL_HU_BU : LSX2RI3_VVI<0x730c2000>;
def VSLLWIL_WU_HU : LSX2RI4_VVI<0x730c4000>;
def VSLLWIL_DU_WU : LSX2RI5_VVI<0x730c8000>;
def VEXTL_QU_DU : LSX2R_VV<0x730d0000>;
def VSRLR_B : LSX3R_VVV<0x70f00000>;
def VSRLR_H : LSX3R_VVV<0x70f08000>;
def VSRLR_W : LSX3R_VVV<0x70f10000>;
def VSRLR_D : LSX3R_VVV<0x70f18000>;
def VSRLRI_B : LSX2RI3_VVI<0x72a42000>;
def VSRLRI_H : LSX2RI4_VVI<0x72a44000>;
def VSRLRI_W : LSX2RI5_VVI<0x72a48000>;
def VSRLRI_D : LSX2RI6_VVI<0x72a50000>;
def VSRAR_B : LSX3R_VVV<0x70f20000>;
def VSRAR_H : LSX3R_VVV<0x70f28000>;
def VSRAR_W : LSX3R_VVV<0x70f30000>;
def VSRAR_D : LSX3R_VVV<0x70f38000>;
def VSRARI_B : LSX2RI3_VVI<0x72a82000>;
def VSRARI_H : LSX2RI4_VVI<0x72a84000>;
def VSRARI_W : LSX2RI5_VVI<0x72a88000>;
def VSRARI_D : LSX2RI6_VVI<0x72a90000>;
def VSRLN_B_H : LSX3R_VVV<0x70f48000>;
def VSRLN_H_W : LSX3R_VVV<0x70f50000>;
def VSRLN_W_D : LSX3R_VVV<0x70f58000>;
def VSRAN_B_H : LSX3R_VVV<0x70f68000>;
def VSRAN_H_W : LSX3R_VVV<0x70f70000>;
def VSRAN_W_D : LSX3R_VVV<0x70f78000>;
def VSRLNI_B_H : LSX2RI4_VVVI<0x73404000>;
def VSRLNI_H_W : LSX2RI5_VVVI<0x73408000>;
def VSRLNI_W_D : LSX2RI6_VVVI<0x73410000>;
def VSRLNI_D_Q : LSX2RI7_VVVI<0x73420000>;
def VSRANI_B_H : LSX2RI4_VVVI<0x73584000>;
def VSRANI_H_W : LSX2RI5_VVVI<0x73588000>;
def VSRANI_W_D : LSX2RI6_VVVI<0x73590000>;
def VSRANI_D_Q : LSX2RI7_VVVI<0x735a0000>;
def VSRLRN_B_H : LSX3R_VVV<0x70f88000>;
def VSRLRN_H_W : LSX3R_VVV<0x70f90000>;
def VSRLRN_W_D : LSX3R_VVV<0x70f98000>;
def VSRARN_B_H : LSX3R_VVV<0x70fa8000>;
def VSRARN_H_W : LSX3R_VVV<0x70fb0000>;
def VSRARN_W_D : LSX3R_VVV<0x70fb8000>;
def VSRLRNI_B_H : LSX2RI4_VVVI<0x73444000>;
def VSRLRNI_H_W : LSX2RI5_VVVI<0x73448000>;
def VSRLRNI_W_D : LSX2RI6_VVVI<0x73450000>;
def VSRLRNI_D_Q : LSX2RI7_VVVI<0x73460000>;
def VSRARNI_B_H : LSX2RI4_VVVI<0x735c4000>;
def VSRARNI_H_W : LSX2RI5_VVVI<0x735c8000>;
def VSRARNI_W_D : LSX2RI6_VVVI<0x735d0000>;
def VSRARNI_D_Q : LSX2RI7_VVVI<0x735e0000>;
def VSSRLN_B_H : LSX3R_VVV<0x70fc8000>;
def VSSRLN_H_W : LSX3R_VVV<0x70fd0000>;
def VSSRLN_W_D : LSX3R_VVV<0x70fd8000>;
def VSSRAN_B_H : LSX3R_VVV<0x70fe8000>;
def VSSRAN_H_W : LSX3R_VVV<0x70ff0000>;
def VSSRAN_W_D : LSX3R_VVV<0x70ff8000>;
def VSSRLN_BU_H : LSX3R_VVV<0x71048000>;
def VSSRLN_HU_W : LSX3R_VVV<0x71050000>;
def VSSRLN_WU_D : LSX3R_VVV<0x71058000>;
def VSSRAN_BU_H : LSX3R_VVV<0x71068000>;
def VSSRAN_HU_W : LSX3R_VVV<0x71070000>;
def VSSRAN_WU_D : LSX3R_VVV<0x71078000>;
def VSSRLNI_B_H : LSX2RI4_VVVI<0x73484000>;
def VSSRLNI_H_W : LSX2RI5_VVVI<0x73488000>;
def VSSRLNI_W_D : LSX2RI6_VVVI<0x73490000>;
def VSSRLNI_D_Q : LSX2RI7_VVVI<0x734a0000>;
def VSSRANI_B_H : LSX2RI4_VVVI<0x73604000>;
def VSSRANI_H_W : LSX2RI5_VVVI<0x73608000>;
def VSSRANI_W_D : LSX2RI6_VVVI<0x73610000>;
def VSSRANI_D_Q : LSX2RI7_VVVI<0x73620000>;
def VSSRLNI_BU_H : LSX2RI4_VVVI<0x734c4000>;
def VSSRLNI_HU_W : LSX2RI5_VVVI<0x734c8000>;
def VSSRLNI_WU_D : LSX2RI6_VVVI<0x734d0000>;
def VSSRLNI_DU_Q : LSX2RI7_VVVI<0x734e0000>;
def VSSRANI_BU_H : LSX2RI4_VVVI<0x73644000>;
def VSSRANI_HU_W : LSX2RI5_VVVI<0x73648000>;
def VSSRANI_WU_D : LSX2RI6_VVVI<0x73650000>;
def VSSRANI_DU_Q : LSX2RI7_VVVI<0x73660000>;
def VSSRLRN_B_H : LSX3R_VVV<0x71008000>;
def VSSRLRN_H_W : LSX3R_VVV<0x71010000>;
def VSSRLRN_W_D : LSX3R_VVV<0x71018000>;
def VSSRARN_B_H : LSX3R_VVV<0x71028000>;
def VSSRARN_H_W : LSX3R_VVV<0x71030000>;
def VSSRARN_W_D : LSX3R_VVV<0x71038000>;
def VSSRLRN_BU_H : LSX3R_VVV<0x71088000>;
def VSSRLRN_HU_W : LSX3R_VVV<0x71090000>;
def VSSRLRN_WU_D : LSX3R_VVV<0x71098000>;
def VSSRARN_BU_H : LSX3R_VVV<0x710a8000>;
def VSSRARN_HU_W : LSX3R_VVV<0x710b0000>;
def VSSRARN_WU_D : LSX3R_VVV<0x710b8000>;
def VSSRLRNI_B_H : LSX2RI4_VVVI<0x73504000>;
def VSSRLRNI_H_W : LSX2RI5_VVVI<0x73508000>;
def VSSRLRNI_W_D : LSX2RI6_VVVI<0x73510000>;
def VSSRLRNI_D_Q : LSX2RI7_VVVI<0x73520000>;
def VSSRARNI_B_H : LSX2RI4_VVVI<0x73684000>;
def VSSRARNI_H_W : LSX2RI5_VVVI<0x73688000>;
def VSSRARNI_W_D : LSX2RI6_VVVI<0x73690000>;
def VSSRARNI_D_Q : LSX2RI7_VVVI<0x736a0000>;
def VSSRLRNI_BU_H : LSX2RI4_VVVI<0x73544000>;
def VSSRLRNI_HU_W : LSX2RI5_VVVI<0x73548000>;
def VSSRLRNI_WU_D : LSX2RI6_VVVI<0x73550000>;
def VSSRLRNI_DU_Q : LSX2RI7_VVVI<0x73560000>;
def VSSRARNI_BU_H : LSX2RI4_VVVI<0x736c4000>;
def VSSRARNI_HU_W : LSX2RI5_VVVI<0x736c8000>;
def VSSRARNI_WU_D : LSX2RI6_VVVI<0x736d0000>;
def VSSRARNI_DU_Q : LSX2RI7_VVVI<0x736e0000>;
def VCLO_B : LSX2R_VV<0x729c0000>;
def VCLO_H : LSX2R_VV<0x729c0400>;
def VCLO_W : LSX2R_VV<0x729c0800>;
def VCLO_D : LSX2R_VV<0x729c0c00>;
def VCLZ_B : LSX2R_VV<0x729c1000>;
def VCLZ_H : LSX2R_VV<0x729c1400>;
def VCLZ_W : LSX2R_VV<0x729c1800>;
def VCLZ_D : LSX2R_VV<0x729c1c00>;
def VPCNT_B : LSX2R_VV<0x729c2000>;
def VPCNT_H : LSX2R_VV<0x729c2400>;
def VPCNT_W : LSX2R_VV<0x729c2800>;
def VPCNT_D : LSX2R_VV<0x729c2c00>;
def VBITCLR_B : LSX3R_VVV<0x710c0000>;
def VBITCLR_H : LSX3R_VVV<0x710c8000>;
def VBITCLR_W : LSX3R_VVV<0x710d0000>;
def VBITCLR_D : LSX3R_VVV<0x710d8000>;
def VBITCLRI_B : LSX2RI3_VVI<0x73102000>;
def VBITCLRI_H : LSX2RI4_VVI<0x73104000>;
def VBITCLRI_W : LSX2RI5_VVI<0x73108000>;
def VBITCLRI_D : LSX2RI6_VVI<0x73110000>;
def VBITSET_B : LSX3R_VVV<0x710e0000>;
def VBITSET_H : LSX3R_VVV<0x710e8000>;
def VBITSET_W : LSX3R_VVV<0x710f0000>;
def VBITSET_D : LSX3R_VVV<0x710f8000>;
def VBITSETI_B : LSX2RI3_VVI<0x73142000>;
def VBITSETI_H : LSX2RI4_VVI<0x73144000>;
def VBITSETI_W : LSX2RI5_VVI<0x73148000>;
def VBITSETI_D : LSX2RI6_VVI<0x73150000>;
def VBITREV_B : LSX3R_VVV<0x71100000>;
def VBITREV_H : LSX3R_VVV<0x71108000>;
def VBITREV_W : LSX3R_VVV<0x71110000>;
def VBITREV_D : LSX3R_VVV<0x71118000>;
def VBITREVI_B : LSX2RI3_VVI<0x73182000>;
def VBITREVI_H : LSX2RI4_VVI<0x73184000>;
def VBITREVI_W : LSX2RI5_VVI<0x73188000>;
def VBITREVI_D : LSX2RI6_VVI<0x73190000>;
def VFRSTP_B : LSX3R_VVVV<0x712b0000>;
def VFRSTP_H : LSX3R_VVVV<0x712b8000>;
def VFRSTPI_B : LSX2RI5_VVVI<0x729a0000>;
def VFRSTPI_H : LSX2RI5_VVVI<0x729a8000>;
def VFADD_S : LSX3R_VVV<0x71308000>;
def VFADD_D : LSX3R_VVV<0x71310000>;
def VFSUB_S : LSX3R_VVV<0x71328000>;
def VFSUB_D : LSX3R_VVV<0x71330000>;
def VFMUL_S : LSX3R_VVV<0x71388000>;
def VFMUL_D : LSX3R_VVV<0x71390000>;
def VFDIV_S : LSX3R_VVV<0x713a8000>;
def VFDIV_D : LSX3R_VVV<0x713b0000>;
def VFMADD_S : LSX4R_VVVV<0x09100000>;
def VFMADD_D : LSX4R_VVVV<0x09200000>;
def VFMSUB_S : LSX4R_VVVV<0x09500000>;
def VFMSUB_D : LSX4R_VVVV<0x09600000>;
def VFNMADD_S : LSX4R_VVVV<0x09900000>;
def VFNMADD_D : LSX4R_VVVV<0x09a00000>;
def VFNMSUB_S : LSX4R_VVVV<0x09d00000>;
def VFNMSUB_D : LSX4R_VVVV<0x09e00000>;
def VFMAX_S : LSX3R_VVV<0x713c8000>;
def VFMAX_D : LSX3R_VVV<0x713d0000>;
def VFMIN_S : LSX3R_VVV<0x713e8000>;
def VFMIN_D : LSX3R_VVV<0x713f0000>;
def VFMAXA_S : LSX3R_VVV<0x71408000>;
def VFMAXA_D : LSX3R_VVV<0x71410000>;
def VFMINA_S : LSX3R_VVV<0x71428000>;
def VFMINA_D : LSX3R_VVV<0x71430000>;
def VFLOGB_S : LSX2R_VV<0x729cc400>;
def VFLOGB_D : LSX2R_VV<0x729cc800>;
def VFCLASS_S : LSX2R_VV<0x729cd400>;
def VFCLASS_D : LSX2R_VV<0x729cd800>;
def VFSQRT_S : LSX2R_VV<0x729ce400>;
def VFSQRT_D : LSX2R_VV<0x729ce800>;
def VFRECIP_S : LSX2R_VV<0x729cf400>;
def VFRECIP_D : LSX2R_VV<0x729cf800>;
def VFRSQRT_S : LSX2R_VV<0x729d0400>;
def VFRSQRT_D : LSX2R_VV<0x729d0800>;
def VFRECIPE_S : LSX2R_VV<0x729d1400>;
def VFRECIPE_D : LSX2R_VV<0x729d1800>;
def VFRSQRTE_S : LSX2R_VV<0x729d2400>;
def VFRSQRTE_D : LSX2R_VV<0x729d2800>;
def VFCVTL_S_H : LSX2R_VV<0x729de800>;
def VFCVTH_S_H : LSX2R_VV<0x729dec00>;
def VFCVTL_D_S : LSX2R_VV<0x729df000>;
def VFCVTH_D_S : LSX2R_VV<0x729df400>;
def VFCVT_H_S : LSX3R_VVV<0x71460000>;
def VFCVT_S_D : LSX3R_VVV<0x71468000>;
def VFRINTRNE_S : LSX2R_VV<0x729d7400>;
def VFRINTRNE_D : LSX2R_VV<0x729d7800>;
def VFRINTRZ_S : LSX2R_VV<0x729d6400>;
def VFRINTRZ_D : LSX2R_VV<0x729d6800>;
def VFRINTRP_S : LSX2R_VV<0x729d5400>;
def VFRINTRP_D : LSX2R_VV<0x729d5800>;
def VFRINTRM_S : LSX2R_VV<0x729d4400>;
def VFRINTRM_D : LSX2R_VV<0x729d4800>;
def VFRINT_S : LSX2R_VV<0x729d3400>;
def VFRINT_D : LSX2R_VV<0x729d3800>;
def VFTINTRNE_W_S : LSX2R_VV<0x729e5000>;
def VFTINTRNE_L_D : LSX2R_VV<0x729e5400>;
def VFTINTRZ_W_S : LSX2R_VV<0x729e4800>;
def VFTINTRZ_L_D : LSX2R_VV<0x729e4c00>;
def VFTINTRP_W_S : LSX2R_VV<0x729e4000>;
def VFTINTRP_L_D : LSX2R_VV<0x729e4400>;
def VFTINTRM_W_S : LSX2R_VV<0x729e3800>;
def VFTINTRM_L_D : LSX2R_VV<0x729e3c00>;
def VFTINT_W_S : LSX2R_VV<0x729e3000>;
def VFTINT_L_D : LSX2R_VV<0x729e3400>;
def VFTINTRZ_WU_S : LSX2R_VV<0x729e7000>;
def VFTINTRZ_LU_D : LSX2R_VV<0x729e7400>;
def VFTINT_WU_S : LSX2R_VV<0x729e5800>;
def VFTINT_LU_D : LSX2R_VV<0x729e5c00>;