accumulator fix

Author: timothygu1

src/cpu_core.v

@@ -53,13 +53,10 @@ module cpu_core (
     shift_reg #(8) acc (
         .clk(clk),
         .rstn(rst_n),
-        .en(acc_shift_en || acc_write_en),
-        .load(acc_write_en),
-        .dir(1'b1),
+        .en(acc_write_en),
         .serial_in(alu_result),
         .parallel_in(8'b0),
-        .q(out),
-        .serial_out(acc_out_bit)
+        .q(out)
     );
 
     // ALU
@@ -91,6 +88,7 @@ module cpu_core (
         .btn_edge(btn_edge),
         .bit_done(bit_done),
         .alu_op(alu_op),
+        .acc_write_en(acc_write_en),
         .reg_shift_en(reg_shift_en),
         .reg_write_en(reg_write_en),
         .acc_write_en(acc_write_en),
@@ -101,5 +99,5 @@ module cpu_core (
         .carry_en(carry_en)
     );
 
-    wire _unused = &{carry_in, acc_shift_en, 1'b0, reg_write_en, acc_write_en};
+    wire _unused = &{carry_in, acc_shift_en, 1'b0, reg_write_en};
 endmodule

src/fsm_control.v

@@ -62,7 +62,6 @@ module fsm_control (
                     next_state = S_EXECUTE;
 
             S_EXECUTE:
-                if (bit_done)
                     next_state = S_WRITE_ACC;
 
             S_WRITE_ACC:
@@ -97,9 +96,11 @@ module fsm_control (
             end
 
             S_WRITE_ACC: begin
-                acc_write_en = 1;
-                acc_shift_en = 1;
+                reg_shift_en = 1;
+                alu_op       = decode_alu_op(opcode);
                 en_counter   = 1;
+                carry_en     = 1;
+                acc_write_en = 1;
             end
         endcase
     end

src/shift_reg.v

@@ -1,4 +1,4 @@
-// shift_reg.v - bidirectional shift register with optional parallel load
+// shift_reg.v - shift register with optional parallel load
 
 `default_nettype none
 
@@ -9,27 +9,30 @@ module shift_reg
     input  wire                  rstn,        // active-low synchronous reset
     input  wire                  en,          // 1 -> perform load/shift
     input  wire                  load,        // 1 -> parallel load, 0 -> shift
-    input  wire                  dir,         // 0 -> shift left, 1 -> shift right
     input  wire                  serial_in,   // bit entering during a shift
     input  wire  [WIDTH-1:0]     parallel_in, // data for parallel load
-    output reg   [WIDTH-1:0]     q,           // register contents
-    output wire                  serial_out   // bit exiting during a shift
+    output reg   [WIDTH-1:0]     q           // register contents
 );
 
+    reg [$clog2(WIDTH)-1:0] bit_index;
+    
     // next-state datapath
     wire [WIDTH-1:0] next_q =
-        load          ? parallel_in                    : // parallel load
-        (dir == 1'b0) ? {q[WIDTH-2:0], serial_in}      : // shift left
-                        {serial_in, q[WIDTH-1:1]};       // shift right
+        load          ? parallel_in : {serial_in, q[WIDTH-1:1]};       
 
-    // sequential part
-    always @(posedge clk)
-        if (!rstn)
+     always @(posedge clk or negedge rstn) begin
+        if (!rstn) begin
             q <= {WIDTH{1'b0}};   // synchronous clear
-        else if (en)
-            q <= next_q;          // load or shift
-
-    // bit shifted out on this cycle
-    assign serial_out = dir ? q[0] : q[WIDTH-1];
+            bit_index <= 0;
+        end else if (en) begin
+            if (load) begin
+                q[WIDTH-1:0] <= parallel_in;
+                bit_index <= 0;
+            end else begin
+                q[bit_index] <= serial_in;
+                bit_index <= bit_index + 1; // increment bit index each cycle
+            end
+        end
+    end
 
 endmodule

test/test.gtkw

@@ -1,22 +1,22 @@
 [*]
 [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
-[*] Tue Jul  8 20:02:40 2025
+[*] Tue Jul  8 23:26:25 2025
 [*]
 [dumpfile] "/workspaces/bit-serial-CPU/test/tb.vcd"
-[dumpfile_mtime] "Tue Jul  8 19:58:49 2025"
-[dumpfile_size] 9847
+[dumpfile_mtime] "Tue Jul  8 23:25:01 2025"
+[dumpfile_size] 9954
 [savefile] "/workspaces/bit-serial-CPU/test/test.gtkw"
-[timestart] 772800000
-[size] 1000 600
+[timestart] 737400000
+[size] 1182 600
 [pos] -1 -1
-*-26.000000 845200000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-26.000000 912800000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] tb.
 [treeopen] tb.user_project.
 [treeopen] tb.user_project.u_cpu_core.
 [sst_width] 214
-[signals_width] 150
+[signals_width] 210
 [sst_expanded] 1
-[sst_vpaned_height] 60
+[sst_vpaned_height] 171
 @22
 tb.ui_in[7:0]
 tb.uio_in[7:0]
@@ -40,5 +40,11 @@ tb.user_project.u_cpu_core.regfile.rs1_bit
 tb.user_project.u_cpu_core.regfile.rs2_bit
 tb.user_project.u_cpu_core.regfile.rs1_addr[2:0]
 tb.user_project.u_cpu_core.regfile.rs2_addr[2:0]
+tb.user_project.u_cpu_core.alu.alu_op[1:0]
+tb.user_project.u_cpu_core.alu.result
+@23
+tb.user_project.u_cpu_core.acc.q[7:0]
+@28
+tb.user_project.u_cpu_core.acc.en
 [pattern_trace] 1
 [pattern_trace] 0

test/test.py

@@ -68,7 +68,7 @@ async def test_project(dut):
     dut._log.info("Test project behavior")
 
     # Input first 8 instruction bits
-    await load_instruction(dut, 0x32)
+    await load_instruction(dut, 0b00111100)
 
     # Input second 8 instruction bits
     await load_instruction(dut, 0x04)