add load + store + sub and heavy refactor

Author: timothygu1

info.yaml

@@ -20,9 +20,8 @@ project:
     - "top.v"
     - "cpu_core.v"
     - "alu_1bit.v"
-    - "counter.v"
     - "fsm_control.v"
-    - "shift_reg.v"
+    - "accumulator.v"
     - "regfile_serial.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.

src/accumulator.v

@@ -0,0 +1,46 @@
+// shift_reg.v - shift register with optional parallel load
+
+`default_nettype none
+
+module accumulator
+#(parameter WIDTH = 8)
+(
+    input  wire                  clk,
+    input  wire                  rst_n,        // active-low synchronous reset
+    input  wire                  acc_write_en,          // 1 -> perform load/shift
+    input  wire                  acc_load_en,        // 1 -> parallel load, 0 -> shift
+    input  wire  [WIDTH-1:0]     acc_parallel_in,
+    input  wire                  alu_result,   // bit entering during a shift
+    output reg   [WIDTH-1:0]     acc_bits,           // register contents
+    output reg      done
+);
+
+    reg [$clog2(WIDTH)-1:0] bit_index;    
+
+     always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            acc_bits <= {WIDTH{1'b0}};   // synchronous clear
+            bit_index <= 0;
+        end else if (acc_load_en) begin
+            acc_bits <= acc_parallel_in;
+            bit_index <= 0;
+        end else if (acc_write_en) begin
+            acc_bits[bit_index] <= alu_result;
+            bit_index <= bit_index + 1;
+        end else begin
+            bit_index <= 0;
+        end
+     end 
+
+
+        // Combinational logic
+        always @(*) begin
+            if (bit_index == WIDTH - 2) begin
+                done = 1;
+            end
+            else begin
+                done = 0;
+            end
+        end
+
+endmodule

src/alu_1bit.v

@@ -3,27 +3,62 @@
 `default_nettype none
 
 module alu_1bit (
+    input  wire clk,
+    input  wire rst_n,
     input  wire rs1,
     input  wire rs2,
-    input  wire carry_in,
-    input  wire [1:0] alu_op,   // 2-bit op select
-    output wire result,
-    output wire carry_out
+    input  wire [2:0] alu_op,   // 3-bit op select
+    input  wire alu_enable,
+    input  wire alu_start,
+    output reg alu_result
 );
+    
+    wire carry_out;
+    reg carry_in;
+    wire inverted = ~rs2; // Inverted rs2 for subtraction
 
-    wire add_result = rs1 ^ rs2 ^ carry_in;
-    wire add_cout   = (rs1 & rs2) | (rs1 & carry_in) | (rs2 & carry_in);
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            carry_in <= 0;
+            alu_result <= 0;
+        end else if (alu_enable) begin
+            carry_in <= carry_out;
+            // process one bit this cycle
+            if (alu_op == 3'b000) begin
+                alu_result <= rs1 ^ rs2 ^ carry_in;
+            end else if (alu_op == 3'b001) begin
+                alu_result <= rs1 ^ inverted ^ carry_in;
+            end else if (alu_op == 3'b010) begin
+                alu_result <= rs1 ^ rs2;
+            end else if (alu_op == 3'b011) begin
+                alu_result <= rs1 & rs2;
+            end else if (alu_op == 3'b100) begin
+                alu_result <= rs1 | rs2;
+            end else begin
+                alu_result <= 1'b0;
+            end
+        end
+    end
 
-    wire and_result = rs1 & rs2;
-    wire or_result  = rs1 | rs2;
-    wire xor_result = rs1 ^ rs2;
-
-    assign result = (alu_op == 2'b00) ? add_result :
-                    (alu_op == 2'b01) ? xor_result :
-                    (alu_op == 2'b10) ? and_result :
-                    (alu_op == 2'b11) ? or_result  :
+   assign carry_out = (alu_start && (alu_op == 3'b001)) ? 1'b1 :
+                    (alu_enable && (alu_op == 3'b001)) ? (rs1 & inverted) | (rs1 & carry_in) | (inverted & carry_in) :
+                    (alu_enable && (alu_op == 3'b000)) ? (rs1 & rs2) | (rs1 & carry_in) | (rs2 & carry_in) :
                     1'b0;
 
-    assign carry_out = (alu_op == 2'b00) ? add_cout : 1'b0;
+    //wire add_result = alu_op == ? rs1 ^ rs2 ^ carry_in : rs1 ^ ~rs2 ^ 1'b0;
+    //wire add_cout   = (rs1 & rs2) | (rs1 & carry_in) | (rs2 & carry_in);
+
+    // wire and_result = rs1 & rs2;
+    // wire or_result  = rs1 | rs2;
+    // wire xor_result = rs1 ^ rs2;
+
+    // assign alu_result = (alu_op == 3'b000) ? rs1 ^ rs2 ^ carry_in :
+    //                 (alu_op == 3'b001) ? rs1 ^ ~rs2 ^ 1'b0 :
+    //                 (alu_op == 3'b010) ? rs2 ^ rs2 :
+    //                 (alu_op == 3'b011) ? rs1 & rs2 :
+    //                 (alu_op == 3'b100) ? rs1 | rs2  :
+    //                 1'b0;
+
+    // assign carry_out = ((alu_op == 3'b000) & carry_en) ? add_cout : 1'b0;
 
 endmodule

src/counter.v

@@ -9,33 +9,28 @@ module cpu_core (
     input  wire [11:0] instr,
     input  wire        inst_done,
     input  wire        btn_edge,
-    output wire [7:0]  out
+    output wire [7:0]  acc_bits
 );
 
     // Wires between modules
     wire rs1_bit, rs2_bit, alu_result;
-    wire [1:0] alu_op;
-    wire carry_in, carry_out; // LINT fix: unused for now 
+    wire [2:0] alu_op;
 
-    wire reg_shift_en, acc_shift_en;
+    wire alu_start;
+    wire reg_shift_en, acc_write_en;
     wire imm_shift_en;
-    wire reg_write_en, acc_write_en;
+    wire reg_store_en, acc_load_en;
     wire en_counter, clr_counter;
     wire bit_done;
     wire carry_en;
-    wire acc_out_bit;
 
-    wire [2:0] count; // unused
+    wire [7:0] acc_parallel_in;
+    wire [7:0] regfile_bits;
+
+    assign acc_parallel_in = acc_load_en ? (opcode[3] ? regfile_bits : instr[11:4]) // load from regfile if R-type, otherwise use imm
+                             : 8'b0; 
 
-    // Carry register
-    reg carry;
-    always @(posedge clk)
-        if (!rst_n)
-            carry <= 0;
-        else if (carry_en)
-            carry <= 0;
-        else
-            carry <= carry_out;
+    wire [2:0] count; // unused
 
     // TODO: REGFILE
     regfile_serial regfile (
@@ -46,38 +41,33 @@ module cpu_core (
         .is_rtype(opcode[3]),
         .rs1_bit(rs1_bit),
         .rs2_bit(rs2_bit),
-        .wr_bit(acc_out_bit),
-        .wr_en(reg_write_en)
+        .acc_bits(acc_bits),
+        .regfile_bits(regfile_bits),
+        .reg_store_en(reg_store_en)
     );
 
     // Accumulator register
-    shift_reg #(8) acc (
+    accumulator #(8) acc (
         .clk(clk),
         .rst_n(rst_n),
-        .en(acc_write_en),
-        .serial_in(alu_result),
-        .parallel_in(8'b0),
-        .q(out)
+        .acc_load_en(acc_load_en),
+        .acc_parallel_in(acc_parallel_in),
+        .acc_write_en(acc_write_en),
+        .alu_result(alu_result),
+        .acc_bits(acc_bits),
+        .done(bit_done)
     );
 
     // ALU
     alu_1bit alu (
+        .clk(clk),
+        .rst_n(rst_n),
         .rs1(rs1_bit),
         .rs2(rs2_bit),
-        .carry_in(carry),
+        .alu_start(alu_start),
         .alu_op(alu_op),
-        .result(alu_result),
-        .carry_out(carry_out)
-    );
-
-    // Counter
-    counter exec_counter (
-        .clk(clk),
-        .rstn(rst_n),
-        .en(en_counter),
-        .clr(clr_counter),
-        .done(bit_done),
-        .count(count) // not being used
+        .alu_enable(carry_en),
+        .alu_result(alu_result)
     );
 
     // Control FSM
@@ -89,15 +79,13 @@ module cpu_core (
         .btn_edge(btn_edge),
         .bit_done(bit_done),
         .alu_op(alu_op),
+        .alu_start(alu_start),
+        .acc_load_en(acc_load_en),
         .acc_write_en(acc_write_en),
         .reg_shift_en(reg_shift_en),
-        .reg_write_en(reg_write_en),
-        .acc_shift_en(acc_shift_en),
+        .reg_store_en(reg_store_en),
         .imm_shift_en(imm_shift_en),
-        .clr_counter(clr_counter),
-        .en_counter(en_counter),
         .carry_en(carry_en)
     );
 
-    wire _unused = &{carry_in, acc_shift_en, 1'b0, reg_write_en};
 endmodule