Skip to content

Commit 8e5eb83

Browse files
committed
WIP
1 parent 0a0e8f2 commit 8e5eb83

File tree

2 files changed

+75
-25
lines changed

2 files changed

+75
-25
lines changed

info.yaml

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,17 @@
11
# Tiny Tapeout project information
22
project:
3-
title: "" # Project title
4-
author: "" # Your name
3+
title: "16-bit bit-serial CPU" # Project title
4+
author: "Tim Gu, Andrew Wang" # Your name
55
discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
6-
description: "" # One line description of what your project does
6+
description: "A bit-serial CPU and 16-bit instruction architecture" # One line description of what your project does
77
language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
8-
clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable)
8+
clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable) # TODO: may need to prescale clock
99

1010
# How many tiles your design occupies? A single tile is about 167x108 uM.
1111
tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
1212

1313
# Your top module name must start with "tt_um_". Make it unique by including your github username:
14-
top_module: "tt_um_example"
14+
top_module: "tt_um_cpu_top"
1515

1616
# List your project's source files here.
1717
# Source files must be in ./src and you must list each source file separately, one per line.
@@ -23,27 +23,27 @@ project:
2323
# This section is for the datasheet/website. Use descriptive names (e.g., RX, TX, MOSI, SCL, SEG_A, etc.).
2424
pinout:
2525
# Inputs
26-
ui[0]: ""
27-
ui[1]: ""
28-
ui[2]: ""
29-
ui[3]: ""
30-
ui[4]: ""
31-
ui[5]: ""
32-
ui[6]: ""
33-
ui[7]: ""
26+
ui[0]: "INST_0"
27+
ui[1]: "INST_1"
28+
ui[2]: "INST_2"
29+
ui[3]: "INST_3"
30+
ui[4]: "INST_4"
31+
ui[5]: "INST_5"
32+
ui[6]: "INST_6"
33+
ui[7]: "INST_7"
3434

3535
# Outputs
36-
uo[0]: ""
37-
uo[1]: ""
38-
uo[2]: ""
39-
uo[3]: ""
40-
uo[4]: ""
41-
uo[5]: ""
42-
uo[6]: ""
43-
uo[7]: ""
36+
uo[0]: "LED_0"
37+
uo[1]: "LED_1"
38+
uo[2]: "LED_2"
39+
uo[3]: "LED_3"
40+
uo[4]: "LED_4"
41+
uo[5]: "LED_5"
42+
uo[6]: "LED_6"
43+
uo[7]: "LED_7"
4444

4545
# Bidirectional pins
46-
uio[0]: ""
46+
uio[0]: "PB_INST"
4747
uio[1]: ""
4848
uio[2]: ""
4949
uio[3]: ""

src/project.v

Lines changed: 53 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,9 @@
55

66
`default_nettype none
77

8-
module tt_um_example (
9-
input wire [7:0] ui_in, // Dedicated inputs
10-
output wire [7:0] uo_out, // Dedicated outputs
8+
module tt_um_cpu_top (
9+
input wire [7:0] ui_in, // Inputs for instruction data (through DIP switches)
10+
output wire [7:0] uo_out, // Outputs to drive LEDs
1111
input wire [7:0] uio_in, // IOs: Input path
1212
output wire [7:0] uio_out, // IOs: Output path
1313
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
@@ -21,6 +21,56 @@ module tt_um_example (
2121
assign uio_out = 0;
2222
assign uio_oe = 0;
2323

24+
25+
reg [15:0] instr;
26+
reg [3:0] bit_count;
27+
28+
/*
29+
IDEAS IN PROGRESS:
30+
S_IDLE should display a status on the 7-seg display on the demo board. Perhaps a letter indicating the expected next input
31+
('L' for lower 8 bits, 'H' for upper 8 bits)
32+
33+
34+
35+
*/
36+
37+
// Button edge-detector and synchronizer
38+
39+
reg btn_sync0, btn_sync1, btn_prev;
40+
wire btn_level = uio_in[0]; // external push button
41+
wire btn_edge = btn_sync1 & ~btn_prev; // detect rising edge
42+
43+
always @(posedge clk or negedge rst_n) begin
44+
if (!rst_n) begin
45+
btn_sync0 <= 1'b1; // assume pull-up idle high
46+
btn_sync1 <= 1'b1;
47+
btn_prev <= 1'b1;
48+
end else begin
49+
btn_sync0 <= btn_level;
50+
btn_sync1 <= btn_sync0;
51+
btn_prev <= btn_sync1;
52+
end
53+
end
54+
55+
// FSM states
56+
57+
typedef enum logic [2:0] {
58+
S_RESET, // TODO is this needed, or do we use built-in rst_n instead?
59+
S_IDLE, // waiting for button press to shift in instruction bit values from DIP switches
60+
S_FETCH_LO, // capture lower 8 instruction bits
61+
S_FETCH_HI, // capture upper 8 instruction bits
62+
S_EXECUTE // perform
63+
} state_t;
64+
65+
state_t state, next_state;
66+
67+
// datapath control signals and serial wires
68+
69+
reg le; // load enable for shift registers
70+
reg ae; // accumulate enable for ALU
71+
wire serial_in; // single bit serial input into ALU
72+
wire serial_out; // single bit serial output from ALU
73+
2474
// List all unused inputs to prevent warnings
2575
wire _unused = &{ena, clk, rst_n, 1'b0};
2676

0 commit comments

Comments
 (0)