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gtwiz_us_nlv.log
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# Copyright (C) 1994-2019, Concept Engineering GmbH.
# All Rights Reserved. Cmd=logfile.
# Nlview 7.0.21 2019-05-29 bk=1.5064 VDI=41 GEI=36 GUI=JA:9.0 TLS
# License cookie [G|T|S|B|*] for HR="Xilinx Inc."
# -----------------------------------------------------------------------------
# -----------------------------------------------------------------------------
property attrfontsize 8
property fillcolor1
#R #441133
property fillcolor5
#R #651b4d
property -colorscheme lightblue
property shadowstyle 1
property gatecellname 2
property showpinname 2
property boxminwidth 50
property boxminheight 40
#CMD bind stroke-1 -action {}
#CMD bind stroke-nw-1 -action callback -echo_type line -echo_text {Zoom fit}
#CMD bind stroke-nw-1 -action zoom_fit -echo_type line -echo_text {Zoom fit}
#CMD bind stroke-ne-1 -action zoom_out -echo_type line -echo_text {Zoom -%z}
#CMD bind stroke-se-1 -action zoom_in -echo_type rectangle -autoscroll -echo_text {Zoom area}
#CMD bind stroke-sw-1 -action zoom_in2 -echo_type line -echo_text {Zoom +%z}
module new gtmodule
# * Current module is gtmodule
load symbol QUAD_X0 v HIERBOX port a0 in port a1 in port a2 in port a3 in port QPLL0 in port QPLL1 in port RECCLK_clk0 out port RECCLK_clk1 out
load symbol QUAD_X1 v HIERBOX port a0 out port a1 out port a2 out port a3 out port QPLL0 out port QPLL1 out port RECCLK_clk0 in port RECCLK_clk1 in
load symbol CPLL_X0 syn BOX port A in port B out text CPLL -cc 25 0 12
load symbol CPLL_X1 syn BOX port A out port B in text CPLL -cc 25 0 12
load symbol QPLL0_X0 syn BOX port A in port B out text QPLL0 -cc 25 0 12
load symbol QPLL0_X1 syn BOX port A out port B in text QPLL0 -cc 25 0 12
load symbol QPLL1_X0 syn BOX port A in port B out text QPLL1 -cc 25 0 12
load symbol QPLL1_X1 syn BOX port A out port B in text QPLL1 -cc 25 0 12
load inst QuadX0Y9 QUAD_X0 v -pg 1 -y 1 -x 2000 -autohide -attr @cell QuadX0Y9 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin QuadX0Y9 QPLL0 } -attr @name {}
attribute {hierPin QuadX0Y9 QPLL0 } -attr @name {}
attribute {pin QuadX0Y9 QPLL1 } -attr @name {}
attribute {hierPin QuadX0Y9 QPLL1 } -attr @name {}
attribute {pin QuadX0Y9 a0 } -attr @name {}
attribute {hierPin QuadX0Y9 a0 } -attr @name {}
attribute {pin QuadX0Y9 a1 } -attr @name {}
attribute {hierPin QuadX0Y9 a1 } -attr @name {}
attribute {pin QuadX0Y9 a2 } -attr @name {}
attribute {hierPin QuadX0Y9 a2 } -attr @name {}
attribute {pin QuadX0Y9 a3 } -attr @name {}
attribute {hierPin QuadX0Y9 a3 } -attr @name {}
attribute {pin QuadX0Y9 RECCLK_clk0 } -attr @name {}
attribute {hierPin QuadX0Y9 RECCLK_clk0 } -attr @name {}
attribute {pin QuadX0Y9 RECCLK_clk1 } -attr @name {}
attribute {hierPin QuadX0Y9 RECCLK_clk1 } -attr @name {}
load inst cpll.X0Y39 CPLL_X0 syn -hier QuadX0Y9 -pg 1 -y 2 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y39 A} -attr @name {}
attribute {pin cpll.X0Y39 B} -attr @name {}
attribute {inst cpll.X0Y39} -attr @fillcolor #00868b
load symbol X0Y39 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y39 X0Y39 syn -hier QuadX0Y9 -pg 1 -y 2 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y39} -attr @fillcolor #7a7a7a
load inst cpll.X0Y38 CPLL_X0 syn -hier QuadX0Y9 -pg 1 -y 87 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y38 A} -attr @name {}
attribute {pin cpll.X0Y38 B} -attr @name {}
attribute {inst cpll.X0Y38} -attr @fillcolor #00868b
load symbol X0Y38 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y38 X0Y38 syn -hier QuadX0Y9 -pg 1 -y 87 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y38} -attr @fillcolor #7a7a7a
load inst QPLL0.QuadX0Y9 QPLL0_X0 syn -hier QuadX0Y9 -pg 1 -y 172 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL0.QuadX0Y9 A} -attr @name {}
attribute {pin QPLL0.QuadX0Y9 B} -attr @name {}
attribute {inst QPLL0.QuadX0Y9} -attr @fillcolor #00868b
load inst QPLL1.QuadX0Y9 QPLL1_X0 syn -hier QuadX0Y9 -pg 1 -y 257 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL1.QuadX0Y9 A} -attr @name {}
attribute {pin QPLL1.QuadX0Y9 B} -attr @name {}
attribute {inst QPLL1.QuadX0Y9} -attr @fillcolor #00868b
load inst cpll.X0Y37 CPLL_X0 syn -hier QuadX0Y9 -pg 1 -y 342 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y37 A} -attr @name {}
attribute {pin cpll.X0Y37 B} -attr @name {}
attribute {inst cpll.X0Y37} -attr @fillcolor #00868b
load symbol X0Y37 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y37 X0Y37 syn -hier QuadX0Y9 -pg 1 -y 342 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y37} -attr @fillcolor #7a7a7a
load inst cpll.X0Y36 CPLL_X0 syn -hier QuadX0Y9 -pg 1 -y 427 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y36 A} -attr @name {}
attribute {pin cpll.X0Y36 B} -attr @name {}
attribute {inst cpll.X0Y36} -attr @fillcolor #00868b
load symbol X0Y36 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y36 X0Y36 syn -hier QuadX0Y9 -pg 1 -y 427 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y36} -attr @fillcolor #7a7a7a
load port QuadX0Y9_clk0 in -pg 1 -y 141 -x 1 -attr @fillcolor #3a5fcd
load port QuadX0Y9_clk1 in -pg 1 -y 311 -x 1 -attr @fillcolor #3a5fcd
load inst QuadX0Y8 QUAD_X0 v -pg 1 -y 563 -x 2000 -autohide -attr @cell QuadX0Y8 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin QuadX0Y8 QPLL0 } -attr @name {}
attribute {hierPin QuadX0Y8 QPLL0 } -attr @name {}
attribute {pin QuadX0Y8 QPLL1 } -attr @name {}
attribute {hierPin QuadX0Y8 QPLL1 } -attr @name {}
attribute {pin QuadX0Y8 a0 } -attr @name {}
attribute {hierPin QuadX0Y8 a0 } -attr @name {}
attribute {pin QuadX0Y8 a1 } -attr @name {}
attribute {hierPin QuadX0Y8 a1 } -attr @name {}
attribute {pin QuadX0Y8 a2 } -attr @name {}
attribute {hierPin QuadX0Y8 a2 } -attr @name {}
attribute {pin QuadX0Y8 a3 } -attr @name {}
attribute {hierPin QuadX0Y8 a3 } -attr @name {}
attribute {pin QuadX0Y8 RECCLK_clk0 } -attr @name {}
attribute {hierPin QuadX0Y8 RECCLK_clk0 } -attr @name {}
attribute {pin QuadX0Y8 RECCLK_clk1 } -attr @name {}
attribute {hierPin QuadX0Y8 RECCLK_clk1 } -attr @name {}
load inst cpll.X0Y35 CPLL_X0 syn -hier QuadX0Y8 -pg 1 -y 564 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y35 A} -attr @name {}
attribute {pin cpll.X0Y35 B} -attr @name {}
attribute {inst cpll.X0Y35} -attr @fillcolor #00868b
load symbol X0Y35 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y35 X0Y35 syn -hier QuadX0Y8 -pg 1 -y 564 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y35} -attr @fillcolor #7a7a7a
load inst cpll.X0Y34 CPLL_X0 syn -hier QuadX0Y8 -pg 1 -y 649 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y34 A} -attr @name {}
attribute {pin cpll.X0Y34 B} -attr @name {}
attribute {inst cpll.X0Y34} -attr @fillcolor #00868b
load symbol X0Y34 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y34 X0Y34 syn -hier QuadX0Y8 -pg 1 -y 649 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y34} -attr @fillcolor #7a7a7a
load inst QPLL0.QuadX0Y8 QPLL0_X0 syn -hier QuadX0Y8 -pg 1 -y 734 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL0.QuadX0Y8 A} -attr @name {}
attribute {pin QPLL0.QuadX0Y8 B} -attr @name {}
attribute {inst QPLL0.QuadX0Y8} -attr @fillcolor #00868b
load inst QPLL1.QuadX0Y8 QPLL1_X0 syn -hier QuadX0Y8 -pg 1 -y 819 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL1.QuadX0Y8 A} -attr @name {}
attribute {pin QPLL1.QuadX0Y8 B} -attr @name {}
attribute {inst QPLL1.QuadX0Y8} -attr @fillcolor #00868b
load inst cpll.X0Y33 CPLL_X0 syn -hier QuadX0Y8 -pg 1 -y 904 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y33 A} -attr @name {}
attribute {pin cpll.X0Y33 B} -attr @name {}
attribute {inst cpll.X0Y33} -attr @fillcolor #00868b
load symbol X0Y33 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y33 X0Y33 syn -hier QuadX0Y8 -pg 1 -y 904 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y33} -attr @fillcolor #7a7a7a
load inst cpll.X0Y32 CPLL_X0 syn -hier QuadX0Y8 -pg 1 -y 989 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y32 A} -attr @name {}
attribute {pin cpll.X0Y32 B} -attr @name {}
attribute {inst cpll.X0Y32} -attr @fillcolor #00868b
load symbol X0Y32 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y32 X0Y32 syn -hier QuadX0Y8 -pg 1 -y 989 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y32} -attr @fillcolor #7a7a7a
load port QuadX0Y8_clk0 in -pg 1 -y 703 -x 1 -attr @fillcolor #3a5fcd
load port QuadX0Y8_clk1 in -pg 1 -y 873 -x 1 -attr @fillcolor #3a5fcd
load inst QuadX0Y7 QUAD_X0 v -pg 1 -y 1125 -x 2000 -autohide -attr @cell QuadX0Y7 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin QuadX0Y7 QPLL0 } -attr @name {}
attribute {hierPin QuadX0Y7 QPLL0 } -attr @name {}
attribute {pin QuadX0Y7 QPLL1 } -attr @name {}
attribute {hierPin QuadX0Y7 QPLL1 } -attr @name {}
attribute {pin QuadX0Y7 a0 } -attr @name {}
attribute {hierPin QuadX0Y7 a0 } -attr @name {}
attribute {pin QuadX0Y7 a1 } -attr @name {}
attribute {hierPin QuadX0Y7 a1 } -attr @name {}
attribute {pin QuadX0Y7 a2 } -attr @name {}
attribute {hierPin QuadX0Y7 a2 } -attr @name {}
attribute {pin QuadX0Y7 a3 } -attr @name {}
attribute {hierPin QuadX0Y7 a3 } -attr @name {}
attribute {pin QuadX0Y7 RECCLK_clk0 } -attr @name {}
attribute {hierPin QuadX0Y7 RECCLK_clk0 } -attr @name {}
attribute {pin QuadX0Y7 RECCLK_clk1 } -attr @name {}
attribute {hierPin QuadX0Y7 RECCLK_clk1 } -attr @name {}
load inst cpll.X0Y31 CPLL_X0 syn -hier QuadX0Y7 -pg 1 -y 1126 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y31 A} -attr @name {}
attribute {pin cpll.X0Y31 B} -attr @name {}
attribute {inst cpll.X0Y31} -attr @fillcolor #00868b
load symbol X0Y31 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y31 X0Y31 syn -hier QuadX0Y7 -pg 1 -y 1126 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y31} -attr @fillcolor #7a7a7a
load inst cpll.X0Y30 CPLL_X0 syn -hier QuadX0Y7 -pg 1 -y 1211 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y30 A} -attr @name {}
attribute {pin cpll.X0Y30 B} -attr @name {}
attribute {inst cpll.X0Y30} -attr @fillcolor #00868b
load symbol X0Y30 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y30 X0Y30 syn -hier QuadX0Y7 -pg 1 -y 1211 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y30} -attr @fillcolor #7a7a7a
load inst QPLL0.QuadX0Y7 QPLL0_X0 syn -hier QuadX0Y7 -pg 1 -y 1296 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL0.QuadX0Y7 A} -attr @name {}
attribute {pin QPLL0.QuadX0Y7 B} -attr @name {}
attribute {inst QPLL0.QuadX0Y7} -attr @fillcolor #00868b
load inst QPLL1.QuadX0Y7 QPLL1_X0 syn -hier QuadX0Y7 -pg 1 -y 1381 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL1.QuadX0Y7 A} -attr @name {}
attribute {pin QPLL1.QuadX0Y7 B} -attr @name {}
attribute {inst QPLL1.QuadX0Y7} -attr @fillcolor #00868b
load inst cpll.X0Y29 CPLL_X0 syn -hier QuadX0Y7 -pg 1 -y 1466 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y29 A} -attr @name {}
attribute {pin cpll.X0Y29 B} -attr @name {}
attribute {inst cpll.X0Y29} -attr @fillcolor #00868b
load symbol X0Y29 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y29 X0Y29 syn -hier QuadX0Y7 -pg 1 -y 1466 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y29} -attr @fillcolor #7a7a7a
load inst cpll.X0Y28 CPLL_X0 syn -hier QuadX0Y7 -pg 1 -y 1551 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y28 A} -attr @name {}
attribute {pin cpll.X0Y28 B} -attr @name {}
attribute {inst cpll.X0Y28} -attr @fillcolor #00868b
load symbol X0Y28 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y28 X0Y28 syn -hier QuadX0Y7 -pg 1 -y 1551 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y28} -attr @fillcolor #7a7a7a
load port QuadX0Y7_clk0 in -pg 1 -y 1265 -x 1 -attr @fillcolor #3a5fcd
load port QuadX0Y7_clk1 in -pg 1 -y 1435 -x 1 -attr @fillcolor #3a5fcd
load inst QuadX0Y6 QUAD_X0 v -pg 1 -y 1687 -x 2000 -autohide -attr @cell QuadX0Y6 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin QuadX0Y6 QPLL0 } -attr @name {}
attribute {hierPin QuadX0Y6 QPLL0 } -attr @name {}
attribute {pin QuadX0Y6 QPLL1 } -attr @name {}
attribute {hierPin QuadX0Y6 QPLL1 } -attr @name {}
attribute {pin QuadX0Y6 a0 } -attr @name {}
attribute {hierPin QuadX0Y6 a0 } -attr @name {}
attribute {pin QuadX0Y6 a1 } -attr @name {}
attribute {hierPin QuadX0Y6 a1 } -attr @name {}
attribute {pin QuadX0Y6 a2 } -attr @name {}
attribute {hierPin QuadX0Y6 a2 } -attr @name {}
attribute {pin QuadX0Y6 a3 } -attr @name {}
attribute {hierPin QuadX0Y6 a3 } -attr @name {}
attribute {pin QuadX0Y6 RECCLK_clk0 } -attr @name {}
attribute {hierPin QuadX0Y6 RECCLK_clk0 } -attr @name {}
attribute {pin QuadX0Y6 RECCLK_clk1 } -attr @name {}
attribute {hierPin QuadX0Y6 RECCLK_clk1 } -attr @name {}
load inst cpll.X0Y27 CPLL_X0 syn -hier QuadX0Y6 -pg 1 -y 1688 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y27 A} -attr @name {}
attribute {pin cpll.X0Y27 B} -attr @name {}
attribute {inst cpll.X0Y27} -attr @fillcolor #00868b
load symbol X0Y27 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y27 X0Y27 syn -hier QuadX0Y6 -pg 1 -y 1688 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y27} -attr @fillcolor #7a7a7a
load inst cpll.X0Y26 CPLL_X0 syn -hier QuadX0Y6 -pg 1 -y 1773 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y26 A} -attr @name {}
attribute {pin cpll.X0Y26 B} -attr @name {}
attribute {inst cpll.X0Y26} -attr @fillcolor #00868b
load symbol X0Y26 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y26 X0Y26 syn -hier QuadX0Y6 -pg 1 -y 1773 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y26} -attr @fillcolor #7a7a7a
load inst QPLL0.QuadX0Y6 QPLL0_X0 syn -hier QuadX0Y6 -pg 1 -y 1858 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL0.QuadX0Y6 A} -attr @name {}
attribute {pin QPLL0.QuadX0Y6 B} -attr @name {}
attribute {inst QPLL0.QuadX0Y6} -attr @fillcolor #00868b
load inst QPLL1.QuadX0Y6 QPLL1_X0 syn -hier QuadX0Y6 -pg 1 -y 1943 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL1.QuadX0Y6 A} -attr @name {}
attribute {pin QPLL1.QuadX0Y6 B} -attr @name {}
attribute {inst QPLL1.QuadX0Y6} -attr @fillcolor #00868b
load inst cpll.X0Y25 CPLL_X0 syn -hier QuadX0Y6 -pg 1 -y 2028 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y25 A} -attr @name {}
attribute {pin cpll.X0Y25 B} -attr @name {}
attribute {inst cpll.X0Y25} -attr @fillcolor #00868b
load symbol X0Y25 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y25 X0Y25 syn -hier QuadX0Y6 -pg 1 -y 2028 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y25} -attr @fillcolor #7a7a7a
load inst cpll.X0Y24 CPLL_X0 syn -hier QuadX0Y6 -pg 1 -y 2113 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y24 A} -attr @name {}
attribute {pin cpll.X0Y24 B} -attr @name {}
attribute {inst cpll.X0Y24} -attr @fillcolor #00868b
load symbol X0Y24 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y24 X0Y24 syn -hier QuadX0Y6 -pg 1 -y 2113 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y24} -attr @fillcolor #7a7a7a
load port QuadX0Y6_clk0 in -pg 1 -y 1827 -x 1 -attr @fillcolor #3a5fcd
load port QuadX0Y6_clk1 in -pg 1 -y 1997 -x 1 -attr @fillcolor #3a5fcd
load inst QuadX0Y5 QUAD_X0 v -pg 1 -y 2249 -x 2000 -autohide -attr @cell QuadX0Y5 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin QuadX0Y5 QPLL0 } -attr @name {}
attribute {hierPin QuadX0Y5 QPLL0 } -attr @name {}
attribute {pin QuadX0Y5 QPLL1 } -attr @name {}
attribute {hierPin QuadX0Y5 QPLL1 } -attr @name {}
attribute {pin QuadX0Y5 a0 } -attr @name {}
attribute {hierPin QuadX0Y5 a0 } -attr @name {}
attribute {pin QuadX0Y5 a1 } -attr @name {}
attribute {hierPin QuadX0Y5 a1 } -attr @name {}
attribute {pin QuadX0Y5 a2 } -attr @name {}
attribute {hierPin QuadX0Y5 a2 } -attr @name {}
attribute {pin QuadX0Y5 a3 } -attr @name {}
attribute {hierPin QuadX0Y5 a3 } -attr @name {}
attribute {pin QuadX0Y5 RECCLK_clk0 } -attr @name {}
attribute {hierPin QuadX0Y5 RECCLK_clk0 } -attr @name {}
attribute {pin QuadX0Y5 RECCLK_clk1 } -attr @name {}
attribute {hierPin QuadX0Y5 RECCLK_clk1 } -attr @name {}
load inst cpll.X0Y23 CPLL_X0 syn -hier QuadX0Y5 -pg 1 -y 2250 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y23 A} -attr @name {}
attribute {pin cpll.X0Y23 B} -attr @name {}
attribute {inst cpll.X0Y23} -attr @fillcolor #00868b
load symbol X0Y23 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y23 X0Y23 syn -hier QuadX0Y5 -pg 1 -y 2250 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y23} -attr @fillcolor #7a7a7a
load inst cpll.X0Y22 CPLL_X0 syn -hier QuadX0Y5 -pg 1 -y 2335 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y22 A} -attr @name {}
attribute {pin cpll.X0Y22 B} -attr @name {}
attribute {inst cpll.X0Y22} -attr @fillcolor #00868b
load symbol X0Y22 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y22 X0Y22 syn -hier QuadX0Y5 -pg 1 -y 2335 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y22} -attr @fillcolor #7a7a7a
load inst QPLL0.QuadX0Y5 QPLL0_X0 syn -hier QuadX0Y5 -pg 1 -y 2420 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL0.QuadX0Y5 A} -attr @name {}
attribute {pin QPLL0.QuadX0Y5 B} -attr @name {}
attribute {inst QPLL0.QuadX0Y5} -attr @fillcolor #00868b
load inst QPLL1.QuadX0Y5 QPLL1_X0 syn -hier QuadX0Y5 -pg 1 -y 2505 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL1.QuadX0Y5 A} -attr @name {}
attribute {pin QPLL1.QuadX0Y5 B} -attr @name {}
attribute {inst QPLL1.QuadX0Y5} -attr @fillcolor #00868b
load inst cpll.X0Y21 CPLL_X0 syn -hier QuadX0Y5 -pg 1 -y 2590 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y21 A} -attr @name {}
attribute {pin cpll.X0Y21 B} -attr @name {}
attribute {inst cpll.X0Y21} -attr @fillcolor #00868b
load symbol X0Y21 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y21 X0Y21 syn -hier QuadX0Y5 -pg 1 -y 2590 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y21} -attr @fillcolor #7a7a7a
load inst cpll.X0Y20 CPLL_X0 syn -hier QuadX0Y5 -pg 1 -y 2675 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y20 A} -attr @name {}
attribute {pin cpll.X0Y20 B} -attr @name {}
attribute {inst cpll.X0Y20} -attr @fillcolor #00868b
load symbol X0Y20 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y20 X0Y20 syn -hier QuadX0Y5 -pg 1 -y 2675 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y20} -attr @fillcolor #7a7a7a
load port QuadX0Y5_clk0 in -pg 1 -y 2389 -x 1 -attr @fillcolor #3a5fcd
load port QuadX0Y5_clk1 in -pg 1 -y 2559 -x 1 -attr @fillcolor #3a5fcd
load inst QuadX0Y4 QUAD_X0 v -pg 1 -y 2811 -x 2000 -autohide -attr @cell QuadX0Y4 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin QuadX0Y4 QPLL0 } -attr @name {}
attribute {hierPin QuadX0Y4 QPLL0 } -attr @name {}
attribute {pin QuadX0Y4 QPLL1 } -attr @name {}
attribute {hierPin QuadX0Y4 QPLL1 } -attr @name {}
attribute {pin QuadX0Y4 a0 } -attr @name {}
attribute {hierPin QuadX0Y4 a0 } -attr @name {}
attribute {pin QuadX0Y4 a1 } -attr @name {}
attribute {hierPin QuadX0Y4 a1 } -attr @name {}
attribute {pin QuadX0Y4 a2 } -attr @name {}
attribute {hierPin QuadX0Y4 a2 } -attr @name {}
attribute {pin QuadX0Y4 a3 } -attr @name {}
attribute {hierPin QuadX0Y4 a3 } -attr @name {}
attribute {pin QuadX0Y4 RECCLK_clk0 } -attr @name {}
attribute {hierPin QuadX0Y4 RECCLK_clk0 } -attr @name {}
attribute {pin QuadX0Y4 RECCLK_clk1 } -attr @name {}
attribute {hierPin QuadX0Y4 RECCLK_clk1 } -attr @name {}
load inst cpll.X0Y19 CPLL_X0 syn -hier QuadX0Y4 -pg 1 -y 2812 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y19 A} -attr @name {}
attribute {pin cpll.X0Y19 B} -attr @name {}
attribute {inst cpll.X0Y19} -attr @fillcolor #00868b
load symbol X0Y19 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y19 X0Y19 syn -hier QuadX0Y4 -pg 1 -y 2812 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y19} -attr @fillcolor #7a7a7a
load inst cpll.X0Y18 CPLL_X0 syn -hier QuadX0Y4 -pg 1 -y 2897 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y18 A} -attr @name {}
attribute {pin cpll.X0Y18 B} -attr @name {}
attribute {inst cpll.X0Y18} -attr @fillcolor #00868b
load symbol X0Y18 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y18 X0Y18 syn -hier QuadX0Y4 -pg 1 -y 2897 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y18} -attr @fillcolor #7a7a7a
load inst QPLL0.QuadX0Y4 QPLL0_X0 syn -hier QuadX0Y4 -pg 1 -y 2982 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL0.QuadX0Y4 A} -attr @name {}
attribute {pin QPLL0.QuadX0Y4 B} -attr @name {}
attribute {inst QPLL0.QuadX0Y4} -attr @fillcolor #00868b
load inst QPLL1.QuadX0Y4 QPLL1_X0 syn -hier QuadX0Y4 -pg 1 -y 3067 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL1.QuadX0Y4 A} -attr @name {}
attribute {pin QPLL1.QuadX0Y4 B} -attr @name {}
attribute {inst QPLL1.QuadX0Y4} -attr @fillcolor #00868b
load inst cpll.X0Y17 CPLL_X0 syn -hier QuadX0Y4 -pg 1 -y 3152 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y17 A} -attr @name {}
attribute {pin cpll.X0Y17 B} -attr @name {}
attribute {inst cpll.X0Y17} -attr @fillcolor #00868b
load symbol X0Y17 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y17 X0Y17 syn -hier QuadX0Y4 -pg 1 -y 3152 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y17} -attr @fillcolor #7a7a7a
load inst cpll.X0Y16 CPLL_X0 syn -hier QuadX0Y4 -pg 1 -y 3237 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y16 A} -attr @name {}
attribute {pin cpll.X0Y16 B} -attr @name {}
attribute {inst cpll.X0Y16} -attr @fillcolor #00868b
load symbol X0Y16 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y16 X0Y16 syn -hier QuadX0Y4 -pg 1 -y 3237 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y16} -attr @fillcolor #7a7a7a
load port QuadX0Y4_clk0 in -pg 1 -y 2951 -x 1 -attr @fillcolor #3a5fcd
load port QuadX0Y4_clk1 in -pg 1 -y 3121 -x 1 -attr @fillcolor #3a5fcd
load inst QuadX0Y3 QUAD_X0 v -pg 1 -y 3373 -x 2000 -autohide -attr @cell QuadX0Y3 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin QuadX0Y3 QPLL0 } -attr @name {}
attribute {hierPin QuadX0Y3 QPLL0 } -attr @name {}
attribute {pin QuadX0Y3 QPLL1 } -attr @name {}
attribute {hierPin QuadX0Y3 QPLL1 } -attr @name {}
attribute {pin QuadX0Y3 a0 } -attr @name {}
attribute {hierPin QuadX0Y3 a0 } -attr @name {}
attribute {pin QuadX0Y3 a1 } -attr @name {}
attribute {hierPin QuadX0Y3 a1 } -attr @name {}
attribute {pin QuadX0Y3 a2 } -attr @name {}
attribute {hierPin QuadX0Y3 a2 } -attr @name {}
attribute {pin QuadX0Y3 a3 } -attr @name {}
attribute {hierPin QuadX0Y3 a3 } -attr @name {}
attribute {pin QuadX0Y3 RECCLK_clk0 } -attr @name {}
attribute {hierPin QuadX0Y3 RECCLK_clk0 } -attr @name {}
attribute {pin QuadX0Y3 RECCLK_clk1 } -attr @name {}
attribute {hierPin QuadX0Y3 RECCLK_clk1 } -attr @name {}
load inst cpll.X0Y15 CPLL_X0 syn -hier QuadX0Y3 -pg 1 -y 3374 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y15 A} -attr @name {}
attribute {pin cpll.X0Y15 B} -attr @name {}
attribute {inst cpll.X0Y15} -attr @fillcolor #00868b
load symbol X0Y15 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y15 X0Y15 syn -hier QuadX0Y3 -pg 1 -y 3374 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y15} -attr @fillcolor #7a7a7a
load inst cpll.X0Y14 CPLL_X0 syn -hier QuadX0Y3 -pg 1 -y 3459 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y14 A} -attr @name {}
attribute {pin cpll.X0Y14 B} -attr @name {}
attribute {inst cpll.X0Y14} -attr @fillcolor #00868b
load symbol X0Y14 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y14 X0Y14 syn -hier QuadX0Y3 -pg 1 -y 3459 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y14} -attr @fillcolor #7a7a7a
load inst QPLL0.QuadX0Y3 QPLL0_X0 syn -hier QuadX0Y3 -pg 1 -y 3544 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL0.QuadX0Y3 A} -attr @name {}
attribute {pin QPLL0.QuadX0Y3 B} -attr @name {}
attribute {inst QPLL0.QuadX0Y3} -attr @fillcolor #00868b
load inst QPLL1.QuadX0Y3 QPLL1_X0 syn -hier QuadX0Y3 -pg 1 -y 3629 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL1.QuadX0Y3 A} -attr @name {}
attribute {pin QPLL1.QuadX0Y3 B} -attr @name {}
attribute {inst QPLL1.QuadX0Y3} -attr @fillcolor #00868b
load inst cpll.X0Y13 CPLL_X0 syn -hier QuadX0Y3 -pg 1 -y 3714 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y13 A} -attr @name {}
attribute {pin cpll.X0Y13 B} -attr @name {}
attribute {inst cpll.X0Y13} -attr @fillcolor #00868b
load symbol X0Y13 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y13 X0Y13 syn -hier QuadX0Y3 -pg 1 -y 3714 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y13} -attr @fillcolor #7a7a7a
load inst cpll.X0Y12 CPLL_X0 syn -hier QuadX0Y3 -pg 1 -y 3799 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y12 A} -attr @name {}
attribute {pin cpll.X0Y12 B} -attr @name {}
attribute {inst cpll.X0Y12} -attr @fillcolor #00868b
load symbol X0Y12 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y12 X0Y12 syn -hier QuadX0Y3 -pg 1 -y 3799 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y12} -attr @fillcolor #7a7a7a
load port QuadX0Y3_clk0 in -pg 1 -y 3513 -x 1 -attr @fillcolor #3a5fcd
load port QuadX0Y3_clk1 in -pg 1 -y 3683 -x 1 -attr @fillcolor #3a5fcd
load inst QuadX0Y2 QUAD_X0 v -pg 1 -y 3935 -x 2000 -autohide -attr @cell QuadX0Y2 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin QuadX0Y2 QPLL0 } -attr @name {}
attribute {hierPin QuadX0Y2 QPLL0 } -attr @name {}
attribute {pin QuadX0Y2 QPLL1 } -attr @name {}
attribute {hierPin QuadX0Y2 QPLL1 } -attr @name {}
attribute {pin QuadX0Y2 a0 } -attr @name {}
attribute {hierPin QuadX0Y2 a0 } -attr @name {}
attribute {pin QuadX0Y2 a1 } -attr @name {}
attribute {hierPin QuadX0Y2 a1 } -attr @name {}
attribute {pin QuadX0Y2 a2 } -attr @name {}
attribute {hierPin QuadX0Y2 a2 } -attr @name {}
attribute {pin QuadX0Y2 a3 } -attr @name {}
attribute {hierPin QuadX0Y2 a3 } -attr @name {}
attribute {pin QuadX0Y2 RECCLK_clk0 } -attr @name {}
attribute {hierPin QuadX0Y2 RECCLK_clk0 } -attr @name {}
attribute {pin QuadX0Y2 RECCLK_clk1 } -attr @name {}
attribute {hierPin QuadX0Y2 RECCLK_clk1 } -attr @name {}
load inst cpll.X0Y11 CPLL_X0 syn -hier QuadX0Y2 -pg 1 -y 3936 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y11 A} -attr @name {}
attribute {pin cpll.X0Y11 B} -attr @name {}
attribute {inst cpll.X0Y11} -attr @fillcolor #00868b
load symbol X0Y11 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y11 X0Y11 syn -hier QuadX0Y2 -pg 1 -y 3936 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y11} -attr @fillcolor #7a7a7a
load inst cpll.X0Y10 CPLL_X0 syn -hier QuadX0Y2 -pg 1 -y 4021 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y10 A} -attr @name {}
attribute {pin cpll.X0Y10 B} -attr @name {}
attribute {inst cpll.X0Y10} -attr @fillcolor #00868b
load symbol X0Y10 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y10 X0Y10 syn -hier QuadX0Y2 -pg 1 -y 4021 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y10} -attr @fillcolor #7a7a7a
load inst QPLL0.QuadX0Y2 QPLL0_X0 syn -hier QuadX0Y2 -pg 1 -y 4106 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL0.QuadX0Y2 A} -attr @name {}
attribute {pin QPLL0.QuadX0Y2 B} -attr @name {}
attribute {inst QPLL0.QuadX0Y2} -attr @fillcolor #00868b
load inst QPLL1.QuadX0Y2 QPLL1_X0 syn -hier QuadX0Y2 -pg 1 -y 4191 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL1.QuadX0Y2 A} -attr @name {}
attribute {pin QPLL1.QuadX0Y2 B} -attr @name {}
attribute {inst QPLL1.QuadX0Y2} -attr @fillcolor #00868b
load inst cpll.X0Y9 CPLL_X0 syn -hier QuadX0Y2 -pg 1 -y 4276 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y9 A} -attr @name {}
attribute {pin cpll.X0Y9 B} -attr @name {}
attribute {inst cpll.X0Y9} -attr @fillcolor #00868b
load symbol X0Y9 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y9 X0Y9 syn -hier QuadX0Y2 -pg 1 -y 4276 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y9} -attr @fillcolor #7a7a7a
load inst cpll.X0Y8 CPLL_X0 syn -hier QuadX0Y2 -pg 1 -y 4361 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y8 A} -attr @name {}
attribute {pin cpll.X0Y8 B} -attr @name {}
attribute {inst cpll.X0Y8} -attr @fillcolor #00868b
load symbol X0Y8 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y8 X0Y8 syn -hier QuadX0Y2 -pg 1 -y 4361 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y8} -attr @fillcolor #7a7a7a
load port QuadX0Y2_clk0 in -pg 1 -y 4075 -x 1 -attr @fillcolor #3a5fcd
load port QuadX0Y2_clk1 in -pg 1 -y 4245 -x 1 -attr @fillcolor #3a5fcd
load inst QuadX0Y1 QUAD_X0 v -pg 1 -y 4497 -x 2000 -autohide -attr @cell QuadX0Y1 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin QuadX0Y1 QPLL0 } -attr @name {}
attribute {hierPin QuadX0Y1 QPLL0 } -attr @name {}
attribute {pin QuadX0Y1 QPLL1 } -attr @name {}
attribute {hierPin QuadX0Y1 QPLL1 } -attr @name {}
attribute {pin QuadX0Y1 a0 } -attr @name {}
attribute {hierPin QuadX0Y1 a0 } -attr @name {}
attribute {pin QuadX0Y1 a1 } -attr @name {}
attribute {hierPin QuadX0Y1 a1 } -attr @name {}
attribute {pin QuadX0Y1 a2 } -attr @name {}
attribute {hierPin QuadX0Y1 a2 } -attr @name {}
attribute {pin QuadX0Y1 a3 } -attr @name {}
attribute {hierPin QuadX0Y1 a3 } -attr @name {}
attribute {pin QuadX0Y1 RECCLK_clk0 } -attr @name {}
attribute {hierPin QuadX0Y1 RECCLK_clk0 } -attr @name {}
attribute {pin QuadX0Y1 RECCLK_clk1 } -attr @name {}
attribute {hierPin QuadX0Y1 RECCLK_clk1 } -attr @name {}
load inst cpll.X0Y7 CPLL_X0 syn -hier QuadX0Y1 -pg 1 -y 4498 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y7 A} -attr @name {}
attribute {pin cpll.X0Y7 B} -attr @name {}
attribute {inst cpll.X0Y7} -attr @fillcolor #00868b
load symbol X0Y7 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y7 X0Y7 syn -hier QuadX0Y1 -pg 1 -y 4498 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y7} -attr @fillcolor #7a7a7a
load inst cpll.X0Y6 CPLL_X0 syn -hier QuadX0Y1 -pg 1 -y 4583 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y6 A} -attr @name {}
attribute {pin cpll.X0Y6 B} -attr @name {}
attribute {inst cpll.X0Y6} -attr @fillcolor #00868b
load symbol X0Y6 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y6 X0Y6 syn -hier QuadX0Y1 -pg 1 -y 4583 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y6} -attr @fillcolor #7a7a7a
load inst QPLL0.QuadX0Y1 QPLL0_X0 syn -hier QuadX0Y1 -pg 1 -y 4668 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL0.QuadX0Y1 A} -attr @name {}
attribute {pin QPLL0.QuadX0Y1 B} -attr @name {}
attribute {inst QPLL0.QuadX0Y1} -attr @fillcolor #00868b
load inst QPLL1.QuadX0Y1 QPLL1_X0 syn -hier QuadX0Y1 -pg 1 -y 4753 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL1.QuadX0Y1 A} -attr @name {}
attribute {pin QPLL1.QuadX0Y1 B} -attr @name {}
attribute {inst QPLL1.QuadX0Y1} -attr @fillcolor #00868b
load inst cpll.X0Y5 CPLL_X0 syn -hier QuadX0Y1 -pg 1 -y 4838 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y5 A} -attr @name {}
attribute {pin cpll.X0Y5 B} -attr @name {}
attribute {inst cpll.X0Y5} -attr @fillcolor #00868b
load symbol X0Y5 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y5 X0Y5 syn -hier QuadX0Y1 -pg 1 -y 4838 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y5} -attr @fillcolor #7a7a7a
load inst cpll.X0Y4 CPLL_X0 syn -hier QuadX0Y1 -pg 1 -y 4923 -x 1 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X0Y4 A} -attr @name {}
attribute {pin cpll.X0Y4 B} -attr @name {}
attribute {inst cpll.X0Y4} -attr @fillcolor #00868b
load symbol X0Y4 syn HIERGEN port TX in port RX in port RXRECCLK out
load inst GT.X0Y4 X0Y4 syn -hier QuadX0Y1 -pg 1 -y 4923 -x 2000 -autohide -attr @name {}
attribute {inst GT.X0Y4} -attr @fillcolor #7a7a7a
load port QuadX0Y1_clk0 in -pg 1 -y 4637 -x 1 -attr @fillcolor #3a5fcd
load port QuadX0Y1_clk1 in -pg 1 -y 4807 -x 1 -attr @fillcolor #3a5fcd
load inst QuadX1Y14 QUAD_X1 v -pg 1 -y 1 -x 12000 -autohide -attr @cell QuadX1Y14 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin QuadX1Y14 QPLL0 } -attr @name {}
attribute {hierPin QuadX1Y14 QPLL0 } -attr @name {}
attribute {pin QuadX1Y14 QPLL1 } -attr @name {}
attribute {hierPin QuadX1Y14 QPLL1 } -attr @name {}
attribute {pin QuadX1Y14 a0 } -attr @name {}
attribute {hierPin QuadX1Y14 a0 } -attr @name {}
attribute {pin QuadX1Y14 a1 } -attr @name {}
attribute {hierPin QuadX1Y14 a1 } -attr @name {}
attribute {pin QuadX1Y14 a2 } -attr @name {}
attribute {hierPin QuadX1Y14 a2 } -attr @name {}
attribute {pin QuadX1Y14 a3 } -attr @name {}
attribute {hierPin QuadX1Y14 a3 } -attr @name {}
attribute {pin QuadX1Y14 RECCLK_clk0 } -attr @name {}
attribute {hierPin QuadX1Y14 RECCLK_clk0 } -attr @name {}
attribute {pin QuadX1Y14 RECCLK_clk1 } -attr @name {}
attribute {hierPin QuadX1Y14 RECCLK_clk1 } -attr @name {}
load inst cpll.X1Y59 CPLL_X1 syn -hier QuadX1Y14 -pg 1 -y 2 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y59 A} -attr @name {}
attribute {pin cpll.X1Y59 B} -attr @name {}
attribute {inst cpll.X1Y59} -attr @fillcolor #00868b
load symbol X1Y59 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y59 X1Y59 syn -hier QuadX1Y14 -pg 1 -y 2 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y59} -attr @fillcolor #7a7a7a
load inst cpll.X1Y58 CPLL_X1 syn -hier QuadX1Y14 -pg 1 -y 87 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y58 A} -attr @name {}
attribute {pin cpll.X1Y58 B} -attr @name {}
attribute {inst cpll.X1Y58} -attr @fillcolor #00868b
load symbol X1Y58 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y58 X1Y58 syn -hier QuadX1Y14 -pg 1 -y 87 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y58} -attr @fillcolor #7a7a7a
load inst QPLL0.QuadX1Y14 QPLL0_X1 syn -hier QuadX1Y14 -pg 1 -y 172 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL0.QuadX1Y14 A} -attr @name {}
attribute {pin QPLL0.QuadX1Y14 B} -attr @name {}
attribute {inst QPLL0.QuadX1Y14} -attr @fillcolor #00868b
load inst QPLL1.QuadX1Y14 QPLL1_X1 syn -hier QuadX1Y14 -pg 1 -y 257 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL1.QuadX1Y14 A} -attr @name {}
attribute {pin QPLL1.QuadX1Y14 B} -attr @name {}
attribute {inst QPLL1.QuadX1Y14} -attr @fillcolor #00868b
load inst cpll.X1Y57 CPLL_X1 syn -hier QuadX1Y14 -pg 1 -y 342 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y57 A} -attr @name {}
attribute {pin cpll.X1Y57 B} -attr @name {}
attribute {inst cpll.X1Y57} -attr @fillcolor #00868b
load symbol X1Y57 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y57 X1Y57 syn -hier QuadX1Y14 -pg 1 -y 342 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y57} -attr @fillcolor #7a7a7a
load inst cpll.X1Y56 CPLL_X1 syn -hier QuadX1Y14 -pg 1 -y 427 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y56 A} -attr @name {}
attribute {pin cpll.X1Y56 B} -attr @name {}
attribute {inst cpll.X1Y56} -attr @fillcolor #00868b
load symbol X1Y56 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y56 X1Y56 syn -hier QuadX1Y14 -pg 1 -y 427 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y56} -attr @fillcolor #7a7a7a
load port QuadX1Y14_clk0 out -pg 1 -y 141 -x 12001 -attr @fillcolor #3a5fcd
load port QuadX1Y14_clk1 out -pg 1 -y 311 -x 12001 -attr @fillcolor #3a5fcd
load inst QuadX1Y13 QUAD_X1 v -pg 1 -y 563 -x 12000 -autohide -attr @cell QuadX1Y13 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin QuadX1Y13 QPLL0 } -attr @name {}
attribute {hierPin QuadX1Y13 QPLL0 } -attr @name {}
attribute {pin QuadX1Y13 QPLL1 } -attr @name {}
attribute {hierPin QuadX1Y13 QPLL1 } -attr @name {}
attribute {pin QuadX1Y13 a0 } -attr @name {}
attribute {hierPin QuadX1Y13 a0 } -attr @name {}
attribute {pin QuadX1Y13 a1 } -attr @name {}
attribute {hierPin QuadX1Y13 a1 } -attr @name {}
attribute {pin QuadX1Y13 a2 } -attr @name {}
attribute {hierPin QuadX1Y13 a2 } -attr @name {}
attribute {pin QuadX1Y13 a3 } -attr @name {}
attribute {hierPin QuadX1Y13 a3 } -attr @name {}
attribute {pin QuadX1Y13 RECCLK_clk0 } -attr @name {}
attribute {hierPin QuadX1Y13 RECCLK_clk0 } -attr @name {}
attribute {pin QuadX1Y13 RECCLK_clk1 } -attr @name {}
attribute {hierPin QuadX1Y13 RECCLK_clk1 } -attr @name {}
load inst cpll.X1Y55 CPLL_X1 syn -hier QuadX1Y13 -pg 1 -y 564 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y55 A} -attr @name {}
attribute {pin cpll.X1Y55 B} -attr @name {}
attribute {inst cpll.X1Y55} -attr @fillcolor #00868b
load symbol X1Y55 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y55 X1Y55 syn -hier QuadX1Y13 -pg 1 -y 564 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y55} -attr @fillcolor #7a7a7a
load inst cpll.X1Y54 CPLL_X1 syn -hier QuadX1Y13 -pg 1 -y 649 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y54 A} -attr @name {}
attribute {pin cpll.X1Y54 B} -attr @name {}
attribute {inst cpll.X1Y54} -attr @fillcolor #00868b
load symbol X1Y54 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y54 X1Y54 syn -hier QuadX1Y13 -pg 1 -y 649 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y54} -attr @fillcolor #7a7a7a
load inst QPLL0.QuadX1Y13 QPLL0_X1 syn -hier QuadX1Y13 -pg 1 -y 734 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL0.QuadX1Y13 A} -attr @name {}
attribute {pin QPLL0.QuadX1Y13 B} -attr @name {}
attribute {inst QPLL0.QuadX1Y13} -attr @fillcolor #00868b
load inst QPLL1.QuadX1Y13 QPLL1_X1 syn -hier QuadX1Y13 -pg 1 -y 819 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL1.QuadX1Y13 A} -attr @name {}
attribute {pin QPLL1.QuadX1Y13 B} -attr @name {}
attribute {inst QPLL1.QuadX1Y13} -attr @fillcolor #00868b
load inst cpll.X1Y53 CPLL_X1 syn -hier QuadX1Y13 -pg 1 -y 904 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y53 A} -attr @name {}
attribute {pin cpll.X1Y53 B} -attr @name {}
attribute {inst cpll.X1Y53} -attr @fillcolor #00868b
load symbol X1Y53 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y53 X1Y53 syn -hier QuadX1Y13 -pg 1 -y 904 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y53} -attr @fillcolor #7a7a7a
load inst cpll.X1Y52 CPLL_X1 syn -hier QuadX1Y13 -pg 1 -y 989 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y52 A} -attr @name {}
attribute {pin cpll.X1Y52 B} -attr @name {}
attribute {inst cpll.X1Y52} -attr @fillcolor #00868b
load symbol X1Y52 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y52 X1Y52 syn -hier QuadX1Y13 -pg 1 -y 989 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y52} -attr @fillcolor #7a7a7a
load port QuadX1Y13_clk0 out -pg 1 -y 703 -x 12001 -attr @fillcolor #3a5fcd
load port QuadX1Y13_clk1 out -pg 1 -y 873 -x 12001 -attr @fillcolor #3a5fcd
load inst QuadX1Y12 QUAD_X1 v -pg 1 -y 1125 -x 12000 -autohide -attr @cell QuadX1Y12 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin QuadX1Y12 QPLL0 } -attr @name {}
attribute {hierPin QuadX1Y12 QPLL0 } -attr @name {}
attribute {pin QuadX1Y12 QPLL1 } -attr @name {}
attribute {hierPin QuadX1Y12 QPLL1 } -attr @name {}
attribute {pin QuadX1Y12 a0 } -attr @name {}
attribute {hierPin QuadX1Y12 a0 } -attr @name {}
attribute {pin QuadX1Y12 a1 } -attr @name {}
attribute {hierPin QuadX1Y12 a1 } -attr @name {}
attribute {pin QuadX1Y12 a2 } -attr @name {}
attribute {hierPin QuadX1Y12 a2 } -attr @name {}
attribute {pin QuadX1Y12 a3 } -attr @name {}
attribute {hierPin QuadX1Y12 a3 } -attr @name {}
attribute {pin QuadX1Y12 RECCLK_clk0 } -attr @name {}
attribute {hierPin QuadX1Y12 RECCLK_clk0 } -attr @name {}
attribute {pin QuadX1Y12 RECCLK_clk1 } -attr @name {}
attribute {hierPin QuadX1Y12 RECCLK_clk1 } -attr @name {}
load inst cpll.X1Y51 CPLL_X1 syn -hier QuadX1Y12 -pg 1 -y 1126 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y51 A} -attr @name {}
attribute {pin cpll.X1Y51 B} -attr @name {}
attribute {inst cpll.X1Y51} -attr @fillcolor #00868b
load symbol X1Y51 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y51 X1Y51 syn -hier QuadX1Y12 -pg 1 -y 1126 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y51} -attr @fillcolor #7a7a7a
load inst cpll.X1Y50 CPLL_X1 syn -hier QuadX1Y12 -pg 1 -y 1211 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y50 A} -attr @name {}
attribute {pin cpll.X1Y50 B} -attr @name {}
attribute {inst cpll.X1Y50} -attr @fillcolor #00868b
load symbol X1Y50 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y50 X1Y50 syn -hier QuadX1Y12 -pg 1 -y 1211 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y50} -attr @fillcolor #7a7a7a
load inst QPLL0.QuadX1Y12 QPLL0_X1 syn -hier QuadX1Y12 -pg 1 -y 1296 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL0.QuadX1Y12 A} -attr @name {}
attribute {pin QPLL0.QuadX1Y12 B} -attr @name {}
attribute {inst QPLL0.QuadX1Y12} -attr @fillcolor #00868b
load inst QPLL1.QuadX1Y12 QPLL1_X1 syn -hier QuadX1Y12 -pg 1 -y 1381 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL1.QuadX1Y12 A} -attr @name {}
attribute {pin QPLL1.QuadX1Y12 B} -attr @name {}
attribute {inst QPLL1.QuadX1Y12} -attr @fillcolor #00868b
load inst cpll.X1Y49 CPLL_X1 syn -hier QuadX1Y12 -pg 1 -y 1466 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y49 A} -attr @name {}
attribute {pin cpll.X1Y49 B} -attr @name {}
attribute {inst cpll.X1Y49} -attr @fillcolor #00868b
load symbol X1Y49 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y49 X1Y49 syn -hier QuadX1Y12 -pg 1 -y 1466 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y49} -attr @fillcolor #7a7a7a
load inst cpll.X1Y48 CPLL_X1 syn -hier QuadX1Y12 -pg 1 -y 1551 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y48 A} -attr @name {}
attribute {pin cpll.X1Y48 B} -attr @name {}
attribute {inst cpll.X1Y48} -attr @fillcolor #00868b
load symbol X1Y48 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y48 X1Y48 syn -hier QuadX1Y12 -pg 1 -y 1551 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y48} -attr @fillcolor #7a7a7a
load port QuadX1Y12_clk0 out -pg 1 -y 1265 -x 12001 -attr @fillcolor #3a5fcd
load port QuadX1Y12_clk1 out -pg 1 -y 1435 -x 12001 -attr @fillcolor #3a5fcd
load inst QuadX1Y11 QUAD_X1 v -pg 1 -y 1687 -x 12000 -autohide -attr @cell QuadX1Y11 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin QuadX1Y11 QPLL0 } -attr @name {}
attribute {hierPin QuadX1Y11 QPLL0 } -attr @name {}
attribute {pin QuadX1Y11 QPLL1 } -attr @name {}
attribute {hierPin QuadX1Y11 QPLL1 } -attr @name {}
attribute {pin QuadX1Y11 a0 } -attr @name {}
attribute {hierPin QuadX1Y11 a0 } -attr @name {}
attribute {pin QuadX1Y11 a1 } -attr @name {}
attribute {hierPin QuadX1Y11 a1 } -attr @name {}
attribute {pin QuadX1Y11 a2 } -attr @name {}
attribute {hierPin QuadX1Y11 a2 } -attr @name {}
attribute {pin QuadX1Y11 a3 } -attr @name {}
attribute {hierPin QuadX1Y11 a3 } -attr @name {}
attribute {pin QuadX1Y11 RECCLK_clk0 } -attr @name {}
attribute {hierPin QuadX1Y11 RECCLK_clk0 } -attr @name {}
attribute {pin QuadX1Y11 RECCLK_clk1 } -attr @name {}
attribute {hierPin QuadX1Y11 RECCLK_clk1 } -attr @name {}
load inst cpll.X1Y47 CPLL_X1 syn -hier QuadX1Y11 -pg 1 -y 1688 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y47 A} -attr @name {}
attribute {pin cpll.X1Y47 B} -attr @name {}
attribute {inst cpll.X1Y47} -attr @fillcolor #00868b
load symbol X1Y47 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y47 X1Y47 syn -hier QuadX1Y11 -pg 1 -y 1688 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y47} -attr @fillcolor #7a7a7a
load inst cpll.X1Y46 CPLL_X1 syn -hier QuadX1Y11 -pg 1 -y 1773 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y46 A} -attr @name {}
attribute {pin cpll.X1Y46 B} -attr @name {}
attribute {inst cpll.X1Y46} -attr @fillcolor #00868b
load symbol X1Y46 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y46 X1Y46 syn -hier QuadX1Y11 -pg 1 -y 1773 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y46} -attr @fillcolor #7a7a7a
load inst QPLL0.QuadX1Y11 QPLL0_X1 syn -hier QuadX1Y11 -pg 1 -y 1858 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL0.QuadX1Y11 A} -attr @name {}
attribute {pin QPLL0.QuadX1Y11 B} -attr @name {}
attribute {inst QPLL0.QuadX1Y11} -attr @fillcolor #00868b
load inst QPLL1.QuadX1Y11 QPLL1_X1 syn -hier QuadX1Y11 -pg 1 -y 1943 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL1.QuadX1Y11 A} -attr @name {}
attribute {pin QPLL1.QuadX1Y11 B} -attr @name {}
attribute {inst QPLL1.QuadX1Y11} -attr @fillcolor #00868b
load inst cpll.X1Y45 CPLL_X1 syn -hier QuadX1Y11 -pg 1 -y 2028 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y45 A} -attr @name {}
attribute {pin cpll.X1Y45 B} -attr @name {}
attribute {inst cpll.X1Y45} -attr @fillcolor #00868b
load symbol X1Y45 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y45 X1Y45 syn -hier QuadX1Y11 -pg 1 -y 2028 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y45} -attr @fillcolor #7a7a7a
load inst cpll.X1Y44 CPLL_X1 syn -hier QuadX1Y11 -pg 1 -y 2113 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y44 A} -attr @name {}
attribute {pin cpll.X1Y44 B} -attr @name {}
attribute {inst cpll.X1Y44} -attr @fillcolor #00868b
load symbol X1Y44 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y44 X1Y44 syn -hier QuadX1Y11 -pg 1 -y 2113 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y44} -attr @fillcolor #7a7a7a
load port QuadX1Y11_clk0 out -pg 1 -y 1827 -x 12001 -attr @fillcolor #3a5fcd
load port QuadX1Y11_clk1 out -pg 1 -y 1997 -x 12001 -attr @fillcolor #3a5fcd
load inst QuadX1Y10 QUAD_X1 v -pg 1 -y 2249 -x 12000 -autohide -attr @cell QuadX1Y10 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin QuadX1Y10 QPLL0 } -attr @name {}
attribute {hierPin QuadX1Y10 QPLL0 } -attr @name {}
attribute {pin QuadX1Y10 QPLL1 } -attr @name {}
attribute {hierPin QuadX1Y10 QPLL1 } -attr @name {}
attribute {pin QuadX1Y10 a0 } -attr @name {}
attribute {hierPin QuadX1Y10 a0 } -attr @name {}
attribute {pin QuadX1Y10 a1 } -attr @name {}
attribute {hierPin QuadX1Y10 a1 } -attr @name {}
attribute {pin QuadX1Y10 a2 } -attr @name {}
attribute {hierPin QuadX1Y10 a2 } -attr @name {}
attribute {pin QuadX1Y10 a3 } -attr @name {}
attribute {hierPin QuadX1Y10 a3 } -attr @name {}
attribute {pin QuadX1Y10 RECCLK_clk0 } -attr @name {}
attribute {hierPin QuadX1Y10 RECCLK_clk0 } -attr @name {}
attribute {pin QuadX1Y10 RECCLK_clk1 } -attr @name {}
attribute {hierPin QuadX1Y10 RECCLK_clk1 } -attr @name {}
load inst cpll.X1Y43 CPLL_X1 syn -hier QuadX1Y10 -pg 1 -y 2250 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y43 A} -attr @name {}
attribute {pin cpll.X1Y43 B} -attr @name {}
attribute {inst cpll.X1Y43} -attr @fillcolor #00868b
load symbol X1Y43 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y43 X1Y43 syn -hier QuadX1Y10 -pg 1 -y 2250 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y43} -attr @fillcolor #7a7a7a
load inst cpll.X1Y42 CPLL_X1 syn -hier QuadX1Y10 -pg 1 -y 2335 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y42 A} -attr @name {}
attribute {pin cpll.X1Y42 B} -attr @name {}
attribute {inst cpll.X1Y42} -attr @fillcolor #00868b
load symbol X1Y42 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y42 X1Y42 syn -hier QuadX1Y10 -pg 1 -y 2335 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y42} -attr @fillcolor #7a7a7a
load inst QPLL0.QuadX1Y10 QPLL0_X1 syn -hier QuadX1Y10 -pg 1 -y 2420 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL0.QuadX1Y10 A} -attr @name {}
attribute {pin QPLL0.QuadX1Y10 B} -attr @name {}
attribute {inst QPLL0.QuadX1Y10} -attr @fillcolor #00868b
load inst QPLL1.QuadX1Y10 QPLL1_X1 syn -hier QuadX1Y10 -pg 1 -y 2505 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL1.QuadX1Y10 A} -attr @name {}
attribute {pin QPLL1.QuadX1Y10 B} -attr @name {}
attribute {inst QPLL1.QuadX1Y10} -attr @fillcolor #00868b
load inst cpll.X1Y41 CPLL_X1 syn -hier QuadX1Y10 -pg 1 -y 2590 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y41 A} -attr @name {}
attribute {pin cpll.X1Y41 B} -attr @name {}
attribute {inst cpll.X1Y41} -attr @fillcolor #00868b
load symbol X1Y41 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y41 X1Y41 syn -hier QuadX1Y10 -pg 1 -y 2590 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y41} -attr @fillcolor #7a7a7a
load inst cpll.X1Y40 CPLL_X1 syn -hier QuadX1Y10 -pg 1 -y 2675 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y40 A} -attr @name {}
attribute {pin cpll.X1Y40 B} -attr @name {}
attribute {inst cpll.X1Y40} -attr @fillcolor #00868b
load symbol X1Y40 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y40 X1Y40 syn -hier QuadX1Y10 -pg 1 -y 2675 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y40} -attr @fillcolor #7a7a7a
load port QuadX1Y10_clk0 out -pg 1 -y 2389 -x 12001 -attr @fillcolor #3a5fcd
load port QuadX1Y10_clk1 out -pg 1 -y 2559 -x 12001 -attr @fillcolor #3a5fcd
load inst QuadX1Y9 QUAD_X1 v -pg 1 -y 2811 -x 12000 -autohide -attr @cell QuadX1Y9 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin QuadX1Y9 QPLL0 } -attr @name {}
attribute {hierPin QuadX1Y9 QPLL0 } -attr @name {}
attribute {pin QuadX1Y9 QPLL1 } -attr @name {}
attribute {hierPin QuadX1Y9 QPLL1 } -attr @name {}
attribute {pin QuadX1Y9 a0 } -attr @name {}
attribute {hierPin QuadX1Y9 a0 } -attr @name {}
attribute {pin QuadX1Y9 a1 } -attr @name {}
attribute {hierPin QuadX1Y9 a1 } -attr @name {}
attribute {pin QuadX1Y9 a2 } -attr @name {}
attribute {hierPin QuadX1Y9 a2 } -attr @name {}
attribute {pin QuadX1Y9 a3 } -attr @name {}
attribute {hierPin QuadX1Y9 a3 } -attr @name {}
attribute {pin QuadX1Y9 RECCLK_clk0 } -attr @name {}
attribute {hierPin QuadX1Y9 RECCLK_clk0 } -attr @name {}
attribute {pin QuadX1Y9 RECCLK_clk1 } -attr @name {}
attribute {hierPin QuadX1Y9 RECCLK_clk1 } -attr @name {}
load inst cpll.X1Y39 CPLL_X1 syn -hier QuadX1Y9 -pg 1 -y 2812 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y39 A} -attr @name {}
attribute {pin cpll.X1Y39 B} -attr @name {}
attribute {inst cpll.X1Y39} -attr @fillcolor #00868b
load symbol X1Y39 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y39 X1Y39 syn -hier QuadX1Y9 -pg 1 -y 2812 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y39} -attr @fillcolor #7a7a7a
load inst cpll.X1Y38 CPLL_X1 syn -hier QuadX1Y9 -pg 1 -y 2897 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y38 A} -attr @name {}
attribute {pin cpll.X1Y38 B} -attr @name {}
attribute {inst cpll.X1Y38} -attr @fillcolor #00868b
load symbol X1Y38 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y38 X1Y38 syn -hier QuadX1Y9 -pg 1 -y 2897 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y38} -attr @fillcolor #7a7a7a
load inst QPLL0.QuadX1Y9 QPLL0_X1 syn -hier QuadX1Y9 -pg 1 -y 2982 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL0.QuadX1Y9 A} -attr @name {}
attribute {pin QPLL0.QuadX1Y9 B} -attr @name {}
attribute {inst QPLL0.QuadX1Y9} -attr @fillcolor #00868b
load inst QPLL1.QuadX1Y9 QPLL1_X1 syn -hier QuadX1Y9 -pg 1 -y 3067 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL1.QuadX1Y9 A} -attr @name {}
attribute {pin QPLL1.QuadX1Y9 B} -attr @name {}
attribute {inst QPLL1.QuadX1Y9} -attr @fillcolor #00868b
load inst cpll.X1Y37 CPLL_X1 syn -hier QuadX1Y9 -pg 1 -y 3152 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y37 A} -attr @name {}
attribute {pin cpll.X1Y37 B} -attr @name {}
attribute {inst cpll.X1Y37} -attr @fillcolor #00868b
load symbol X1Y37 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y37 X1Y37 syn -hier QuadX1Y9 -pg 1 -y 3152 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y37} -attr @fillcolor #7a7a7a
load inst cpll.X1Y36 CPLL_X1 syn -hier QuadX1Y9 -pg 1 -y 3237 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y36 A} -attr @name {}
attribute {pin cpll.X1Y36 B} -attr @name {}
attribute {inst cpll.X1Y36} -attr @fillcolor #00868b
load symbol X1Y36 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y36 X1Y36 syn -hier QuadX1Y9 -pg 1 -y 3237 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y36} -attr @fillcolor #7a7a7a
load port QuadX1Y9_clk0 out -pg 1 -y 2951 -x 12001 -attr @fillcolor #3a5fcd
load port QuadX1Y9_clk1 out -pg 1 -y 3121 -x 12001 -attr @fillcolor #3a5fcd
load inst QuadX1Y8 QUAD_X1 v -pg 1 -y 3373 -x 12000 -autohide -attr @cell QuadX1Y8 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin QuadX1Y8 QPLL0 } -attr @name {}
attribute {hierPin QuadX1Y8 QPLL0 } -attr @name {}
attribute {pin QuadX1Y8 QPLL1 } -attr @name {}
attribute {hierPin QuadX1Y8 QPLL1 } -attr @name {}
attribute {pin QuadX1Y8 a0 } -attr @name {}
attribute {hierPin QuadX1Y8 a0 } -attr @name {}
attribute {pin QuadX1Y8 a1 } -attr @name {}
attribute {hierPin QuadX1Y8 a1 } -attr @name {}
attribute {pin QuadX1Y8 a2 } -attr @name {}
attribute {hierPin QuadX1Y8 a2 } -attr @name {}
attribute {pin QuadX1Y8 a3 } -attr @name {}
attribute {hierPin QuadX1Y8 a3 } -attr @name {}
attribute {pin QuadX1Y8 RECCLK_clk0 } -attr @name {}
attribute {hierPin QuadX1Y8 RECCLK_clk0 } -attr @name {}
attribute {pin QuadX1Y8 RECCLK_clk1 } -attr @name {}
attribute {hierPin QuadX1Y8 RECCLK_clk1 } -attr @name {}
load inst cpll.X1Y35 CPLL_X1 syn -hier QuadX1Y8 -pg 1 -y 3374 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y35 A} -attr @name {}
attribute {pin cpll.X1Y35 B} -attr @name {}
attribute {inst cpll.X1Y35} -attr @fillcolor #00868b
load symbol X1Y35 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y35 X1Y35 syn -hier QuadX1Y8 -pg 1 -y 3374 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y35} -attr @fillcolor #7a7a7a
load inst cpll.X1Y34 CPLL_X1 syn -hier QuadX1Y8 -pg 1 -y 3459 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y34 A} -attr @name {}
attribute {pin cpll.X1Y34 B} -attr @name {}
attribute {inst cpll.X1Y34} -attr @fillcolor #00868b
load symbol X1Y34 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y34 X1Y34 syn -hier QuadX1Y8 -pg 1 -y 3459 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y34} -attr @fillcolor #7a7a7a
load inst QPLL0.QuadX1Y8 QPLL0_X1 syn -hier QuadX1Y8 -pg 1 -y 3544 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL0.QuadX1Y8 A} -attr @name {}
attribute {pin QPLL0.QuadX1Y8 B} -attr @name {}
attribute {inst QPLL0.QuadX1Y8} -attr @fillcolor #00868b
load inst QPLL1.QuadX1Y8 QPLL1_X1 syn -hier QuadX1Y8 -pg 1 -y 3629 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL1.QuadX1Y8 A} -attr @name {}
attribute {pin QPLL1.QuadX1Y8 B} -attr @name {}
attribute {inst QPLL1.QuadX1Y8} -attr @fillcolor #00868b
load inst cpll.X1Y33 CPLL_X1 syn -hier QuadX1Y8 -pg 1 -y 3714 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y33 A} -attr @name {}
attribute {pin cpll.X1Y33 B} -attr @name {}
attribute {inst cpll.X1Y33} -attr @fillcolor #00868b
load symbol X1Y33 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y33 X1Y33 syn -hier QuadX1Y8 -pg 1 -y 3714 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y33} -attr @fillcolor #7a7a7a
load inst cpll.X1Y32 CPLL_X1 syn -hier QuadX1Y8 -pg 1 -y 3799 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y32 A} -attr @name {}
attribute {pin cpll.X1Y32 B} -attr @name {}
attribute {inst cpll.X1Y32} -attr @fillcolor #00868b
load symbol X1Y32 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y32 X1Y32 syn -hier QuadX1Y8 -pg 1 -y 3799 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y32} -attr @fillcolor #7a7a7a
load port QuadX1Y8_clk0 out -pg 1 -y 3513 -x 12001 -attr @fillcolor #3a5fcd
load port QuadX1Y8_clk1 out -pg 1 -y 3683 -x 12001 -attr @fillcolor #3a5fcd
load inst QuadX1Y7 QUAD_X1 v -pg 1 -y 3935 -x 12000 -autohide -attr @cell QuadX1Y7 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin QuadX1Y7 QPLL0 } -attr @name {}
attribute {hierPin QuadX1Y7 QPLL0 } -attr @name {}
attribute {pin QuadX1Y7 QPLL1 } -attr @name {}
attribute {hierPin QuadX1Y7 QPLL1 } -attr @name {}
attribute {pin QuadX1Y7 a0 } -attr @name {}
attribute {hierPin QuadX1Y7 a0 } -attr @name {}
attribute {pin QuadX1Y7 a1 } -attr @name {}
attribute {hierPin QuadX1Y7 a1 } -attr @name {}
attribute {pin QuadX1Y7 a2 } -attr @name {}
attribute {hierPin QuadX1Y7 a2 } -attr @name {}
attribute {pin QuadX1Y7 a3 } -attr @name {}
attribute {hierPin QuadX1Y7 a3 } -attr @name {}
attribute {pin QuadX1Y7 RECCLK_clk0 } -attr @name {}
attribute {hierPin QuadX1Y7 RECCLK_clk0 } -attr @name {}
attribute {pin QuadX1Y7 RECCLK_clk1 } -attr @name {}
attribute {hierPin QuadX1Y7 RECCLK_clk1 } -attr @name {}
load inst cpll.X1Y31 CPLL_X1 syn -hier QuadX1Y7 -pg 1 -y 3936 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y31 A} -attr @name {}
attribute {pin cpll.X1Y31 B} -attr @name {}
attribute {inst cpll.X1Y31} -attr @fillcolor #00868b
load symbol X1Y31 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y31 X1Y31 syn -hier QuadX1Y7 -pg 1 -y 3936 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y31} -attr @fillcolor #7a7a7a
load inst cpll.X1Y30 CPLL_X1 syn -hier QuadX1Y7 -pg 1 -y 4021 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y30 A} -attr @name {}
attribute {pin cpll.X1Y30 B} -attr @name {}
attribute {inst cpll.X1Y30} -attr @fillcolor #00868b
load symbol X1Y30 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y30 X1Y30 syn -hier QuadX1Y7 -pg 1 -y 4021 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y30} -attr @fillcolor #7a7a7a
load inst QPLL0.QuadX1Y7 QPLL0_X1 syn -hier QuadX1Y7 -pg 1 -y 4106 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL0.QuadX1Y7 A} -attr @name {}
attribute {pin QPLL0.QuadX1Y7 B} -attr @name {}
attribute {inst QPLL0.QuadX1Y7} -attr @fillcolor #00868b
load inst QPLL1.QuadX1Y7 QPLL1_X1 syn -hier QuadX1Y7 -pg 1 -y 4191 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin QPLL1.QuadX1Y7 A} -attr @name {}
attribute {pin QPLL1.QuadX1Y7 B} -attr @name {}
attribute {inst QPLL1.QuadX1Y7} -attr @fillcolor #00868b
load inst cpll.X1Y29 CPLL_X1 syn -hier QuadX1Y7 -pg 1 -y 4276 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y29 A} -attr @name {}
attribute {pin cpll.X1Y29 B} -attr @name {}
attribute {inst cpll.X1Y29} -attr @fillcolor #00868b
load symbol X1Y29 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y29 X1Y29 syn -hier QuadX1Y7 -pg 1 -y 4276 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y29} -attr @fillcolor #7a7a7a
load inst cpll.X1Y28 CPLL_X1 syn -hier QuadX1Y7 -pg 1 -y 4361 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y28 A} -attr @name {}
attribute {pin cpll.X1Y28 B} -attr @name {}
attribute {inst cpll.X1Y28} -attr @fillcolor #00868b
load symbol X1Y28 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y28 X1Y28 syn -hier QuadX1Y7 -pg 1 -y 4361 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y28} -attr @fillcolor #7a7a7a
load port QuadX1Y7_clk0 out -pg 1 -y 4075 -x 12001 -attr @fillcolor #3a5fcd
load port QuadX1Y7_clk1 out -pg 1 -y 4245 -x 12001 -attr @fillcolor #3a5fcd
load inst QuadX1Y6 QUAD_X1 v -pg 1 -y 4497 -x 12000 -autohide -attr @cell QuadX1Y6 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin QuadX1Y6 QPLL0 } -attr @name {}
attribute {hierPin QuadX1Y6 QPLL0 } -attr @name {}
attribute {pin QuadX1Y6 QPLL1 } -attr @name {}
attribute {hierPin QuadX1Y6 QPLL1 } -attr @name {}
attribute {pin QuadX1Y6 a0 } -attr @name {}
attribute {hierPin QuadX1Y6 a0 } -attr @name {}
attribute {pin QuadX1Y6 a1 } -attr @name {}
attribute {hierPin QuadX1Y6 a1 } -attr @name {}
attribute {pin QuadX1Y6 a2 } -attr @name {}
attribute {hierPin QuadX1Y6 a2 } -attr @name {}
attribute {pin QuadX1Y6 a3 } -attr @name {}
attribute {hierPin QuadX1Y6 a3 } -attr @name {}
attribute {pin QuadX1Y6 RECCLK_clk0 } -attr @name {}
attribute {hierPin QuadX1Y6 RECCLK_clk0 } -attr @name {}
attribute {pin QuadX1Y6 RECCLK_clk1 } -attr @name {}
attribute {hierPin QuadX1Y6 RECCLK_clk1 } -attr @name {}
load inst cpll.X1Y27 CPLL_X1 syn -hier QuadX1Y6 -pg 1 -y 4498 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y27 A} -attr @name {}
attribute {pin cpll.X1Y27 B} -attr @name {}
attribute {inst cpll.X1Y27} -attr @fillcolor #00868b
load symbol X1Y27 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y27 X1Y27 syn -hier QuadX1Y6 -pg 1 -y 4498 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y27} -attr @fillcolor #7a7a7a
load inst cpll.X1Y26 CPLL_X1 syn -hier QuadX1Y6 -pg 1 -y 4583 -x 12001 -autohide -attr @name {} -attr @cell {}
attribute {pin cpll.X1Y26 A} -attr @name {}
attribute {pin cpll.X1Y26 B} -attr @name {}
attribute {inst cpll.X1Y26} -attr @fillcolor #00868b
load symbol X1Y26 syn HIERGEN port TX out port RX out port RXRECCLK in
load inst GT.X1Y26 X1Y26 syn -hier QuadX1Y6 -pg 1 -y 4583 -x 12000 -autohide -attr @name {}
attribute {inst GT.X1Y26} -attr @fillcolor #7a7a7a
load inst QPLL0.QuadX1Y6 QPLL0_X1 syn -hier QuadX1Y6 -pg 1 -y 4668 -x 12001 -autohide -attr @name {} -attr @cell {}