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Add Vortex DSE specifications
Deterministic slot-based admission with a separate per-slot agreement layer: a message carries its own slot stamp and each node decides admission locally, with no leader, quorum or vote. Two admission modes are specified because both are implemented: the default admits a late message into its own slot, while the opt-in TTL mode rejects it permanently to bound memory. Vortex_DSE_CSlot_AE is specified over the TTL mode; the README says so rather than implying it composes with the default. Six TLC models, all completing in under four seconds. Three TLAPS modules discharging 194, 131 and 34 obligations, all exit 0 under tlapm --strict with no OMITTED steps. Co-authored-by: Claude Opus 5 <noreply@anthropic.com> Signed-off-by: Vasilis Nasopoulos <vasilis_nasopoulos@hotmail.com>
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README.md

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| [DAG-based Consensus](specifications/dag-consensus) | Giuliano Losa | | ||| |
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| [German Cache-Coherence Protocol](specifications/GermanProtocol) | Markus Kuppe | | | |||
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| [FLASH Cache-Coherence Protocol](specifications/FlashProtocol) | Markus Kuppe | | | |||
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| [Vortex DSE](specifications/VortexDSE) | Vasilis Nasopoulos | || || |
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## Other Examples
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\* TLC model configuration for Vortex_DSE_CSlot.
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\* Two nodes, two message ids, slot horizon 2 — bounded but non-trivial.
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CONSTANT
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Nodes = {n1, n2}
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MsgIDs = {m1, m2}
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MaxSlot = 2
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INIT Init
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NEXT Next
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INVARIANT TypeInvariant
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INVARIANT NoFutureAdmission
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INVARIANT ExactlyOncePerNode
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INVARIANT NoPhantomProcess
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INVARIANT DecisionLocalityOnly
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CONSTRAINT StateConstraint
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---- MODULE MC_Vortex_DSE_CSlot ----
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(* TLC bounded model-checking harness for Vortex_DSE_CSlot. *)
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(* Constants are assigned in MC_Vortex_DSE_CSlot.cfg: *)
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(* Nodes = {n1, n2} *)
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(* MsgIDs = {m1, m2} *)
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(* MaxSlot = 2 *)
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EXTENDS Vortex_DSE_CSlot
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====
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---------------- MODULE MC_Vortex_DSE_CSlot_AE ----------------
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(* Apalache harness for Vortex_DSE_CSlot_AE. *)
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(* Fixes constants and bundles the safety invariants for a single *)
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(* symbolic (SMT-backed) check via Apalache. *)
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EXTENDS Vortex_DSE_CSlot_AE
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ConstInit ==
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/\ Nodes = {"n1", "n2"}
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/\ MsgIDs = {"a", "b"}
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/\ MaxSlot = 1
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\* Conjunction of every safety invariant in the module.
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AllInv ==
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/\ TypeInvariant
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/\ MerkleAgreement
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/\ CommittedSupersetsProcessed
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/\ NoPhantomInCommitted
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/\ NoReorderAcrossCslot
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/\ PhaseProgressionValid
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===============================================================
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SPECIFICATION LiveSpec
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CONSTANTS
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Nodes = {n1, n2}
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MsgIDs = {m1}
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MaxSlot = 1
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PROPERTIES
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EventualCommit
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EventualAgreement
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CONSTRAINT
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StateConstraint
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SPECIFICATION Spec
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CONSTANTS
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Nodes = {n1, n2}
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MsgIDs = {m1, m2}
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MaxSlot = 2
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INVARIANTS
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TypeInvariant
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MerkleAgreement
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CommittedSupersetsProcessed
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NoPhantomInCommitted
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NoReorderAcrossCslot
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PhaseProgressionValid
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CONSTRAINT
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StateConstraint

specifications/VortexDSE/README.md

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# Vortex DSE — C-slot admission and per-slot agreement
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Vortex DSE is a deterministic consensus protocol in which a message carries its
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own slot stamp and each node decides admission locally, against its own clock.
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There is no leader, no quorum and no vote: admission is an O(1) local predicate,
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and cross-node agreement on the per-slot input set is established afterwards by
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a separate layer.
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These specifications model that structure. They are the formal counterpart of a
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running implementation; the implementation itself is not part of this
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contribution.
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## Two admission modes
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The protocol has two admission rules, and the difference is one operator.
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| module | rule | meaning |
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| --- | --- | --- |
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| `Vortex_DSE_CSlot` | `m.cslot <= current_slot` | the default. A message stamped for slot *k* that arrives late is still admitted, into slot *k*. Nothing is dropped. |
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| `Vortex_DSE_CSlot_TTL` | `m.cslot = current_slot` | an opt-in bounded-memory mode. A message that misses its slot is rejected permanently, so state does not grow behind the frontier. |
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Both modes are specified because both are implemented; the strict rule is a
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memory concession, not a stronger version of the protocol.
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## Modules
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| module | what it adds |
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| --- | --- |
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| `Vortex_DSE_CSlot` | admission, crash and rejoin via a persisted snapshot |
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| `Vortex_DSE_CSlot_Proofs` | `TypeCorrect`, `NoFutureAdmissionCorrect` |
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| `Vortex_DSE_CSlot_ExactlyOnce_Proof` | `StrictExactlyOnceCorrect` |
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| `Vortex_DSE_CSlot_TTL` | the strict admission mode |
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| `Vortex_DSE_CSlot_Skew` | replaces the single global slot with a per-node clock, plus Byzantine injection of forged slot stamps and origins |
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| `Vortex_DSE_CSlot_AE` | the agreement layer: `Freeze`, `Reconcile`, `Commit` over the strict mode |
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| `Vortex_DSE_CSlot_AE_Proofs` | deductive proofs for the agreement layer |
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`Vortex_DSE_CSlot_AE` is specified over the strict admission rule; it is not a
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refinement of the default mode. Extending it to the late-tolerant rule requires
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restating what "no reordering across slots" means, and is not done here.
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## What is checked
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All TLAPS proofs discharge under `tlapm --strict`, which fails on unproved
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obligations and on proof steps left open — a plain `tlapm` invocation exits 0
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in both cases. There are no `OMITTED` steps in these modules.
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| | obligations |
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| --- | --- |
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| `Vortex_DSE_CSlot_Proofs` | 194 |
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| `Vortex_DSE_CSlot_ExactlyOnce_Proof` | 131 |
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| `Vortex_DSE_CSlot_AE_Proofs` | 34 |
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Every model completes in a few seconds. `Vortex_DSE_CSlot_AE` also carries
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Apalache type annotations, but no symbolic model is registered here; the models
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below are TLC only.
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## Scope
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`Vortex_DSE_CSlot_Skew` bounds pairwise clock skew structurally, by forbidding
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any tick that would breach the bound. It states the assumption; it does not
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model the mechanism that maintains it. Likewise `Reconcile` is a single atomic
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step at specification level — the multi-round protocol underneath is out of
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scope here.
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Source repositories, including the whitepaper and the model-checking logs:
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<https://github.com/vasilisnasopoulos>

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