diff --git a/Makefile b/Makefile index 2f16724d3..721cf18fb 100644 --- a/Makefile +++ b/Makefile @@ -253,6 +253,10 @@ esp32c3: esp32c6: $(MAKE) IDF_TARGET=esp32c6 ESP32_CHIP=esp32c6 esp32 +.PHONY: esp32p4 +esp32p4: + $(MAKE) IDF_TARGET=esp32p4 ESP32_CHIP=esp32p4 esp32 + .PHONY: esp32s2 esp32s2: $(MAKE) IDF_TARGET=esp32s2 ESP32_CHIP=esp32s2 esp32 diff --git a/lib/gpio/adc.toit b/lib/gpio/adc.toit index 8173dd905..e08881d40 100644 --- a/lib/gpio/adc.toit +++ b/lib/gpio/adc.toit @@ -44,6 +44,9 @@ Pin 5 is an ADC pin of channel 2. However, the controller of ADC channel 2 ADC1: Pins 0-6 No ADC2. +## ESP32P4 +ADC1: Pins 16-23, 49-54 + ## ESP32S2 ADC1: Pins 1-10 ADC2: Pins 11-20 diff --git a/lib/gpio/gpio.toit b/lib/gpio/gpio.toit index ce88a50df..ae9494d5b 100644 --- a/lib/gpio/gpio.toit +++ b/lib/gpio/gpio.toit @@ -54,6 +54,17 @@ Pins 0-7 are RTC pins and can be used in deep-sleep. For chip variants without an in-package flash, GPIO14 is not led out to any chip pins. +# ESP32P4 +The ESP32P4 has 55 physical pins (0-54). Each pin can be used as + a general-purpose pin, or be connected to a peripheral. + +Pins 34-38 are strapping pins. +Pins 24-25 are JTAG pins, and should not be used if JTAG support is needed. +Pins 16-23, 49-54 are ADC pins of channel 1. +Pins 51-54 are analog comparator pins. +Pins 0-15 are RTC pins and can be used in deep-sleep. +Pins 2-15 can be used as touch sensor pins. + # ESP32S2 The ESP32S2 has 43 physical pins (0-21, 26-46). Each pin can be used as a general-purpose pin, or be connected to a peripheral. diff --git a/lib/rmt.toit b/lib/rmt.toit index 6a07bb752..56d54f8f8 100644 --- a/lib/rmt.toit +++ b/lib/rmt.toit @@ -18,10 +18,10 @@ $Signals represent a collection of signals to be sent by the RMT controller. The ESP32 has 8 RMT channels, each of which can be configured for input or output. The ESP32C3 and ESP32C6 each have 2 TX and 2 RX channels. -The ESP32S2 and ESP32S3 each have 4 TX and 4 RX channels. +The ESP32P4, ESP32S2 and ESP32S3 each have 4 TX and 4 RX channels. The number of bytes per memory block is 256 on the ESP32 and ESP32S2. It is - 192 on the ESP32C3, ESP32C6, and ESP32S3. + 192 on the ESP32C3, ESP32C6, ESP32P4, and ESP32S3. # Examples @@ -693,7 +693,7 @@ class Channel: The number of bytes per memory block. On the ESP32 and ESP32S2 it is 256. -On the ESP32C3, ESP32C6, and ESP32S3 it is 192. +On the ESP32C3, ESP32C6, ESP32P4, and ESP32S3 it is 192. */ BYTES-PER-MEMORY-BLOCK/int ::= rmt-bytes-per-memory-block_ @@ -914,8 +914,8 @@ class Out extends Channel_: The $loop-count parameter specifies how many times the signals are repeated. If it is set to -1, the signals are repeated indefinitely. The ESP32 only supports -1 (infinite) - and 1. Other variants, like the ESP32C3, ESP32C6, ESP32S2, and ESP32S3, support other - positive values. + and 1. Other variants, like the ESP32C3, ESP32C6, ESP32P4, ESP32S2, and ESP32S3, support + other positive values. The $done-level parameter specifies the level of the pin when the transmission is done. */ @@ -989,7 +989,7 @@ class Out extends Channel_: Synchronizes the output of multiple $Out channels. Not all hardware supports this feature. The ESP32 does not, but the ESP32C3, ESP32C6, - ESP32S2, and ESP32S3 do. + ESP32P4, ESP32S2, and ESP32S3 do. */ class SynchronizationManager: resource_ /ByteArray? := ? diff --git a/lib/system/system.toit b/lib/system/system.toit index c3c7b16cb..a93201e5a 100644 --- a/lib/system/system.toit +++ b/lib/system/system.toit @@ -65,6 +65,9 @@ ARCHITECTURE-ESP32C3 ::= "esp32c3" /** Return value from $architecture. */ ARCHITECTURE-ESP32C6 ::= "esp32c6" +/** Return value from $architecture. */ +ARCHITECTURE-ESP32P4 ::= "esp32p4" + /** Return value from $architecture. */ ARCHITECTURE-ESP32S2 ::= "esp32s2" diff --git a/src/os_esp32.cc b/src/os_esp32.cc index d388544d8..9805d4f6a 100644 --- a/src/os_esp32.cc +++ b/src/os_esp32.cc @@ -50,6 +50,8 @@ #include #elif CONFIG_IDF_TARGET_ESP32C6 #include +#elif CONFIG_IDF_TARGET_ESP32P4 + #include #elif CONFIG_IDF_TARGET_ESP32S2 #include #elif CONFIG_IDF_TARGET_ESP32S3 @@ -317,6 +319,8 @@ void OS::set_up() { const char* chip_name = "ESP32C3"; #elif defined(CONFIG_IDF_TARGET_ESP32C6) const char* chip_name = "ESP32C6"; +#elif defined(CONFIG_IDF_TARGET_ESP32P4) + const char* chip_name = "ESP32P4"; #elif defined(CONFIG_IDF_TARGET_ESP32S2) const char* chip_name = "ESP32S2"; #elif defined(CONFIG_IDF_TARGET_ESP32S3) @@ -425,6 +429,9 @@ OS::HeapMemoryRange OS::get_heap_memory_range() { #ifdef CONFIG_IDF_TARGET_ESP32S3 range.address = reinterpret_cast(0x3fca0000); range.size = 384 * KB; +#elif CONFIG_IDF_TARGET_ESP32P4 + range.address = reinterpret_cast(0x4ff00000); + range.size = 0x4ff3afc0 - 0x4ff00000; #else // DRAM range IRAM range // Internal SRAM 2 200k 3ffa_e000 - 3ffe_0000 @@ -452,6 +459,8 @@ const char* OS::get_architecture() { return "esp32c3"; #elif defined(CONFIG_IDF_TARGET_ESP32C6) return "esp32c6"; +#elif defined(CONFIG_IDF_TARGET_ESP32P4) + return "esp32p4"; #elif defined(CONFIG_IDF_TARGET_ESP32S2) return "esp32s2"; #elif defined(CONFIG_IDF_TARGET_ESP32S3) diff --git a/src/primitive_esp32.cc b/src/primitive_esp32.cc index 18e54db5c..114759eb1 100644 --- a/src/primitive_esp32.cc +++ b/src/primitive_esp32.cc @@ -63,6 +63,8 @@ #include #elif CONFIG_IDF_TARGET_ESP32C6 #include +#elif CONFIG_IDF_TARGET_ESP32P4 + #include #elif CONFIG_IDF_TARGET_ESP32S2 #include #elif CONFIG_IDF_TARGET_ESP32S3 @@ -363,7 +365,9 @@ PRIMITIVE(enable_external_wakeup) { } PRIMITIVE(enable_touchpad_wakeup) { -#if SOC_TOUCH_SENSOR_SUPPORTED +#ifdef CONFIG_IDF_TARGET_ESP32P4 + FAIL(UNIMPLEMENTED); +#elif SOC_TOUCH_SENSOR_SUPPORTED esp_err_t err = esp_sleep_enable_touchpad_wakeup(); if (err != ESP_OK) { ESP_LOGE("Toit", "Failed: sleep_enable_touchpad_wakeup"); @@ -400,7 +404,9 @@ PRIMITIVE(ext1_wakeup_status) { } PRIMITIVE(touchpad_wakeup_status) { -#if SOC_TOUCH_SENSOR_SUPPORTED +#if defined(CONFIG_IDF_TARGET_ESP32P4) + FAIL(UNIMPLEMENTED); +#elif SOC_TOUCH_SENSOR_SUPPORTED touch_pad_t pad = esp_sleep_get_touchpad_wakeup_status(); return Primitive::integer(touch_pad_to_pin_num(pad), process); #else @@ -634,7 +640,9 @@ PRIMITIVE(pin_hold_disable) { } PRIMITIVE(deep_sleep_pin_hold_enable) { -#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if defined(CONFIG_IDF_TARGET_ESP32P4) + FAIL(UNIMPLEMENTED); +#elif !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP gpio_deep_sleep_hold_en(); return process->null_object(); #else @@ -643,7 +651,9 @@ PRIMITIVE(deep_sleep_pin_hold_enable) { } PRIMITIVE(deep_sleep_pin_hold_disable) { -#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if defined(CONFIG_IDF_TARGET_ESP32P4) + FAIL(UNIMPLEMENTED); +#elif !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP gpio_deep_sleep_hold_dis(); return process->null_object(); #else diff --git a/src/resources/adc_esp32.cc b/src/resources/adc_esp32.cc index 468654c01..aaf0ca135 100644 --- a/src/resources/adc_esp32.cc +++ b/src/resources/adc_esp32.cc @@ -106,6 +106,38 @@ static int get_adc1_channel(int pin) { } } +#elif CONFIG_IDF_TARGET_ESP32P4 + +#define ADC_CLK_SRC_DEFAULT ADC_RTC_CLK_SRC_DEFAULT + +static int get_adc1_channel(int pin) { + switch (pin) { + case 16: return ADC_CHANNEL_0; + case 17: return ADC_CHANNEL_1; + case 18: return ADC_CHANNEL_2; + case 19: return ADC_CHANNEL_3; + case 20: return ADC_CHANNEL_4; + case 21: return ADC_CHANNEL_5; + case 22: return ADC_CHANNEL_6; + case 23: return ADC_CHANNEL_7; + default: return -1; + } +} + +static int get_adc2_channel(int pin) { + // Note that the latest version of the ESP-IDF doesn't have a second channel + // anymore, but merges both ADCs into one. + switch (pin) { + case 49: return ADC_CHANNEL_0; + case 50: return ADC_CHANNEL_1; + case 51: return ADC_CHANNEL_2; + case 52: return ADC_CHANNEL_3; + case 53: return ADC_CHANNEL_4; + case 54: return ADC_CHANNEL_5; + default: return -1; + } +} + #elif CONFIG_IDF_TARGET_ESP32S2 #define ADC_CLK_SRC_DEFAULT ADC_RTC_CLK_SRC_DEFAULT diff --git a/src/resources/dac_esp32.cc b/src/resources/dac_esp32.cc index fb2d87e29..4e5637b60 100644 --- a/src/resources/dac_esp32.cc +++ b/src/resources/dac_esp32.cc @@ -63,6 +63,10 @@ static dac_channel_t get_dac_channel(int pin) { #error "Unexpected DAC support for the ESP32C6" +#elif CONFIG_IDF_TARGET_ESP32P4 + +#error "Unexpected DAC support for the ESP32P4" + #elif CONFIG_IDF_TARGET_ESP32S2 static dac_channel_t get_dac_channel(int pin) { diff --git a/src/resources/espnow_esp32.cc b/src/resources/espnow_esp32.cc index d51ef47f9..1aa9ee11b 100644 --- a/src/resources/espnow_esp32.cc +++ b/src/resources/espnow_esp32.cc @@ -15,7 +15,9 @@ #include "../top.h" -#if defined(TOIT_ESP32) && defined(CONFIG_TOIT_ENABLE_ESPNOW) +#if defined(TOIT_ESP32) && \ + (!defined(CONFIG_IDF_TARGET_ESP32P4)) && \ + defined(CONFIG_TOIT_ENABLE_ESPNOW) #include #include @@ -648,4 +650,4 @@ PRIMITIVE(remove_peer) { } // namespace toit -#endif // defined(TOIT_ESP32) && defined(CONFIG_TOIT_ENABLE_ESPNOW) +#endif // defined(TOIT_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32P4) && defined(CONFIG_TOIT_ENABLE_ESPNOW) diff --git a/src/resources/gpio_esp32.cc b/src/resources/gpio_esp32.cc index e90e768f8..6f1523a48 100644 --- a/src/resources/gpio_esp32.cc +++ b/src/resources/gpio_esp32.cc @@ -44,6 +44,7 @@ GPIO summary: - Esp32: https://docs.espressif.com/projects/esp-idf/en/stable/esp32/api-reference/peripherals/gpio.html - Esp32c3: https://docs.espressif.com/projects/esp-idf/en/stable/esp32c3/api-reference/peripherals/gpio.html - Esp32c6: https://docs.espressif.com/projects/esp-idf/en/stable/esp32c6/api-reference/peripherals/gpio.html +- Esp32p4: https://docs.espressif.com/projects/esp-idf/en/stable/esp32p4/api-reference/peripherals/gpio.html - Esp32s2: https://docs.espressif.com/projects/esp-idf/en/stable/esp32s2/api-reference/peripherals/gpio.html - Esp32s3: https://docs.espressif.com/projects/esp-idf/en/stable/esp32s3/api-reference/peripherals/gpio.html */ @@ -58,6 +59,11 @@ static ResourcePool gpio_pins( 20, 21 #elif CONFIG_IDF_TARGET_ESP32C6 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 +#elif CONFIG_IDF_TARGET_ESP32P4 + 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, + 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, + 50, 51, 52, 53, 54 #elif CONFIG_IDF_TARGET_ESP32S3 20, 21, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, @@ -86,6 +92,11 @@ static bool is_restricted_pin(int num) { // Pins 24-30 are used for flash and PSRAM. return 24 <= num && num <= 30; } +#elif CONFIG_IDF_TARGET_ESP32P4 +static bool is_restricted_pin(int num) { + // TODO(floitsch): are there restricted pins on the P4? + return false; +} #elif CONFIG_IDF_TARGET_ESP32S3 static bool is_restricted_pin(int num) { // Pins 26-32 are used for flash, and pins 33-37 are used for diff --git a/src/resources/touch_esp32.cc b/src/resources/touch_esp32.cc index 59a018682..9db28f847 100644 --- a/src/resources/touch_esp32.cc +++ b/src/resources/touch_esp32.cc @@ -80,6 +80,48 @@ int touch_pad_to_pin_num(touch_pad_t pad) { return -1; } +#elif CONFIG_IDF_TARGET_ESP32P4 + +static touch_pad_t get_touch_pad(int pin) { + switch (pin) { + case 2: return TOUCH_PAD_NUM1; + case 3: return TOUCH_PAD_NUM2; + case 4: return TOUCH_PAD_NUM3; + case 5: return TOUCH_PAD_NUM4; + case 6: return TOUCH_PAD_NUM5; + case 7: return TOUCH_PAD_NUM6; + case 8: return TOUCH_PAD_NUM7; + case 9: return TOUCH_PAD_NUM8; + case 10: return TOUCH_PAD_NUM9; + case 11: return TOUCH_PAD_NUM10; + case 12: return TOUCH_PAD_NUM11; + case 13: return TOUCH_PAD_NUM12; + case 14: return TOUCH_PAD_NUM13; + case 15: return TOUCH_PAD_NUM14; + default: return kInvalidTouchPad; + } +} + +int touch_pad_to_pin_num(touch_pad_t pad) { + switch (pad) { + case TOUCH_PAD_NUM1: return 2; + case TOUCH_PAD_NUM2: return 3; + case TOUCH_PAD_NUM3: return 4; + case TOUCH_PAD_NUM4: return 5; + case TOUCH_PAD_NUM5: return 6; + case TOUCH_PAD_NUM6: return 7; + case TOUCH_PAD_NUM7: return 8; + case TOUCH_PAD_NUM8: return 9; + case TOUCH_PAD_NUM9: return 10; + case TOUCH_PAD_NUM10: return 11; + case TOUCH_PAD_NUM11: return 12; + case TOUCH_PAD_NUM12: return 13; + case TOUCH_PAD_NUM13: return 14; + case TOUCH_PAD_NUM14: return 15; + default: return -1; + } +} + #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 static touch_pad_t get_touch_pad(int pin) { @@ -228,7 +270,7 @@ PRIMITIVE(use) { ByteArray* proxy = process->object_heap()->allocate_proxy(); if (proxy == null) FAIL(ALLOCATION_FAILED); -#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32P4 esp_err_t err = touch_pad_config(pad); if (err == ESP_OK) { err = touch_pad_set_thresh(pad, threshold); diff --git a/src/resources/uart_esp32.cc b/src/resources/uart_esp32.cc index f888c5beb..67e262c9f 100644 --- a/src/resources/uart_esp32.cc +++ b/src/resources/uart_esp32.cc @@ -47,7 +47,13 @@ #define UART_NUM_2 (static_cast(2)) /*!< UART port 2 */ #endif #if SOC_UART_HP_NUM > 3 -#error "SOC_UART_HP_NUM > 3" +#define UART_NUM_3 (static_cast(3)) /*!< UART port 3 */ +#endif +#if SOC_UART_HP_NUM > 4 +#define UART_NUM_4 (static_cast(4)) /*!< UART port 4 */ +#endif +#if SOC_UART_HP_NUM > 5 +#error "SOC_UART_HP_NUM > 5" #endif #define UART_NUM_MAX (SOC_UART_HP_NUM) /*!< UART port max */ @@ -59,7 +65,13 @@ static periph_module_t module_from_port(uart_port_t port) { case UART_NUM_2: return PERIPH_UART2_MODULE; #endif #if SOC_UART_HP_NUM > 3 -#error "SOC_UART_HP_NUM > 3" + case UART_NUM_3: return PERIPH_UART3_MODULE; +#endif +#if SOC_UART_HP_NUM > 4 + case UART_NUM_4: return PERIPH_UART4_MODULE; +#endif +#if SOC_UART_HP_NUM > 5 +#error "SOC_UART_HP_NUM > 5" #endif default: // Includes LP uarts. UNREACHABLE(); @@ -85,6 +97,12 @@ static ResourcePool uart_ports( #if SOC_UART_HP_NUM > 2 , UART_NUM_2 #endif +#if SOC_UART_HP_NUM > 3 + , UART_NUM_3 +#endif +#if SOC_UART_HP_NUM > 4 + , UART_NUM_4 +#endif ); typedef enum { diff --git a/src/resources/uart_esp32_hal.c b/src/resources/uart_esp32_hal.c index d13e24f20..0daca26e1 100644 --- a/src/resources/uart_esp32_hal.c +++ b/src/resources/uart_esp32_hal.c @@ -17,6 +17,13 @@ // Therefore we don't test for `TOIT_ESP32` but for `ESP_PLATFORM`. #if defined(ESP_PLATFORM) +// TODO(floitsch): this is a hack to get p4 working. It means that the UART +// (uart_ll_set_baudrate, uart_ll_enable_pad_sleep_clock, ...) isn't correctly +// protected anymore. +#ifndef __DECLARE_RCC_ATOMIC_ENV +#define __DECLARE_RCC_ATOMIC_ENV ((void)0) +#endif + #include "esp_attr.h" #include "uart_esp32_hal.h" #include "hal/uart_hal.h" diff --git a/src/resources/wifi_esp32.cc b/src/resources/wifi_esp32.cc index 89ac8c298..1ea530db6 100644 --- a/src/resources/wifi_esp32.cc +++ b/src/resources/wifi_esp32.cc @@ -35,7 +35,7 @@ #include "../event_sources/system_esp32.h" namespace toit { -#if defined(CONFIG_TOIT_ENABLE_WIFI) +#if defined(CONFIG_TOIT_ENABLE_WIFI) && (!defined(CONFIG_IDF_TARGET_ESP32P4)) enum { WIFI_CONNECTED = 1 << 0, WIFI_IP_ASSIGNED = 1 << 1, @@ -812,7 +812,7 @@ PRIMITIVE(ap_info) { return ap_array; } -#endif // CONFIG_TOIT_ENABLE_WIFI +#endif // CONFIG_TOIT_ENABLE_WIFI && !CONFIG_IDF_TARGET_ESP32P4 } // namespace toit #endif // TOIT_ESP32 diff --git a/src/resources/wifi_espnow_esp32.cc b/src/resources/wifi_espnow_esp32.cc index 7492bf79b..a116c67ad 100644 --- a/src/resources/wifi_espnow_esp32.cc +++ b/src/resources/wifi_espnow_esp32.cc @@ -15,7 +15,7 @@ #include "../top.h" -#ifdef TOIT_ESP32 +#if defined(TOIT_ESP32) && (!defined(CONFIG_IDF_TARGET_ESP32P4)) #if defined(CONFIG_TOIT_ENABLE_WIFI) || defined(CONFIG_TOIT_ENABLE_ESPNOW) #include "wifi_espnow_esp32.h" @@ -31,4 +31,4 @@ ResourcePool wifi_espnow_pool( } // namespace toit #endif // CONFIG_TOIT_ENABLE_WIFI || CONFIG_TOIT_ENABLE_ESPNOW -#endif // TOIT_ESP32 +#endif // TOIT_ESP32 && !CONFIG_IDF_TARGET_ESP32P4 diff --git a/src/rtc_memory_esp32.cc b/src/rtc_memory_esp32.cc index 9e44f1bda..176a4e653 100644 --- a/src/rtc_memory_esp32.cc +++ b/src/rtc_memory_esp32.cc @@ -35,6 +35,9 @@ #elif CONFIG_IDF_TARGET_ESP32C6 #include #include +#elif CONFIG_IDF_TARGET_ESP32P4 + #include + #include #elif CONFIG_IDF_TARGET_ESP32S2 #include #include diff --git a/src/utils.cc b/src/utils.cc index d6ab7916b..2c4a9c47f 100644 --- a/src/utils.cc +++ b/src/utils.cc @@ -659,7 +659,11 @@ void iram_safe_char_memcpy(char* dst, const char* src, size_t bytes) { : "r" (dst), "r" (src), "r" (bytes) // Clobbers. : ); -#elif (!defined(TOIT_ESP32)) || defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32C6) || defined(CONFIG_IDF_TARGET_ESP32S2) +#elif (!defined(TOIT_ESP32)) || \ + defined(CONFIG_IDF_TARGET_ESP32C3) || \ + defined(CONFIG_IDF_TARGET_ESP32C6) || \ + defined(CONFIG_IDF_TARGET_ESP32P4) || \ + defined(CONFIG_IDF_TARGET_ESP32S2) memcpy(dst, src, bytes); #else #error "Unknown target" diff --git a/toolchains/esp32p4/CMakeLists.txt b/toolchains/esp32p4/CMakeLists.txt new file mode 100644 index 000000000..393e96366 --- /dev/null +++ b/toolchains/esp32p4/CMakeLists.txt @@ -0,0 +1,10 @@ +# The following lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.5) + +list(APPEND EXTRA_COMPONENT_DIRS "../idf/components") + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(toit) + +toit_postprocess() diff --git a/toolchains/esp32p4/main/CMakeLists.txt b/toolchains/esp32p4/main/CMakeLists.txt new file mode 100644 index 000000000..a971fcd20 --- /dev/null +++ b/toolchains/esp32p4/main/CMakeLists.txt @@ -0,0 +1,2 @@ +idf_component_register(SRCS "toit.c" + INCLUDE_DIRS "") diff --git a/toolchains/esp32p4/main/toit.c b/toolchains/esp32p4/main/toit.c new file mode 100644 index 000000000..f4aefc09d --- /dev/null +++ b/toolchains/esp32p4/main/toit.c @@ -0,0 +1,22 @@ +// Copyright (C) 2018 Toitware ApS. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; version +// 2.1 only. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// The license can be found in the file `LICENSE` in the top level +// directory of this repository. + +// Toit ESP32 top level, derived from ESP-IDF Hello World example. + +extern void toit_start(); + +void app_main() { + toit_start(); +} diff --git a/toolchains/esp32p4/partitions.csv b/toolchains/esp32p4/partitions.csv new file mode 100644 index 000000000..c6ef16579 --- /dev/null +++ b/toolchains/esp32p4/partitions.csv @@ -0,0 +1,27 @@ +# Copyright (C) 2022 Toitware ApS. +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; version +# 2.1 only. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# The license can be found in the file `LICENSE` in the top level +# directory of this repository. + +# Partition Table for Toit. + +# Name, Type, SubType, Offset, Size +# bootloader,, , 0x000000, 0x008000 +# partitions,, , 0x008000, 0x000c00 +secure, 0x42, 0x00, 0x009000, 0x004000, +otadata, data, ota, , 0x002000, +phy_init, data, phy, , 0x001000, +ota_0, app, ota_0, , 0x1a0000, +ota_1, app, ota_1, , 0x1a0000, +nvs, data, nvs, , 0x010000, +programs, 0x40, 0x00, , 0x0a0000, encrypted diff --git a/toolchains/esp32p4/sdkconfig b/toolchains/esp32p4/sdkconfig new file mode 100644 index 000000000..2532f129a --- /dev/null +++ b/toolchains/esp32p4/sdkconfig @@ -0,0 +1,2387 @@ +# +# Automatically generated file. DO NOT EDIT. +# Espressif IoT Development Framework (ESP-IDF) 5.4.2 Project Configuration +# +CONFIG_SOC_ADC_SUPPORTED=y +CONFIG_SOC_ANA_CMPR_SUPPORTED=y +CONFIG_SOC_DEDICATED_GPIO_SUPPORTED=y +CONFIG_SOC_UART_SUPPORTED=y +CONFIG_SOC_GDMA_SUPPORTED=y +CONFIG_SOC_AHB_GDMA_SUPPORTED=y +CONFIG_SOC_AXI_GDMA_SUPPORTED=y +CONFIG_SOC_DW_GDMA_SUPPORTED=y +CONFIG_SOC_DMA2D_SUPPORTED=y +CONFIG_SOC_GPTIMER_SUPPORTED=y +CONFIG_SOC_PCNT_SUPPORTED=y +CONFIG_SOC_LCDCAM_SUPPORTED=y +CONFIG_SOC_LCDCAM_CAM_SUPPORTED=y +CONFIG_SOC_LCDCAM_I80_LCD_SUPPORTED=y +CONFIG_SOC_LCDCAM_RGB_LCD_SUPPORTED=y +CONFIG_SOC_MIPI_CSI_SUPPORTED=y +CONFIG_SOC_MIPI_DSI_SUPPORTED=y +CONFIG_SOC_MCPWM_SUPPORTED=y +CONFIG_SOC_TWAI_SUPPORTED=y +CONFIG_SOC_ETM_SUPPORTED=y +CONFIG_SOC_PARLIO_SUPPORTED=y +CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED=y +CONFIG_SOC_EMAC_SUPPORTED=y +CONFIG_SOC_USB_OTG_SUPPORTED=y +CONFIG_SOC_WIRELESS_HOST_SUPPORTED=y +CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED=y +CONFIG_SOC_TEMP_SENSOR_SUPPORTED=y +CONFIG_SOC_SUPPORTS_SECURE_DL_MODE=y +CONFIG_SOC_ULP_SUPPORTED=y +CONFIG_SOC_LP_CORE_SUPPORTED=y +CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD=y +CONFIG_SOC_EFUSE_SUPPORTED=y +CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y +CONFIG_SOC_RTC_MEM_SUPPORTED=y +CONFIG_SOC_RMT_SUPPORTED=y +CONFIG_SOC_I2S_SUPPORTED=y +CONFIG_SOC_SDM_SUPPORTED=y +CONFIG_SOC_GPSPI_SUPPORTED=y +CONFIG_SOC_LEDC_SUPPORTED=y +CONFIG_SOC_ISP_SUPPORTED=y +CONFIG_SOC_I2C_SUPPORTED=y +CONFIG_SOC_SYSTIMER_SUPPORTED=y +CONFIG_SOC_AES_SUPPORTED=y +CONFIG_SOC_MPI_SUPPORTED=y +CONFIG_SOC_SHA_SUPPORTED=y +CONFIG_SOC_HMAC_SUPPORTED=y +CONFIG_SOC_DIG_SIGN_SUPPORTED=y +CONFIG_SOC_ECC_SUPPORTED=y +CONFIG_SOC_ECC_EXTENDED_MODES_SUPPORTED=y +CONFIG_SOC_FLASH_ENC_SUPPORTED=y +CONFIG_SOC_SECURE_BOOT_SUPPORTED=y +CONFIG_SOC_BOD_SUPPORTED=y +CONFIG_SOC_APM_SUPPORTED=y +CONFIG_SOC_PMU_SUPPORTED=y +CONFIG_SOC_DCDC_SUPPORTED=y +CONFIG_SOC_PAU_SUPPORTED=y +CONFIG_SOC_LP_TIMER_SUPPORTED=y +CONFIG_SOC_ULP_LP_UART_SUPPORTED=y +CONFIG_SOC_LP_GPIO_MATRIX_SUPPORTED=y +CONFIG_SOC_LP_PERIPHERALS_SUPPORTED=y +CONFIG_SOC_LP_I2C_SUPPORTED=y +CONFIG_SOC_LP_I2S_SUPPORTED=y +CONFIG_SOC_LP_SPI_SUPPORTED=y +CONFIG_SOC_LP_ADC_SUPPORTED=y +CONFIG_SOC_LP_VAD_SUPPORTED=y +CONFIG_SOC_SPIRAM_SUPPORTED=y +CONFIG_SOC_PSRAM_DMA_CAPABLE=y +CONFIG_SOC_SDMMC_HOST_SUPPORTED=y +CONFIG_SOC_CLK_TREE_SUPPORTED=y +CONFIG_SOC_ASSIST_DEBUG_SUPPORTED=y +CONFIG_SOC_DEBUG_PROBE_SUPPORTED=y +CONFIG_SOC_WDT_SUPPORTED=y +CONFIG_SOC_SPI_FLASH_SUPPORTED=y +CONFIG_SOC_TOUCH_SENSOR_SUPPORTED=y +CONFIG_SOC_RNG_SUPPORTED=y +CONFIG_SOC_GP_LDO_SUPPORTED=y +CONFIG_SOC_PPA_SUPPORTED=y +CONFIG_SOC_LIGHT_SLEEP_SUPPORTED=y +CONFIG_SOC_DEEP_SLEEP_SUPPORTED=y +CONFIG_SOC_PM_SUPPORTED=y +CONFIG_SOC_SIMD_INSTRUCTION_SUPPORTED=y +CONFIG_SOC_XTAL_SUPPORT_40M=y +CONFIG_SOC_AES_SUPPORT_DMA=y +CONFIG_SOC_AES_SUPPORT_GCM=y +CONFIG_SOC_AES_GDMA=y +CONFIG_SOC_AES_SUPPORT_AES_128=y +CONFIG_SOC_AES_SUPPORT_AES_256=y +CONFIG_SOC_ADC_RTC_CTRL_SUPPORTED=y +CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y +CONFIG_SOC_ADC_DMA_SUPPORTED=y +CONFIG_SOC_ADC_PERIPH_NUM=2 +CONFIG_SOC_ADC_MAX_CHANNEL_NUM=8 +CONFIG_SOC_ADC_ATTEN_NUM=4 +CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=2 +CONFIG_SOC_ADC_PATT_LEN_MAX=16 +CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12 +CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=12 +CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM=2 +CONFIG_SOC_ADC_DIGI_MONITOR_NUM=2 +CONFIG_SOC_ADC_DIGI_RESULT_BYTES=4 +CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4 +CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=83333 +CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=611 +CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=12 +CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12 +CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED=y +CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED=y +CONFIG_SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED=y +CONFIG_SOC_ADC_SHARED_POWER=y +CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y +CONFIG_SOC_SHARED_IDCACHE_SUPPORTED=y +CONFIG_SOC_CACHE_WRITEBACK_SUPPORTED=y +CONFIG_SOC_CACHE_FREEZE_SUPPORTED=y +CONFIG_SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE=y +CONFIG_SOC_CPU_CORES_NUM=2 +CONFIG_SOC_CPU_INTR_NUM=32 +CONFIG_SOC_CPU_HAS_FLEXIBLE_INTC=y +CONFIG_SOC_INT_CLIC_SUPPORTED=y +CONFIG_SOC_INT_HW_NESTED_SUPPORTED=y +CONFIG_SOC_BRANCH_PREDICTOR_SUPPORTED=y +CONFIG_SOC_CPU_COPROC_NUM=3 +CONFIG_SOC_CPU_HAS_FPU=y +CONFIG_SOC_CPU_HAS_FPU_EXT_ILL_BUG=y +CONFIG_SOC_CPU_HAS_HWLOOP=y +CONFIG_SOC_CPU_HAS_HWLOOP_STATE_BUG=y +CONFIG_SOC_CPU_HAS_PIE=y +CONFIG_SOC_HP_CPU_HAS_MULTIPLE_CORES=y +CONFIG_SOC_CPU_BREAKPOINTS_NUM=3 +CONFIG_SOC_CPU_WATCHPOINTS_NUM=3 +CONFIG_SOC_CPU_WATCHPOINT_MAX_REGION_SIZE=0x100 +CONFIG_SOC_CPU_HAS_PMA=y +CONFIG_SOC_CPU_IDRAM_SPLIT_USING_PMP=y +CONFIG_SOC_CPU_PMP_REGION_GRANULARITY=128 +CONFIG_SOC_CPU_HAS_LOCKUP_RESET=y +CONFIG_SOC_SIMD_PREFERRED_DATA_ALIGNMENT=16 +CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN=4096 +CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH=16 +CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US=1100 +CONFIG_SOC_DMA_CAN_ACCESS_FLASH=y +CONFIG_SOC_AHB_GDMA_VERSION=2 +CONFIG_SOC_GDMA_SUPPORT_CRC=y +CONFIG_SOC_GDMA_NUM_GROUPS_MAX=2 +CONFIG_SOC_GDMA_PAIRS_PER_GROUP_MAX=3 +CONFIG_SOC_AXI_GDMA_SUPPORT_PSRAM=y +CONFIG_SOC_GDMA_SUPPORT_ETM=y +CONFIG_SOC_GDMA_SUPPORT_SLEEP_RETENTION=y +CONFIG_SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT=16 +CONFIG_SOC_DMA2D_GROUPS=1 +CONFIG_SOC_DMA2D_TX_CHANNELS_PER_GROUP=3 +CONFIG_SOC_DMA2D_RX_CHANNELS_PER_GROUP=2 +CONFIG_SOC_ETM_GROUPS=1 +CONFIG_SOC_ETM_CHANNELS_PER_GROUP=50 +CONFIG_SOC_ETM_SUPPORT_SLEEP_RETENTION=y +CONFIG_SOC_GPIO_PORT=1 +CONFIG_SOC_GPIO_PIN_COUNT=55 +CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER=y +CONFIG_SOC_GPIO_FLEX_GLITCH_FILTER_NUM=8 +CONFIG_SOC_GPIO_SUPPORT_PIN_HYS_FILTER=y +CONFIG_SOC_GPIO_SUPPORT_ETM=y +CONFIG_SOC_GPIO_SUPPORT_RTC_INDEPENDENT=y +CONFIG_SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP=y +CONFIG_SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE=y +CONFIG_SOC_LP_IO_CLOCK_IS_INDEPENDENT=y +CONFIG_SOC_GPIO_VALID_GPIO_MASK=0x007FFFFFFFFFFFFF +CONFIG_SOC_GPIO_IN_RANGE_MAX=54 +CONFIG_SOC_GPIO_OUT_RANGE_MAX=54 +CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK=0 +CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT=16 +CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0x007FFFFFFFFF0000 +CONFIG_SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX=y +CONFIG_SOC_GPIO_CLOCKOUT_CHANNEL_NUM=2 +CONFIG_SOC_CLOCKOUT_SUPPORT_CHANNEL_DIVIDER=y +CONFIG_SOC_DEBUG_PROBE_NUM_UNIT=1 +CONFIG_SOC_DEBUG_PROBE_MAX_OUTPUT_WIDTH=16 +CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD=y +CONFIG_SOC_RTCIO_PIN_COUNT=16 +CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED=y +CONFIG_SOC_RTCIO_HOLD_SUPPORTED=y +CONFIG_SOC_RTCIO_WAKE_SUPPORTED=y +CONFIG_SOC_RTCIO_EDGE_WAKE_SUPPORTED=y +CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM=8 +CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM=8 +CONFIG_SOC_DEDIC_PERIPH_ALWAYS_ENABLE=y +CONFIG_SOC_ANA_CMPR_NUM=2 +CONFIG_SOC_ANA_CMPR_CAN_DISTINGUISH_EDGE=y +CONFIG_SOC_ANA_CMPR_SUPPORT_ETM=y +CONFIG_SOC_I2C_NUM=3 +CONFIG_SOC_HP_I2C_NUM=2 +CONFIG_SOC_I2C_FIFO_LEN=32 +CONFIG_SOC_I2C_CMD_REG_NUM=8 +CONFIG_SOC_I2C_SUPPORT_SLAVE=y +CONFIG_SOC_I2C_SUPPORT_HW_FSM_RST=y +CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS=y +CONFIG_SOC_I2C_SUPPORT_XTAL=y +CONFIG_SOC_I2C_SUPPORT_RTC=y +CONFIG_SOC_I2C_SUPPORT_10BIT_ADDR=y +CONFIG_SOC_I2C_SLAVE_SUPPORT_BROADCAST=y +CONFIG_SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE=y +CONFIG_SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS=y +CONFIG_SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH=y +CONFIG_SOC_I2C_SUPPORT_SLEEP_RETENTION=y +CONFIG_SOC_LP_I2C_NUM=1 +CONFIG_SOC_LP_I2C_FIFO_LEN=16 +CONFIG_SOC_I2S_NUM=3 +CONFIG_SOC_I2S_HW_VERSION_2=y +CONFIG_SOC_I2S_SUPPORTS_ETM=y +CONFIG_SOC_I2S_SUPPORTS_XTAL=y +CONFIG_SOC_I2S_SUPPORTS_APLL=y +CONFIG_SOC_I2S_SUPPORTS_PCM=y +CONFIG_SOC_I2S_SUPPORTS_PDM=y +CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y +CONFIG_SOC_I2S_SUPPORTS_PDM_RX=y +CONFIG_SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER=y +CONFIG_SOC_I2S_SUPPORTS_TX_SYNC_CNT=y +CONFIG_SOC_I2S_SUPPORTS_TDM=y +CONFIG_SOC_I2S_PDM_MAX_TX_LINES=2 +CONFIG_SOC_I2S_PDM_MAX_RX_LINES=4 +CONFIG_SOC_I2S_TDM_FULL_DATA_WIDTH=y +CONFIG_SOC_I2S_SUPPORT_SLEEP_RETENTION=y +CONFIG_SOC_LP_I2S_NUM=1 +CONFIG_SOC_ISP_BF_SUPPORTED=y +CONFIG_SOC_ISP_CCM_SUPPORTED=y +CONFIG_SOC_ISP_DEMOSAIC_SUPPORTED=y +CONFIG_SOC_ISP_DVP_SUPPORTED=y +CONFIG_SOC_ISP_SHARPEN_SUPPORTED=y +CONFIG_SOC_ISP_COLOR_SUPPORTED=y +CONFIG_SOC_ISP_LSC_SUPPORTED=y +CONFIG_SOC_ISP_SHARE_CSI_BRG=y +CONFIG_SOC_ISP_NUMS=1 +CONFIG_SOC_ISP_DVP_CTLR_NUMS=1 +CONFIG_SOC_ISP_AE_CTLR_NUMS=1 +CONFIG_SOC_ISP_AE_BLOCK_X_NUMS=5 +CONFIG_SOC_ISP_AE_BLOCK_Y_NUMS=5 +CONFIG_SOC_ISP_AF_CTLR_NUMS=1 +CONFIG_SOC_ISP_AF_WINDOW_NUMS=3 +CONFIG_SOC_ISP_BF_TEMPLATE_X_NUMS=3 +CONFIG_SOC_ISP_BF_TEMPLATE_Y_NUMS=3 +CONFIG_SOC_ISP_CCM_DIMENSION=3 +CONFIG_SOC_ISP_DEMOSAIC_GRAD_RATIO_INT_BITS=2 +CONFIG_SOC_ISP_DEMOSAIC_GRAD_RATIO_DEC_BITS=4 +CONFIG_SOC_ISP_DEMOSAIC_GRAD_RATIO_RES_BITS=26 +CONFIG_SOC_ISP_DVP_DATA_WIDTH_MAX=16 +CONFIG_SOC_ISP_SHARPEN_TEMPLATE_X_NUMS=3 +CONFIG_SOC_ISP_SHARPEN_TEMPLATE_Y_NUMS=3 +CONFIG_SOC_ISP_SHARPEN_H_FREQ_COEF_INT_BITS=3 +CONFIG_SOC_ISP_SHARPEN_H_FREQ_COEF_DEC_BITS=5 +CONFIG_SOC_ISP_SHARPEN_H_FREQ_COEF_RES_BITS=24 +CONFIG_SOC_ISP_SHARPEN_M_FREQ_COEF_INT_BITS=3 +CONFIG_SOC_ISP_SHARPEN_M_FREQ_COEF_DEC_BITS=5 +CONFIG_SOC_ISP_SHARPEN_M_FREQ_COEF_RES_BITS=24 +CONFIG_SOC_ISP_HIST_CTLR_NUMS=1 +CONFIG_SOC_ISP_HIST_BLOCK_X_NUMS=5 +CONFIG_SOC_ISP_HIST_BLOCK_Y_NUMS=5 +CONFIG_SOC_ISP_HIST_SEGMENT_NUMS=16 +CONFIG_SOC_ISP_HIST_INTERVAL_NUMS=15 +CONFIG_SOC_ISP_LSC_GRAD_RATIO_INT_BITS=2 +CONFIG_SOC_ISP_LSC_GRAD_RATIO_DEC_BITS=8 +CONFIG_SOC_ISP_LSC_GRAD_RATIO_RES_BITS=22 +CONFIG_SOC_LEDC_SUPPORT_PLL_DIV_CLOCK=y +CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y +CONFIG_SOC_LEDC_TIMER_NUM=4 +CONFIG_SOC_LEDC_CHANNEL_NUM=8 +CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=20 +CONFIG_SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED=y +CONFIG_SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX=16 +CONFIG_SOC_LEDC_SUPPORT_FADE_STOP=y +CONFIG_SOC_LEDC_FADE_PARAMS_BIT_WIDTH=10 +CONFIG_SOC_LEDC_SUPPORT_SLEEP_RETENTION=y +CONFIG_SOC_MMU_PERIPH_NUM=2 +CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=2 +CONFIG_SOC_MMU_DI_VADDR_SHARED=y +CONFIG_SOC_MMU_PER_EXT_MEM_TARGET=y +CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000 +CONFIG_SOC_MPU_REGIONS_MAX_NUM=8 +CONFIG_SOC_PCNT_GROUPS=1 +CONFIG_SOC_PCNT_UNITS_PER_GROUP=4 +CONFIG_SOC_PCNT_CHANNELS_PER_UNIT=2 +CONFIG_SOC_PCNT_THRES_POINT_PER_UNIT=2 +CONFIG_SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE=y +CONFIG_SOC_PCNT_SUPPORT_CLEAR_SIGNAL=y +CONFIG_SOC_PCNT_SUPPORT_SLEEP_RETENTION=y +CONFIG_SOC_RMT_GROUPS=1 +CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=4 +CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=4 +CONFIG_SOC_RMT_CHANNELS_PER_GROUP=8 +CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL=48 +CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG=y +CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION=y +CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP=y +CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT=y +CONFIG_SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP=y +CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO=y +CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY=y +CONFIG_SOC_RMT_SUPPORT_XTAL=y +CONFIG_SOC_RMT_SUPPORT_RC_FAST=y +CONFIG_SOC_RMT_SUPPORT_DMA=y +CONFIG_SOC_RMT_SUPPORT_SLEEP_RETENTION=y +CONFIG_SOC_LCD_I80_SUPPORTED=y +CONFIG_SOC_LCD_RGB_SUPPORTED=y +CONFIG_SOC_LCDCAM_I80_NUM_BUSES=1 +CONFIG_SOC_LCDCAM_I80_BUS_WIDTH=24 +CONFIG_SOC_LCDCAM_RGB_NUM_PANELS=1 +CONFIG_SOC_LCDCAM_RGB_DATA_WIDTH=24 +CONFIG_SOC_LCD_SUPPORT_RGB_YUV_CONV=y +CONFIG_SOC_MCPWM_GROUPS=2 +CONFIG_SOC_MCPWM_TIMERS_PER_GROUP=3 +CONFIG_SOC_MCPWM_OPERATORS_PER_GROUP=3 +CONFIG_SOC_MCPWM_COMPARATORS_PER_OPERATOR=2 +CONFIG_SOC_MCPWM_EVENT_COMPARATORS_PER_OPERATOR=2 +CONFIG_SOC_MCPWM_GENERATORS_PER_OPERATOR=2 +CONFIG_SOC_MCPWM_TRIGGERS_PER_OPERATOR=2 +CONFIG_SOC_MCPWM_GPIO_FAULTS_PER_GROUP=3 +CONFIG_SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP=y +CONFIG_SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER=3 +CONFIG_SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP=3 +CONFIG_SOC_MCPWM_SWSYNC_CAN_PROPAGATE=y +CONFIG_SOC_MCPWM_SUPPORT_ETM=y +CONFIG_SOC_MCPWM_SUPPORT_EVENT_COMPARATOR=y +CONFIG_SOC_MCPWM_CAPTURE_CLK_FROM_GROUP=y +CONFIG_SOC_MCPWM_SUPPORT_SLEEP_RETENTION=y +CONFIG_SOC_USB_OTG_PERIPH_NUM=2 +CONFIG_SOC_USB_UTMI_PHY_NUM=1 +CONFIG_SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO=y +CONFIG_SOC_PARLIO_GROUPS=1 +CONFIG_SOC_PARLIO_TX_UNITS_PER_GROUP=1 +CONFIG_SOC_PARLIO_RX_UNITS_PER_GROUP=1 +CONFIG_SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH=16 +CONFIG_SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH=16 +CONFIG_SOC_PARLIO_TX_CLK_SUPPORT_GATING=y +CONFIG_SOC_PARLIO_RX_CLK_SUPPORT_GATING=y +CONFIG_SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT=y +CONFIG_SOC_PARLIO_TRANS_BIT_ALIGN=y +CONFIG_SOC_PARLIO_TX_SIZE_BY_DMA=y +CONFIG_SOC_PARLIO_SUPPORT_SLEEP_RETENTION=y +CONFIG_SOC_MPI_MEM_BLOCKS_NUM=4 +CONFIG_SOC_MPI_OPERATIONS_NUM=3 +CONFIG_SOC_RSA_MAX_BIT_LEN=4096 +CONFIG_SOC_SDMMC_USE_IOMUX=y +CONFIG_SOC_SDMMC_USE_GPIO_MATRIX=y +CONFIG_SOC_SDMMC_NUM_SLOTS=2 +CONFIG_SOC_SDMMC_DELAY_PHASE_NUM=4 +CONFIG_SOC_SDMMC_IO_POWER_EXTERNAL=y +CONFIG_SOC_SDMMC_PSRAM_DMA_CAPABLE=y +CONFIG_SOC_SDMMC_UHS_I_SUPPORTED=y +CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE=3968 +CONFIG_SOC_SHA_SUPPORT_DMA=y +CONFIG_SOC_SHA_SUPPORT_RESUME=y +CONFIG_SOC_SHA_GDMA=y +CONFIG_SOC_SHA_SUPPORT_SHA1=y +CONFIG_SOC_SHA_SUPPORT_SHA224=y +CONFIG_SOC_SHA_SUPPORT_SHA256=y +CONFIG_SOC_SHA_SUPPORT_SHA384=y +CONFIG_SOC_SHA_SUPPORT_SHA512=y +CONFIG_SOC_SHA_SUPPORT_SHA512_224=y +CONFIG_SOC_SHA_SUPPORT_SHA512_256=y +CONFIG_SOC_SHA_SUPPORT_SHA512_T=y +CONFIG_SOC_ECDSA_SUPPORT_EXPORT_PUBKEY=y +CONFIG_SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE=y +CONFIG_SOC_ECDSA_USES_MPI=y +CONFIG_SOC_SDM_GROUPS=1 +CONFIG_SOC_SDM_CHANNELS_PER_GROUP=8 +CONFIG_SOC_SDM_CLK_SUPPORT_PLL_F80M=y +CONFIG_SOC_SDM_CLK_SUPPORT_XTAL=y +CONFIG_SOC_SPI_PERIPH_NUM=3 +CONFIG_SOC_SPI_MAX_CS_NUM=6 +CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64 +CONFIG_SOC_SPI_SUPPORT_SLEEP_RETENTION=y +CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2=y +CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS=y +CONFIG_SOC_SPI_SUPPORT_DDRCLK=y +CONFIG_SOC_SPI_SUPPORT_CD_SIG=y +CONFIG_SOC_SPI_SUPPORT_OCT=y +CONFIG_SOC_SPI_SUPPORT_CLK_XTAL=y +CONFIG_SOC_SPI_SUPPORT_CLK_RC_FAST=y +CONFIG_SOC_SPI_SUPPORT_CLK_SPLL=y +CONFIG_SOC_MSPI_HAS_INDEPENT_IOMUX=y +CONFIG_SOC_MEMSPI_IS_INDEPENDENT=y +CONFIG_SOC_SPI_MAX_PRE_DIVIDER=16 +CONFIG_SOC_LP_SPI_PERIPH_NUM=y +CONFIG_SOC_LP_SPI_MAXIMUM_BUFFER_SIZE=64 +CONFIG_SOC_SPIRAM_XIP_SUPPORTED=y +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE=y +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND=y +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME=y +CONFIG_SOC_SPI_MEM_SUPPORT_IDLE_INTR=y +CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND=y +CONFIG_SOC_SPI_MEM_SUPPORT_CHECK_SUS=y +CONFIG_SOC_SPI_MEM_SUPPORT_TIMING_TUNING=y +CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_DQS=y +CONFIG_SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP=y +CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT=y +CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y +CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y +CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y +CONFIG_SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT=y +CONFIG_SOC_SYSTIMER_COUNTER_NUM=2 +CONFIG_SOC_SYSTIMER_ALARM_NUM=3 +CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO=32 +CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI=20 +CONFIG_SOC_SYSTIMER_FIXED_DIVIDER=y +CONFIG_SOC_SYSTIMER_SUPPORT_RC_FAST=y +CONFIG_SOC_SYSTIMER_INT_LEVEL=y +CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE=y +CONFIG_SOC_SYSTIMER_SUPPORT_ETM=y +CONFIG_SOC_LP_TIMER_BIT_WIDTH_LO=32 +CONFIG_SOC_LP_TIMER_BIT_WIDTH_HI=16 +CONFIG_SOC_TIMER_GROUPS=2 +CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=2 +CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=54 +CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL=y +CONFIG_SOC_TIMER_GROUP_SUPPORT_RC_FAST=y +CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=4 +CONFIG_SOC_TIMER_SUPPORT_ETM=y +CONFIG_SOC_TIMER_SUPPORT_SLEEP_RETENTION=y +CONFIG_SOC_MWDT_SUPPORT_XTAL=y +CONFIG_SOC_MWDT_SUPPORT_SLEEP_RETENTION=y +CONFIG_SOC_TOUCH_SENSOR_VERSION=3 +CONFIG_SOC_TOUCH_SENSOR_NUM=14 +CONFIG_SOC_TOUCH_SUPPORT_SLEEP_WAKEUP=y +CONFIG_SOC_TOUCH_SUPPORT_WATERPROOF=y +CONFIG_SOC_TOUCH_SUPPORT_PROX_SENSING=y +CONFIG_SOC_TOUCH_PROXIMITY_CHANNEL_NUM=3 +CONFIG_SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED=y +CONFIG_SOC_TOUCH_SUPPORT_FREQ_HOP=y +CONFIG_SOC_TOUCH_SAMPLE_CFG_NUM=3 +CONFIG_SOC_TWAI_CONTROLLER_NUM=3 +CONFIG_SOC_TWAI_CLK_SUPPORT_XTAL=y +CONFIG_SOC_TWAI_BRP_MIN=2 +CONFIG_SOC_TWAI_BRP_MAX=32768 +CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS=y +CONFIG_SOC_TWAI_SUPPORT_SLEEP_RETENTION=y +CONFIG_SOC_EFUSE_DIS_PAD_JTAG=y +CONFIG_SOC_EFUSE_DIS_USB_JTAG=y +CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT=y +CONFIG_SOC_EFUSE_SOFT_DIS_JTAG=y +CONFIG_SOC_EFUSE_DIS_DOWNLOAD_MSPI=y +CONFIG_SOC_EFUSE_ECDSA_KEY=y +CONFIG_SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY=y +CONFIG_SOC_KEY_MANAGER_FE_KEY_DEPLOY=y +CONFIG_SOC_SECURE_BOOT_V2_RSA=y +CONFIG_SOC_SECURE_BOOT_V2_ECC=y +CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3 +CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y +CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY=y +CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=64 +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_256=y +CONFIG_SOC_UART_NUM=6 +CONFIG_SOC_UART_HP_NUM=5 +CONFIG_SOC_UART_LP_NUM=1 +CONFIG_SOC_UART_FIFO_LEN=128 +CONFIG_SOC_LP_UART_FIFO_LEN=16 +CONFIG_SOC_UART_BITRATE_MAX=5000000 +CONFIG_SOC_UART_SUPPORT_PLL_F80M_CLK=y +CONFIG_SOC_UART_SUPPORT_RTC_CLK=y +CONFIG_SOC_UART_SUPPORT_XTAL_CLK=y +CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y +CONFIG_SOC_UART_HAS_LP_UART=y +CONFIG_SOC_UART_SUPPORT_SLEEP_RETENTION=y +CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND=y +CONFIG_SOC_LP_I2S_SUPPORT_VAD=y +CONFIG_SOC_COEX_HW_PTI=y +CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21 +CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH=12 +CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN=y +CONFIG_SOC_PM_EXT1_WAKEUP_BY_PMU=y +CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_XTAL32K_PD=y +CONFIG_SOC_PM_SUPPORT_RC32K_PD=y +CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y +CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y +CONFIG_SOC_PM_SUPPORT_TOP_PD=y +CONFIG_SOC_PM_SUPPORT_CNNT_PD=y +CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD=y +CONFIG_SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY=y +CONFIG_SOC_PM_CPU_RETENTION_BY_SW=y +CONFIG_SOC_PM_CACHE_RETENTION_BY_PAU=y +CONFIG_SOC_PM_PAU_LINK_NUM=4 +CONFIG_SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR=y +CONFIG_SOC_PAU_IN_TOP_DOMAIN=y +CONFIG_SOC_CPU_IN_TOP_DOMAIN=y +CONFIG_SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE=y +CONFIG_SOC_SLEEP_SYSTIMER_STALL_WORKAROUND=y +CONFIG_SOC_SLEEP_TGWDT_STOP_WORKAROUND=y +CONFIG_SOC_PM_RETENTION_MODULE_NUM=64 +CONFIG_SOC_PSRAM_VDD_POWER_MPLL=y +CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y +CONFIG_SOC_CLK_APLL_SUPPORTED=y +CONFIG_SOC_CLK_MPLL_SUPPORTED=y +CONFIG_SOC_CLK_SDIO_PLL_SUPPORTED=y +CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y +CONFIG_SOC_CLK_RC32K_SUPPORTED=y +CONFIG_SOC_CLK_LP_FAST_SUPPORT_LP_PLL=y +CONFIG_SOC_CLK_LP_FAST_SUPPORT_XTAL=y +CONFIG_SOC_PERIPH_CLK_CTRL_SHARED=y +CONFIG_SOC_TEMPERATURE_SENSOR_LP_PLL_SUPPORT=y +CONFIG_SOC_TEMPERATURE_SENSOR_INTR_SUPPORT=y +CONFIG_SOC_TSENS_IS_INDEPENDENT_FROM_ADC=y +CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_ETM=y +CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION=y +CONFIG_SOC_MEM_TCM_SUPPORTED=y +CONFIG_SOC_MEM_NON_CONTIGUOUS_SRAM=y +CONFIG_SOC_ASYNCHRONOUS_BUS_ERROR_MODE=y +CONFIG_SOC_EMAC_IEEE_1588_SUPPORT=y +CONFIG_SOC_EMAC_USE_MULTI_IO_MUX=y +CONFIG_SOC_EMAC_MII_USE_GPIO_MATRIX=y +CONFIG_SOC_JPEG_CODEC_SUPPORTED=y +CONFIG_SOC_JPEG_DECODE_SUPPORTED=y +CONFIG_SOC_JPEG_ENCODE_SUPPORTED=y +CONFIG_SOC_LCDCAM_CAM_SUPPORT_RGB_YUV_CONV=y +CONFIG_SOC_LCDCAM_CAM_PERIPH_NUM=1 +CONFIG_SOC_LCDCAM_CAM_DATA_WIDTH_MAX=16 +CONFIG_SOC_LP_CORE_SUPPORT_ETM=y +CONFIG_SOC_LP_CORE_SUPPORT_LP_ADC=y +CONFIG_SOC_LP_CORE_SUPPORT_LP_VAD=y +CONFIG_IDF_CMAKE=y +CONFIG_IDF_TOOLCHAIN="gcc" +CONFIG_IDF_TOOLCHAIN_GCC=y +CONFIG_IDF_TARGET_ARCH_RISCV=y +CONFIG_IDF_TARGET_ARCH="riscv" +CONFIG_IDF_TARGET="esp32p4" +CONFIG_IDF_INIT_VERSION="5.4.2" +CONFIG_IDF_TARGET_ESP32P4=y +CONFIG_IDF_FIRMWARE_CHIP_ID=0x0012 + +# +# Build type +# +CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y +# CONFIG_APP_BUILD_TYPE_RAM is not set +CONFIG_APP_BUILD_GENERATE_BINARIES=y +CONFIG_APP_BUILD_BOOTLOADER=y +CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y +# CONFIG_APP_REPRODUCIBLE_BUILD is not set +# CONFIG_APP_NO_BLOBS is not set +# end of Build type + +# +# Bootloader config +# + +# +# Bootloader manager +# +CONFIG_BOOTLOADER_COMPILE_TIME_DATE=y +CONFIG_BOOTLOADER_PROJECT_VER=1 +# end of Bootloader manager + +CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x2000 +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set + +# +# Log +# +CONFIG_BOOTLOADER_LOG_LEVEL_NONE=y +# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_INFO is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set +CONFIG_BOOTLOADER_LOG_LEVEL=0 + +# +# Format +# +# CONFIG_BOOTLOADER_LOG_COLORS is not set +CONFIG_BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS=y +# end of Format +# end of Log + +# +# Serial Flash Configurations +# +# CONFIG_BOOTLOADER_FLASH_DC_AWARE is not set +CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y +# end of Serial Flash Configurations + +# CONFIG_BOOTLOADER_FACTORY_RESET is not set +# CONFIG_BOOTLOADER_APP_TEST is not set +CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE=y +CONFIG_BOOTLOADER_WDT_ENABLE=y +# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 +CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE=y +# CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK is not set +CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP=y +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set +CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0x10 +# CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set +CONFIG_BOOTLOADER_RESERVE_RTC_MEM=y +# end of Bootloader config + +# +# Security features +# +CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED=y +CONFIG_SECURE_BOOT_V2_ECC_SUPPORTED=y +CONFIG_SECURE_BOOT_V2_PREFERRED=y +# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set +# CONFIG_SECURE_BOOT is not set +# CONFIG_SECURE_FLASH_ENC_ENABLED is not set +CONFIG_SECURE_ROM_DL_MODE_ENABLED=y +# end of Security features + +# +# Application manager +# +# CONFIG_APP_COMPILE_TIME_DATE is not set +# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set +# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set +# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set +CONFIG_APP_RETRIEVE_LEN_ELF_SHA=9 +# end of Application manager + +CONFIG_ESP_ROM_HAS_CRC_LE=y +CONFIG_ESP_ROM_HAS_CRC_BE=y +CONFIG_ESP_ROM_UART_CLK_IS_XTAL=y +CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM=6 +CONFIG_ESP_ROM_USB_OTG_NUM=5 +CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING=y +CONFIG_ESP_ROM_GET_CLK_FREQ=y +CONFIG_ESP_ROM_HAS_RVFPLIB=y +CONFIG_ESP_ROM_HAS_HAL_WDT=y +CONFIG_ESP_ROM_HAS_HAL_SYSTIMER=y +CONFIG_ESP_ROM_HAS_LAYOUT_TABLE=y +CONFIG_ESP_ROM_WDT_INIT_PATCH=y +CONFIG_ESP_ROM_HAS_LP_ROM=y +CONFIG_ESP_ROM_WITHOUT_REGI2C=y +CONFIG_ESP_ROM_HAS_NEWLIB=y +CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y +CONFIG_ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG=y +CONFIG_ESP_ROM_HAS_VERSION=y +CONFIG_ESP_ROM_CLIC_INT_TYPE_PATCH=y +CONFIG_ESP_ROM_HAS_OUTPUT_PUTC_FUNC=y + +# +# Boot ROM Behavior +# +CONFIG_BOOT_ROM_LOG_ALWAYS_ON=y +# CONFIG_BOOT_ROM_LOG_ALWAYS_OFF is not set +# CONFIG_BOOT_ROM_LOG_ON_GPIO_HIGH is not set +# CONFIG_BOOT_ROM_LOG_ON_GPIO_LOW is not set +# end of Boot ROM Behavior + +# +# Serial flasher config +# +# CONFIG_ESPTOOLPY_NO_STUB is not set +# CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set +# CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE_DIO=y +# CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set +CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y +CONFIG_ESPTOOLPY_FLASHMODE="dio" +CONFIG_ESPTOOLPY_FLASHFREQ_80M=y +# CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set +CONFIG_ESPTOOLPY_FLASHFREQ_VAL=80 +CONFIG_ESPTOOLPY_FLASHFREQ="80m" +# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_32MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE="4MB" +# CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE is not set +CONFIG_ESPTOOLPY_BEFORE_RESET=y +# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +# CONFIG_ESPTOOLPY_AFTER_NORESET is not set +CONFIG_ESPTOOLPY_AFTER="hard_reset" +CONFIG_ESPTOOLPY_MONITOR_BAUD=115200 +# end of Serial flasher config + +# +# Partition Table +# +# CONFIG_PARTITION_TABLE_SINGLE_APP is not set +# CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE is not set +# CONFIG_PARTITION_TABLE_TWO_OTA is not set +# CONFIG_PARTITION_TABLE_TWO_OTA_LARGE is not set +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y +# end of Partition Table + +# +# Compiler options +# +# CONFIG_COMPILER_OPTIMIZATION_DEBUG is not set +CONFIG_COMPILER_OPTIMIZATION_SIZE=y +# CONFIG_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_COMPILER_OPTIMIZATION_NONE is not set +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE is not set +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE=y +CONFIG_COMPILER_ASSERT_NDEBUG_EVALUATE=y +# CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB is not set +CONFIG_COMPILER_FLOAT_LIB_FROM_RVFPLIB=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=0 +# CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set +CONFIG_COMPILER_HIDE_PATHS_MACROS=y +# CONFIG_COMPILER_CXX_EXCEPTIONS is not set +# CONFIG_COMPILER_CXX_RTTI is not set +CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y +# CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set +# CONFIG_COMPILER_NO_MERGE_CONSTANTS is not set +# CONFIG_COMPILER_WARN_WRITE_STRINGS is not set +# CONFIG_COMPILER_SAVE_RESTORE_LIBCALLS is not set +CONFIG_COMPILER_DISABLE_DEFAULT_ERRORS=y +# CONFIG_COMPILER_DISABLE_GCC12_WARNINGS is not set +# CONFIG_COMPILER_DISABLE_GCC13_WARNINGS is not set +# CONFIG_COMPILER_DISABLE_GCC14_WARNINGS is not set +# CONFIG_COMPILER_DUMP_RTL_FILES is not set +CONFIG_COMPILER_RT_LIB_GCCLIB=y +CONFIG_COMPILER_RT_LIB_NAME="gcc" +# CONFIG_COMPILER_ORPHAN_SECTIONS_WARNING is not set +CONFIG_COMPILER_ORPHAN_SECTIONS_PLACE=y +# CONFIG_COMPILER_STATIC_ANALYZER is not set +# end of Compiler options + +# +# Component config +# + +# +# Application Level Tracing +# +# CONFIG_APPTRACE_DEST_JTAG is not set +CONFIG_APPTRACE_DEST_NONE=y +# CONFIG_APPTRACE_DEST_UART1 is not set +# CONFIG_APPTRACE_DEST_UART2 is not set +CONFIG_APPTRACE_DEST_UART_NONE=y +CONFIG_APPTRACE_UART_TASK_PRIO=1 +CONFIG_APPTRACE_LOCK_ENABLE=y +# end of Application Level Tracing + +# +# Bluetooth +# +# CONFIG_BT_ENABLED is not set + +# +# Common Options +# +# CONFIG_BT_BLE_LOG_SPI_OUT_ENABLED is not set +# end of Common Options +# end of Bluetooth + +# +# Console Library +# +# CONFIG_CONSOLE_SORTED_HELP is not set +# end of Console Library + +# +# Driver Configurations +# + +# +# TWAI Configuration +# +# CONFIG_TWAI_ISR_IN_IRAM is not set +# end of TWAI Configuration + +# +# Legacy ADC Driver Configuration +# +# CONFIG_ADC_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_ADC_SKIP_LEGACY_CONFLICT_CHECK is not set + +# +# Legacy ADC Calibration Configuration +# +# CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy ADC Calibration Configuration +# end of Legacy ADC Driver Configuration + +# +# Legacy MCPWM Driver Configurations +# +# CONFIG_MCPWM_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_MCPWM_SKIP_LEGACY_CONFLICT_CHECK is not set +# end of Legacy MCPWM Driver Configurations + +# +# Legacy Timer Group Driver Configurations +# +# CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_GPTIMER_SKIP_LEGACY_CONFLICT_CHECK is not set +# end of Legacy Timer Group Driver Configurations + +# +# Legacy RMT Driver Configurations +# +# CONFIG_RMT_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_RMT_SKIP_LEGACY_CONFLICT_CHECK is not set +# end of Legacy RMT Driver Configurations + +# +# Legacy I2S Driver Configurations +# +# CONFIG_I2S_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_I2S_SKIP_LEGACY_CONFLICT_CHECK is not set +# end of Legacy I2S Driver Configurations + +# +# Legacy I2C Driver Configurations +# +# CONFIG_I2C_SKIP_LEGACY_CONFLICT_CHECK is not set +# end of Legacy I2C Driver Configurations + +# +# Legacy PCNT Driver Configurations +# +# CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_PCNT_SKIP_LEGACY_CONFLICT_CHECK is not set +# end of Legacy PCNT Driver Configurations + +# +# Legacy SDM Driver Configurations +# +# CONFIG_SDM_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_SDM_SKIP_LEGACY_CONFLICT_CHECK is not set +# end of Legacy SDM Driver Configurations + +# +# Legacy Temperature Sensor Driver Configurations +# +# CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_TEMP_SENSOR_SKIP_LEGACY_CONFLICT_CHECK is not set +# end of Legacy Temperature Sensor Driver Configurations +# end of Driver Configurations + +# +# eFuse Bit Manager +# +# CONFIG_EFUSE_CUSTOM_TABLE is not set +# CONFIG_EFUSE_VIRTUAL is not set +CONFIG_EFUSE_MAX_BLK_LEN=256 +# end of eFuse Bit Manager + +# +# ESP-TLS +# +CONFIG_ESP_TLS_USING_MBEDTLS=y +CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y +# CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set +# CONFIG_ESP_TLS_SERVER_SESSION_TICKETS is not set +# CONFIG_ESP_TLS_SERVER_CERT_SELECT_HOOK is not set +# CONFIG_ESP_TLS_SERVER_MIN_AUTH_MODE_OPTIONAL is not set +# CONFIG_ESP_TLS_PSK_VERIFICATION is not set +# CONFIG_ESP_TLS_INSECURE is not set +# end of ESP-TLS + +# +# ADC and ADC Calibration +# +# CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set +# CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set +# CONFIG_ADC_ENABLE_DEBUG_LOG is not set +# end of ADC and ADC Calibration + +# +# Wireless Coexistence +# +# CONFIG_ESP_COEX_GPIO_DEBUG is not set +# end of Wireless Coexistence + +# +# Common ESP-related +# +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y +# end of Common ESP-related + +# +# ESP-Driver:Analog Comparator Configurations +# +# CONFIG_ANA_CMPR_ISR_IRAM_SAFE is not set +# CONFIG_ANA_CMPR_CTRL_FUNC_IN_IRAM is not set +# CONFIG_ANA_CMPR_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:Analog Comparator Configurations + +# +# ESP-Driver:Camera Controller Configurations +# +# CONFIG_CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE is not set +# CONFIG_CAM_CTLR_ISP_DVP_ISR_CACHE_SAFE is not set +# CONFIG_CAM_CTLR_DVP_CAM_ISR_CACHE_SAFE is not set +# end of ESP-Driver:Camera Controller Configurations + +# +# ESP-Driver:GPIO Configurations +# +# CONFIG_GPIO_CTRL_FUNC_IN_IRAM is not set +# end of ESP-Driver:GPIO Configurations + +# +# ESP-Driver:GPTimer Configurations +# +CONFIG_GPTIMER_ISR_HANDLER_IN_IRAM=y +# CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set +# CONFIG_GPTIMER_ISR_IRAM_SAFE is not set +CONFIG_GPTIMER_OBJ_CACHE_SAFE=y +# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:GPTimer Configurations + +# +# ESP-Driver:I2C Configurations +# +# CONFIG_I2C_ISR_IRAM_SAFE is not set +# CONFIG_I2C_ENABLE_DEBUG_LOG is not set +# CONFIG_I2C_ENABLE_SLAVE_DRIVER_VERSION_2 is not set +# end of ESP-Driver:I2C Configurations + +# +# ESP-Driver:I2S Configurations +# +CONFIG_I2S_ISR_IRAM_SAFE=y +# CONFIG_I2S_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:I2S Configurations + +# +# ESP-Driver:ISP Configurations +# +# CONFIG_ISP_ISR_IRAM_SAFE is not set +# CONFIG_ISP_CTRL_FUNC_IN_IRAM is not set +# end of ESP-Driver:ISP Configurations + +# +# ESP-Driver:JPEG-Codec Configurations +# +# CONFIG_JPEG_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:JPEG-Codec Configurations + +# +# ESP-Driver:LEDC Configurations +# +# CONFIG_LEDC_CTRL_FUNC_IN_IRAM is not set +# end of ESP-Driver:LEDC Configurations + +# +# ESP-Driver:MCPWM Configurations +# +# CONFIG_MCPWM_ISR_IRAM_SAFE is not set +# CONFIG_MCPWM_CTRL_FUNC_IN_IRAM is not set +# CONFIG_MCPWM_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:MCPWM Configurations + +# +# ESP-Driver:Parallel IO Configurations +# +# CONFIG_PARLIO_ENABLE_DEBUG_LOG is not set +# CONFIG_PARLIO_ISR_IRAM_SAFE is not set +# end of ESP-Driver:Parallel IO Configurations + +# +# ESP-Driver:PCNT Configurations +# +# CONFIG_PCNT_CTRL_FUNC_IN_IRAM is not set +# CONFIG_PCNT_ISR_IRAM_SAFE is not set +# CONFIG_PCNT_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:PCNT Configurations + +# +# ESP-Driver:RMT Configurations +# +# CONFIG_RMT_ISR_IRAM_SAFE is not set +# CONFIG_RMT_RECV_FUNC_IN_IRAM is not set +# CONFIG_RMT_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:RMT Configurations + +# +# ESP-Driver:Sigma Delta Modulator Configurations +# +# CONFIG_SDM_CTRL_FUNC_IN_IRAM is not set +# CONFIG_SDM_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:Sigma Delta Modulator Configurations + +# +# ESP-Driver:SPI Configurations +# +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +# CONFIG_SPI_SLAVE_IN_IRAM is not set +# CONFIG_SPI_SLAVE_ISR_IN_IRAM is not set +# end of ESP-Driver:SPI Configurations + +# +# ESP-Driver:Touch Sensor Configurations +# +# CONFIG_TOUCH_CTRL_FUNC_IN_IRAM is not set +# CONFIG_TOUCH_ISR_IRAM_SAFE is not set +# CONFIG_TOUCH_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:Touch Sensor Configurations + +# +# ESP-Driver:Temperature Sensor Configurations +# +# CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set +# CONFIG_TEMP_SENSOR_ISR_IRAM_SAFE is not set +# end of ESP-Driver:Temperature Sensor Configurations + +# +# ESP-Driver:UART Configurations +# +CONFIG_UART_ISR_IN_IRAM=y +# end of ESP-Driver:UART Configurations + +# +# ESP-Driver:USB Serial/JTAG Configuration +# +CONFIG_USJ_ENABLE_USB_SERIAL_JTAG=y +# end of ESP-Driver:USB Serial/JTAG Configuration + +# +# Ethernet +# +CONFIG_ETH_ENABLED=y +CONFIG_ETH_USE_ESP32_EMAC=y +CONFIG_ETH_PHY_INTERFACE_RMII=y +CONFIG_ETH_DMA_BUFFER_SIZE=512 +CONFIG_ETH_DMA_RX_BUFFER_NUM=20 +CONFIG_ETH_DMA_TX_BUFFER_NUM=10 +# CONFIG_ETH_SOFT_FLOW_CONTROL is not set +# CONFIG_ETH_IRAM_OPTIMIZATION is not set +CONFIG_ETH_USE_SPI_ETHERNET=y +CONFIG_ETH_SPI_ETHERNET_DM9051=y +CONFIG_ETH_SPI_ETHERNET_W5500=y +# CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL is not set +# CONFIG_ETH_USE_OPENETH is not set +# CONFIG_ETH_TRANSMIT_MUTEX is not set +# end of Ethernet + +# +# Event Loop Library +# +# CONFIG_ESP_EVENT_LOOP_PROFILING is not set +CONFIG_ESP_EVENT_POST_FROM_ISR=y +CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y +# end of Event Loop Library + +# +# GDB Stub +# +CONFIG_ESP_GDBSTUB_ENABLED=y +# CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set +CONFIG_ESP_GDBSTUB_SUPPORT_TASKS=y +CONFIG_ESP_GDBSTUB_MAX_TASKS=32 +# end of GDB Stub + +# +# ESP HID +# +CONFIG_ESPHID_TASK_SIZE_BT=2048 +CONFIG_ESPHID_TASK_SIZE_BLE=4096 +# end of ESP HID + +# +# ESP HTTP client +# +# CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS is not set +# CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set +# CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH is not set +# CONFIG_ESP_HTTP_CLIENT_ENABLE_CUSTOM_TRANSPORT is not set +CONFIG_ESP_HTTP_CLIENT_EVENT_POST_TIMEOUT=2000 +# end of ESP HTTP client + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 +CONFIG_HTTPD_ERR_RESP_NO_DELAY=y +CONFIG_HTTPD_PURGE_BUF_LEN=32 +# CONFIG_HTTPD_LOG_PURGE_DATA is not set +# CONFIG_HTTPD_WS_SUPPORT is not set +# CONFIG_HTTPD_QUEUE_WORK_BLOCKING is not set +CONFIG_HTTPD_SERVER_EVENT_POST_TIMEOUT=2000 +# end of HTTP Server + +# +# ESP HTTPS OTA +# +# CONFIG_ESP_HTTPS_OTA_DECRYPT_CB is not set +# CONFIG_ESP_HTTPS_OTA_ALLOW_HTTP is not set +CONFIG_ESP_HTTPS_OTA_EVENT_POST_TIMEOUT=2000 +# end of ESP HTTPS OTA + +# +# ESP HTTPS server +# +CONFIG_ESP_HTTPS_SERVER_EVENT_POST_TIMEOUT=2000 +# end of ESP HTTPS server + +# +# Hardware Settings +# + +# +# Chip revision +# +# CONFIG_ESP32P4_REV_MIN_0 is not set +CONFIG_ESP32P4_REV_MIN_1=y +# CONFIG_ESP32P4_REV_MIN_100 is not set +CONFIG_ESP32P4_REV_MIN_FULL=1 +CONFIG_ESP_REV_MIN_FULL=1 + +# +# Maximum Supported ESP32-P4 Revision (Rev v1.99) +# +CONFIG_ESP32P4_REV_MAX_FULL=199 +CONFIG_ESP_REV_MAX_FULL=199 +CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL=0 +CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL=99 + +# +# Maximum Supported ESP32-P4 eFuse Block Revision (eFuse Block Rev v0.99) +# +# end of Chip revision + +# +# MAC Config +# +CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y +CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_ONE=y +CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES=1 +CONFIG_ESP32P4_UNIVERSAL_MAC_ADDRESSES_ONE=y +CONFIG_ESP32P4_UNIVERSAL_MAC_ADDRESSES=1 +# CONFIG_ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC is not set +# end of MAC Config + +# +# Sleep Config +# +CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y +CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND=y +# CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU is not set +# CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND is not set +CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY=0 +# CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION is not set +# CONFIG_ESP_SLEEP_DEBUG is not set +CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS=y +# end of Sleep Config + +# +# RTC Clock Config +# +CONFIG_RTC_CLK_SRC_INT_RC=y +# CONFIG_RTC_CLK_SRC_EXT_CRYS is not set +CONFIG_RTC_CLK_CAL_CYCLES=1024 +CONFIG_RTC_FAST_CLK_SRC_RC_FAST=y +# CONFIG_RTC_FAST_CLK_SRC_XTAL is not set +# end of RTC Clock Config + +# +# Peripheral Control +# +# CONFIG_PERIPH_CTRL_FUNC_IN_IRAM is not set +# end of Peripheral Control + +# +# ETM Configuration +# +# CONFIG_ETM_ENABLE_DEBUG_LOG is not set +# end of ETM Configuration + +# +# GDMA Configurations +# +CONFIG_GDMA_CTRL_FUNC_IN_IRAM=y +CONFIG_GDMA_ISR_HANDLER_IN_IRAM=y +CONFIG_GDMA_OBJ_DRAM_SAFE=y +# CONFIG_GDMA_ENABLE_DEBUG_LOG is not set +# CONFIG_GDMA_ISR_IRAM_SAFE is not set +# end of GDMA Configurations + +# +# DW_GDMA Configurations +# +# CONFIG_DW_GDMA_ENABLE_DEBUG_LOG is not set +# end of DW_GDMA Configurations + +# +# 2D-DMA Configurations +# +# CONFIG_DMA2D_OPERATION_FUNC_IN_IRAM is not set +# CONFIG_DMA2D_ISR_IRAM_SAFE is not set +# end of 2D-DMA Configurations + +# +# Main XTAL Config +# +CONFIG_XTAL_FREQ_40=y +CONFIG_XTAL_FREQ=40 +# end of Main XTAL Config + +# +# DCDC Regulator Configurations +# +CONFIG_ESP_SLEEP_KEEP_DCDC_ALWAYS_ON=y +CONFIG_ESP_SLEEP_DCM_VSET_VAL_IN_SLEEP=14 +# end of DCDC Regulator Configurations + +# +# LDO Regulator Configurations +# +CONFIG_ESP_LDO_RESERVE_SPI_NOR_FLASH=y +CONFIG_ESP_LDO_CHAN_SPI_NOR_FLASH_DOMAIN=1 +CONFIG_ESP_LDO_VOLTAGE_SPI_NOR_FLASH_3300_MV=y +CONFIG_ESP_LDO_VOLTAGE_SPI_NOR_FLASH_DOMAIN=3300 +CONFIG_ESP_LDO_RESERVE_PSRAM=y +CONFIG_ESP_LDO_CHAN_PSRAM_DOMAIN=2 +CONFIG_ESP_LDO_VOLTAGE_PSRAM_1900_MV=y +CONFIG_ESP_LDO_VOLTAGE_PSRAM_DOMAIN=1900 +# end of LDO Regulator Configurations + +CONFIG_ESP_SPI_BUS_LOCK_ISR_FUNCS_IN_IRAM=y +# end of Hardware Settings + +# +# ESP-Driver:LCD Controller Configurations +# +# CONFIG_LCD_ENABLE_DEBUG_LOG is not set +# CONFIG_LCD_RGB_ISR_IRAM_SAFE is not set +# CONFIG_LCD_RGB_RESTART_IN_VSYNC is not set +# CONFIG_LCD_DSI_ISR_IRAM_SAFE is not set +# end of ESP-Driver:LCD Controller Configurations + +# +# ESP-MM: Memory Management Configurations +# +# CONFIG_ESP_MM_CACHE_MSYNC_C2M_CHUNKED_OPS is not set +# end of ESP-MM: Memory Management Configurations + +# +# ESP NETIF Adapter +# +CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120 +# CONFIG_ESP_NETIF_PROVIDE_CUSTOM_IMPLEMENTATION is not set +CONFIG_ESP_NETIF_TCPIP_LWIP=y +# CONFIG_ESP_NETIF_LOOPBACK is not set +CONFIG_ESP_NETIF_USES_TCPIP_WITH_BSD_API=y +CONFIG_ESP_NETIF_REPORT_DATA_TRAFFIC=y +# CONFIG_ESP_NETIF_RECEIVE_REPORT_ERRORS is not set +# CONFIG_ESP_NETIF_L2_TAP is not set +# CONFIG_ESP_NETIF_BRIDGE_EN is not set +# CONFIG_ESP_NETIF_SET_DNS_PER_DEFAULT_NETIF is not set +# end of ESP NETIF Adapter + +# +# Partition API Configuration +# +# end of Partition API Configuration + +# +# PHY +# +# end of PHY + +# +# Power Management +# +# CONFIG_PM_ENABLE is not set +# CONFIG_PM_SLP_IRAM_OPT is not set +# CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP is not set +# end of Power Management + +# +# ESP PSRAM +# +CONFIG_SPIRAM=y + +# +# PSRAM config +# +CONFIG_SPIRAM_MODE_HEX=y +CONFIG_SPIRAM_SPEED_20M=y +CONFIG_SPIRAM_SPEED=20 +# CONFIG_SPIRAM_XIP_FROM_PSRAM is not set +# CONFIG_SPIRAM_ECC_ENABLE is not set +CONFIG_SPIRAM_BOOT_INIT=y +CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION=y +CONFIG_SPIRAM_IGNORE_NOTFOUND=y +# CONFIG_SPIRAM_USE_MEMMAP is not set +# CONFIG_SPIRAM_USE_CAPS_ALLOC is not set +CONFIG_SPIRAM_USE_MALLOC=y +CONFIG_SPIRAM_MEMTEST=y +CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=16384 +# CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is not set +CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=32768 +# CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set +# CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY is not set +# end of PSRAM config +# end of ESP PSRAM + +# +# ESP Ringbuf +# +# CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set +# end of ESP Ringbuf + +# +# ESP Security Specific +# +# end of ESP Security Specific + +# +# ESP System Settings +# +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_360=y +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=360 + +# +# Cache config +# +CONFIG_CACHE_L2_CACHE_128KB=y +# CONFIG_CACHE_L2_CACHE_256KB is not set +# CONFIG_CACHE_L2_CACHE_512KB is not set +CONFIG_CACHE_L2_CACHE_SIZE=0x20000 +CONFIG_CACHE_L2_CACHE_LINE_64B=y +# CONFIG_CACHE_L2_CACHE_LINE_128B is not set +CONFIG_CACHE_L2_CACHE_LINE_SIZE=64 +CONFIG_CACHE_L1_CACHE_LINE_SIZE=64 +# end of Cache config + +# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set +CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y +# CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set +# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set +CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=0 +CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y +CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y +# CONFIG_ESP_SYSTEM_USE_EH_FRAME is not set + +# +# Memory protection +# +CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT=y +# CONFIG_ESP_SYSTEM_PMP_LP_CORE_RESERVE_MEM_EXECUTABLE is not set +# end of Memory protection + +CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584 +CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0=y +# CONFIG_ESP_MAIN_TASK_AFFINITY_CPU1 is not set +# CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY is not set +CONFIG_ESP_MAIN_TASK_AFFINITY=0x0 +CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 +CONFIG_ESP_CONSOLE_UART_DEFAULT=y +# CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG is not set +# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set +# CONFIG_ESP_CONSOLE_NONE is not set +# CONFIG_ESP_CONSOLE_SECONDARY_NONE is not set +CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG=y +CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED=y +CONFIG_ESP_CONSOLE_UART=y +CONFIG_ESP_CONSOLE_UART_NUM=0 +CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM=0 +CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200 +# CONFIG_ESP_INT_WDT is not set +CONFIG_ESP_TASK_WDT_EN=y +# CONFIG_ESP_TASK_WDT_INIT is not set +# CONFIG_ESP_PANIC_HANDLER_IRAM is not set +# CONFIG_ESP_DEBUG_STUBS_ENABLE is not set +CONFIG_ESP_DEBUG_OCDAWARE=y +CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y + +# +# Brownout Detector +# +CONFIG_ESP_BROWNOUT_DET=y +CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set +CONFIG_ESP_BROWNOUT_DET_LVL=7 +# end of Brownout Detector + +CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y +CONFIG_ESP_SYSTEM_HW_STACK_GUARD=y +CONFIG_ESP_SYSTEM_HW_PC_RECORD=y +# end of ESP System Settings + +# +# IPC (Inter-Processor Call) +# +CONFIG_ESP_IPC_TASK_STACK_SIZE=1024 +CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y +CONFIG_ESP_IPC_ISR_ENABLE=y +# end of IPC (Inter-Processor Call) + +# +# ESP Timer (High Resolution Timer) +# +# CONFIG_ESP_TIMER_PROFILING is not set +CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y +CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y +CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584 +CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1 +# CONFIG_ESP_TIMER_SHOW_EXPERIMENTAL is not set +CONFIG_ESP_TIMER_TASK_AFFINITY=0x0 +CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0=y +CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0=y +# CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set +CONFIG_ESP_TIMER_IMPL_SYSTIMER=y +# end of ESP Timer (High Resolution Timer) + +# +# Wi-Fi +# +# CONFIG_ESP_HOST_WIFI_ENABLED is not set +# end of Wi-Fi + +# +# Core dump +# +# CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set +# CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set +CONFIG_ESP_COREDUMP_ENABLE_TO_NONE=y +# end of Core dump + +# +# FAT Filesystem support +# +CONFIG_FATFS_VOLUME_COUNT=2 +# CONFIG_FATFS_LFN_NONE is not set +CONFIG_FATFS_LFN_HEAP=y +# CONFIG_FATFS_LFN_STACK is not set +# CONFIG_FATFS_SECTOR_512 is not set +CONFIG_FATFS_SECTOR_4096=y +# CONFIG_FATFS_CODEPAGE_DYNAMIC is not set +CONFIG_FATFS_CODEPAGE_437=y +# CONFIG_FATFS_CODEPAGE_720 is not set +# CONFIG_FATFS_CODEPAGE_737 is not set +# CONFIG_FATFS_CODEPAGE_771 is not set +# CONFIG_FATFS_CODEPAGE_775 is not set +# CONFIG_FATFS_CODEPAGE_850 is not set +# CONFIG_FATFS_CODEPAGE_852 is not set +# CONFIG_FATFS_CODEPAGE_855 is not set +# CONFIG_FATFS_CODEPAGE_857 is not set +# CONFIG_FATFS_CODEPAGE_860 is not set +# CONFIG_FATFS_CODEPAGE_861 is not set +# CONFIG_FATFS_CODEPAGE_862 is not set +# CONFIG_FATFS_CODEPAGE_863 is not set +# CONFIG_FATFS_CODEPAGE_864 is not set +# CONFIG_FATFS_CODEPAGE_865 is not set +# CONFIG_FATFS_CODEPAGE_866 is not set +# CONFIG_FATFS_CODEPAGE_869 is not set +# CONFIG_FATFS_CODEPAGE_932 is not set +# CONFIG_FATFS_CODEPAGE_936 is not set +# CONFIG_FATFS_CODEPAGE_949 is not set +# CONFIG_FATFS_CODEPAGE_950 is not set +CONFIG_FATFS_CODEPAGE=437 +CONFIG_FATFS_MAX_LFN=255 +CONFIG_FATFS_API_ENCODING_ANSI_OEM=y +# CONFIG_FATFS_API_ENCODING_UTF_8 is not set +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y +# CONFIG_FATFS_USE_FASTSEEK is not set +CONFIG_FATFS_USE_STRFUNC_NONE=y +# CONFIG_FATFS_USE_STRFUNC_WITHOUT_CRLF_CONV is not set +# CONFIG_FATFS_USE_STRFUNC_WITH_CRLF_CONV is not set +CONFIG_FATFS_VFS_FSTAT_BLKSIZE=0 +# CONFIG_FATFS_IMMEDIATE_FSYNC is not set +# CONFIG_FATFS_USE_LABEL is not set +CONFIG_FATFS_LINK_LOCK=y +# CONFIG_FATFS_USE_DYN_BUFFERS is not set + +# +# File system free space calculation behavior +# +CONFIG_FATFS_DONT_TRUST_FREE_CLUSTER_CNT=0 +CONFIG_FATFS_DONT_TRUST_LAST_ALLOC=0 +# end of File system free space calculation behavior +# end of FAT Filesystem support + +# +# FreeRTOS +# + +# +# Kernel +# +# CONFIG_FREERTOS_UNICORE is not set +CONFIG_FREERTOS_HZ=100 +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=3 +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1024 +# CONFIG_FREERTOS_USE_IDLE_HOOK is not set +# CONFIG_FREERTOS_USE_TICK_HOOK is not set +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +# CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY is not set +CONFIG_FREERTOS_USE_TIMERS=y +CONFIG_FREERTOS_TIMER_SERVICE_TASK_NAME="Tmr Svc" +# CONFIG_FREERTOS_TIMER_TASK_AFFINITY_CPU0 is not set +# CONFIG_FREERTOS_TIMER_TASK_AFFINITY_CPU1 is not set +CONFIG_FREERTOS_TIMER_TASK_NO_AFFINITY=y +CONFIG_FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1 +CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES=1 +CONFIG_FREERTOS_USE_TRACE_FACILITY=y +# CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS is not set +# CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES is not set +# CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set +# CONFIG_FREERTOS_USE_APPLICATION_TASK_TAG is not set +# end of Kernel + +# +# Port +# +# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set +CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS=y +# CONFIG_FREERTOS_TASK_PRE_DELETION_HOOK is not set +# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set +CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y +CONFIG_FREERTOS_ISR_STACKSIZE=1536 +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y +CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y +# CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 is not set +CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER=y +CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH=y +# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set +# end of Port + +# +# Extra +# +CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y +# end of Extra + +CONFIG_FREERTOS_PORT=y +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y +CONFIG_FREERTOS_DEBUG_OCDAWARE=y +CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y +CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH=y +CONFIG_FREERTOS_NUMBER_OF_CORES=2 +# end of FreeRTOS + +# +# Hardware Abstraction Layer (HAL) and Low Level (LL) +# +CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y +# CONFIG_HAL_ASSERTION_DISABLE is not set +CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=0 +CONFIG_HAL_SYSTIMER_USE_ROM_IMPL=y +CONFIG_HAL_WDT_USE_ROM_IMPL=y +CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y +# end of Hardware Abstraction Layer (HAL) and Low Level (LL) + +# +# Heap memory debugging +# +CONFIG_CMPCT_MALLOC_HEAP=y +CONFIG_HEAP_POISONING_DISABLED=y +# CONFIG_HEAP_POISONING_LIGHT is not set +# CONFIG_HEAP_POISONING_COMPREHENSIVE is not set +CONFIG_HEAP_TRACING_OFF=y +# CONFIG_HEAP_TRACING_STANDALONE is not set +# CONFIG_HEAP_TRACING_TOHOST is not set +# CONFIG_HEAP_USE_HOOKS is not set +# CONFIG_HEAP_TASK_TRACKING is not set +# CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set +# CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH is not set +# end of Heap memory debugging + +# +# Log +# + +# +# Log Level +# +# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set +CONFIG_LOG_DEFAULT_LEVEL_ERROR=y +# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set +# CONFIG_LOG_DEFAULT_LEVEL_INFO is not set +# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set +CONFIG_LOG_DEFAULT_LEVEL=1 +CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT=y +# CONFIG_LOG_MAXIMUM_LEVEL_WARN is not set +# CONFIG_LOG_MAXIMUM_LEVEL_INFO is not set +# CONFIG_LOG_MAXIMUM_LEVEL_DEBUG is not set +# CONFIG_LOG_MAXIMUM_LEVEL_VERBOSE is not set +CONFIG_LOG_MAXIMUM_LEVEL=1 + +# +# Level Settings +# +# CONFIG_LOG_MASTER_LEVEL is not set +CONFIG_LOG_DYNAMIC_LEVEL_CONTROL=y +# CONFIG_LOG_TAG_LEVEL_IMPL_NONE is not set +# CONFIG_LOG_TAG_LEVEL_IMPL_LINKED_LIST is not set +CONFIG_LOG_TAG_LEVEL_IMPL_CACHE_AND_LINKED_LIST=y +# CONFIG_LOG_TAG_LEVEL_CACHE_ARRAY is not set +CONFIG_LOG_TAG_LEVEL_CACHE_BINARY_MIN_HEAP=y +CONFIG_LOG_TAG_LEVEL_IMPL_CACHE_SIZE=31 +# end of Level Settings +# end of Log Level + +# +# Format +# +# CONFIG_LOG_COLORS is not set +CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y +# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set +# end of Format +# end of Log + +# +# LWIP +# +CONFIG_LWIP_ENABLE=y +CONFIG_LWIP_LOCAL_HOSTNAME="toit" +# CONFIG_LWIP_NETIF_API is not set +CONFIG_LWIP_TCPIP_TASK_PRIO=18 +# CONFIG_LWIP_TCPIP_CORE_LOCKING is not set +# CONFIG_LWIP_CHECK_THREAD_SAFETY is not set +# CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES is not set +# CONFIG_LWIP_L2_TO_L3_COPY is not set +# CONFIG_LWIP_IRAM_OPTIMIZATION is not set +# CONFIG_LWIP_EXTRA_IRAM_OPTIMIZATION is not set +CONFIG_LWIP_TIMERS_ONDEMAND=y +CONFIG_LWIP_ND6=y +# CONFIG_LWIP_FORCE_ROUTER_FORWARDING is not set +CONFIG_LWIP_MAX_SOCKETS=10 +# CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set +# CONFIG_LWIP_SO_LINGER is not set +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +# CONFIG_LWIP_SO_RCVBUF is not set +# CONFIG_LWIP_NETBUF_RECVINFO is not set +CONFIG_LWIP_IP_DEFAULT_TTL=64 +CONFIG_LWIP_IP4_FRAG=y +CONFIG_LWIP_IP6_FRAG=y +# CONFIG_LWIP_IP4_REASSEMBLY is not set +# CONFIG_LWIP_IP6_REASSEMBLY is not set +CONFIG_LWIP_IP_REASS_MAX_PBUFS=10 +# CONFIG_LWIP_IP_FORWARD is not set +# CONFIG_LWIP_STATS is not set +CONFIG_LWIP_ESP_GRATUITOUS_ARP=y +CONFIG_LWIP_GARP_TMR_INTERVAL=60 +CONFIG_LWIP_ESP_MLDV6_REPORT=y +CONFIG_LWIP_MLDV6_TMR_INTERVAL=40 +CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +# CONFIG_LWIP_DHCP_DOES_ACD_CHECK is not set +# CONFIG_LWIP_DHCP_DOES_NOT_CHECK_OFFERED_IP is not set +# CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set +CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y +# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set +CONFIG_LWIP_DHCP_OPTIONS_LEN=68 +CONFIG_LWIP_NUM_NETIF_CLIENT_DATA=0 +CONFIG_LWIP_DHCP_COARSE_TIMER_SECS=1 + +# +# DHCP server +# +CONFIG_LWIP_DHCPS=y +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +CONFIG_LWIP_DHCPS_STATIC_ENTRIES=y +CONFIG_LWIP_DHCPS_ADD_DNS=y +# end of DHCP server + +# CONFIG_LWIP_AUTOIP is not set +CONFIG_LWIP_IPV4=y +CONFIG_LWIP_IPV6=y +# CONFIG_LWIP_IPV6_AUTOCONFIG is not set +CONFIG_LWIP_IPV6_NUM_ADDRESSES=3 +# CONFIG_LWIP_IPV6_FORWARD is not set +# CONFIG_LWIP_NETIF_STATUS_CALLBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=16 +CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION=y +CONFIG_LWIP_TCP_MAXRTX=12 +CONFIG_LWIP_TCP_SYNMAXRTX=6 +CONFIG_LWIP_TCP_MSS=1440 +CONFIG_LWIP_TCP_TMR_INTERVAL=250 +CONFIG_LWIP_TCP_MSL=60000 +CONFIG_LWIP_TCP_FIN_WAIT_TIMEOUT=20000 +CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5760 +CONFIG_LWIP_TCP_WND_DEFAULT=5760 +CONFIG_LWIP_TCP_RECVMBOX_SIZE=6 +CONFIG_LWIP_TCP_ACCEPTMBOX_SIZE=6 +CONFIG_LWIP_TCP_QUEUE_OOSEQ=y +CONFIG_LWIP_TCP_OOSEQ_TIMEOUT=6 +CONFIG_LWIP_TCP_OOSEQ_MAX_PBUFS=4 +# CONFIG_LWIP_TCP_SACK_OUT is not set +CONFIG_LWIP_TCP_OVERSIZE_MSS=y +# CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set +CONFIG_LWIP_TCP_RTO_TIME=1500 +# end of TCP + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_LWIP_UDP_RECVMBOX_SIZE=6 +# end of UDP + +# +# Checksums +# +# CONFIG_LWIP_CHECKSUM_CHECK_IP is not set +# CONFIG_LWIP_CHECKSUM_CHECK_UDP is not set +CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y +# end of Checksums + +CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU1 is not set +CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF +CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3 +CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5 +CONFIG_LWIP_IPV6_ND6_NUM_PREFIXES=5 +CONFIG_LWIP_IPV6_ND6_NUM_ROUTERS=3 +CONFIG_LWIP_IPV6_ND6_NUM_DESTINATIONS=10 +# CONFIG_LWIP_PPP_SUPPORT is not set +# CONFIG_LWIP_SLIP_SUPPORT is not set + +# +# ICMP +# +CONFIG_LWIP_ICMP=y +# CONFIG_LWIP_MULTICAST_PING is not set +# CONFIG_LWIP_BROADCAST_PING is not set +# end of ICMP + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 +# end of LWIP RAW API + +# +# SNTP +# +CONFIG_LWIP_SNTP_MAX_SERVERS=1 +# CONFIG_LWIP_DHCP_GET_NTP_SRV is not set +CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 +CONFIG_LWIP_SNTP_STARTUP_DELAY=y +CONFIG_LWIP_SNTP_MAXIMUM_STARTUP_DELAY=5000 +# end of SNTP + +# +# DNS +# +CONFIG_LWIP_DNS_MAX_HOST_IP=1 +CONFIG_LWIP_DNS_MAX_SERVERS=3 +# CONFIG_LWIP_FALLBACK_DNS_SERVER_SUPPORT is not set +# CONFIG_LWIP_DNS_SETSERVER_WITH_NETIF is not set +# end of DNS + +CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7 + +# +# Hooks +# +# CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set +CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y +# CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_ROUTE_NONE=y +# CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_ROUTE_CUSTOM is not set +CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y +# CONFIG_LWIP_HOOK_ND6_GET_GW_DEFAULT is not set +# CONFIG_LWIP_HOOK_ND6_GET_GW_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_NONE=y +# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_CUSTOM is not set +CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set +CONFIG_LWIP_HOOK_DNS_EXT_RESOLVE_NONE=y +# CONFIG_LWIP_HOOK_DNS_EXT_RESOLVE_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_INPUT_NONE=y +# CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM is not set +# end of Hooks + +# CONFIG_LWIP_DEBUG is not set +# end of LWIP + +# +# mbedTLS +# +CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +# CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC is not set +# CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set +# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y +CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=7800 +CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=3700 +# CONFIG_MBEDTLS_DYNAMIC_BUFFER is not set +# CONFIG_MBEDTLS_DEBUG is not set + +# +# mbedTLS v3.x related +# +# CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 is not set +# CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set +CONFIG_MBEDTLS_ECDH_LEGACY_CONTEXT=y +CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK=y +# CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set +CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y +CONFIG_MBEDTLS_PKCS7_C=y +# end of mbedTLS v3.x related + +# +# Certificate Bundle +# +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=y +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=y +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_NONE is not set +# CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEPRECATED_LIST is not set +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS=200 +# end of Certificate Bundle + +CONFIG_MBEDTLS_ECP_RESTARTABLE=y +CONFIG_MBEDTLS_CMAC_C=y +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_AES_USE_INTERRUPT=y +CONFIG_MBEDTLS_AES_INTERRUPT_LEVEL=0 +CONFIG_MBEDTLS_HARDWARE_GCM=y +CONFIG_MBEDTLS_GCM_SUPPORT_NON_AES_CIPHER=y +# CONFIG_MBEDTLS_HARDWARE_MPI is not set +CONFIG_MBEDTLS_HARDWARE_SHA=y +CONFIG_MBEDTLS_HARDWARE_ECC=y +CONFIG_MBEDTLS_ECC_OTHER_CURVES_SOFT_FALLBACK=y +CONFIG_MBEDTLS_ROM_MD5=y +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set +CONFIG_MBEDTLS_HAVE_TIME=y +# CONFIG_MBEDTLS_PLATFORM_TIME_ALT is not set +# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set +CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y +CONFIG_MBEDTLS_SHA1_C=y +CONFIG_MBEDTLS_SHA512_C=y +# CONFIG_MBEDTLS_SHA3_C is not set +# CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT is not set +# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set +CONFIG_MBEDTLS_TLS_CLIENT_ONLY=y +# CONFIG_MBEDTLS_TLS_DISABLED is not set +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +# CONFIG_MBEDTLS_PSK_MODES is not set +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +# end of TLS Key Exchange Methods + +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +# CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set +# CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set +CONFIG_MBEDTLS_SSL_ALPN=y +CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y +CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +# CONFIG_MBEDTLS_CAMELLIA_C is not set +# CONFIG_MBEDTLS_DES_C is not set +# CONFIG_MBEDTLS_BLOWFISH_C is not set +# CONFIG_MBEDTLS_XTEA_C is not set +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +# CONFIG_MBEDTLS_NIST_KW_C is not set +# end of Symmetric Ciphers + +# CONFIG_MBEDTLS_RIPEMD160_C is not set + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +CONFIG_MBEDTLS_PEM_WRITE_C=y +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +# end of Certificates + +CONFIG_MBEDTLS_ECP_C=y +CONFIG_MBEDTLS_PK_PARSE_EC_EXTENDED=y +CONFIG_MBEDTLS_PK_PARSE_EC_COMPRESSED=y +# CONFIG_MBEDTLS_DHM_C is not set +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +# CONFIG_MBEDTLS_ECJPAKE_C is not set +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y +CONFIG_MBEDTLS_ECP_FIXED_POINT_OPTIM=y +CONFIG_MBEDTLS_POLY1305_C=y +CONFIG_MBEDTLS_CHACHA20_C=y +CONFIG_MBEDTLS_CHACHAPOLY_C=y +# CONFIG_MBEDTLS_HKDF_C is not set +# CONFIG_MBEDTLS_THREADING_C is not set +CONFIG_MBEDTLS_ERROR_STRINGS=y +CONFIG_MBEDTLS_FS_IO=y +# CONFIG_MBEDTLS_ALLOW_WEAK_CERTIFICATE_VERIFICATION is not set +# end of mbedTLS + +# +# ESP-MQTT Configurations +# +# CONFIG_MQTT_PROTOCOL_311 is not set +# CONFIG_MQTT_PROTOCOL_5 is not set +# CONFIG_MQTT_TRANSPORT_SSL is not set +# CONFIG_MQTT_MSG_ID_INCREMENTAL is not set +# CONFIG_MQTT_SKIP_PUBLISH_IF_DISCONNECTED is not set +# CONFIG_MQTT_REPORT_DELETED_MESSAGES is not set +# CONFIG_MQTT_USE_CUSTOM_CONFIG is not set +# CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set +# CONFIG_MQTT_CUSTOM_OUTBOX is not set +# end of ESP-MQTT Configurations + +# +# Newlib +# +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +# CONFIG_NEWLIB_NANO_FORMAT is not set +CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y +# CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set +# CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set +# CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set +# end of Newlib + +# +# NVS +# +# CONFIG_NVS_ENCRYPTION is not set +# CONFIG_NVS_ASSERT_ERROR_CHECK is not set +# CONFIG_NVS_LEGACY_DUP_KEYS_COMPATIBILITY is not set +# CONFIG_NVS_ALLOCATE_CACHE_IN_SPIRAM is not set +# end of NVS + +# +# OpenThread +# +# CONFIG_OPENTHREAD_ENABLED is not set + +# +# OpenThread Spinel +# +# CONFIG_OPENTHREAD_SPINEL_ONLY is not set +# end of OpenThread Spinel +# end of OpenThread + +# +# Protocomm +# +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0=y +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1=y +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2=y +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_PATCH_VERSION=y +# end of Protocomm + +# +# PThreads +# +CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_PTHREAD_DEFAULT_CORE_NO_AFFINITY=y +# CONFIG_PTHREAD_DEFAULT_CORE_0 is not set +# CONFIG_PTHREAD_DEFAULT_CORE_1 is not set +CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread" +# end of PThreads + +# +# MMU Config +# +CONFIG_MMU_PAGE_SIZE_64KB=y +CONFIG_MMU_PAGE_MODE="64KB" +CONFIG_MMU_PAGE_SIZE=0x10000 +# end of MMU Config + +# +# Main Flash configuration +# + +# +# SPI Flash behavior when brownout +# +CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC=y +CONFIG_SPI_FLASH_BROWNOUT_RESET=y +# end of SPI Flash behavior when brownout + +# +# Optional and Experimental Features (READ DOCS FIRST) +# + +# +# Features here require specific hardware (READ DOCS FIRST!) +# +# CONFIG_SPI_FLASH_AUTO_SUSPEND is not set +CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US=50 +# CONFIG_SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND is not set +# CONFIG_SPI_FLASH_FORCE_ENABLE_C6_H2_SUSPEND is not set +# end of Optional and Experimental Features (READ DOCS FIRST) +# end of Main Flash configuration + +# +# SPI Flash driver +# +CONFIG_SPI_FLASH_VERIFY_WRITE=y +CONFIG_SPI_FLASH_LOG_FAILED_WRITE=y +CONFIG_SPI_FLASH_WARN_SETTING_ZERO_TO_ONE=y +# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y +CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set +# CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set +CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y +CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 +CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 +CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 +# CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set +# CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set +# CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set + +# +# Auto-detect flash chips +# +CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED=y +# CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP is not set +# CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP is not set +# CONFIG_SPI_FLASH_SUPPORT_GD_CHIP is not set +# CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP is not set +# CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP is not set +# CONFIG_SPI_FLASH_SUPPORT_TH_CHIP is not set +# end of Auto-detect flash chips + +CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y +# end of SPI Flash driver + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +# CONFIG_SPIFFS_CACHE_STATS is not set +# end of SPIFFS Cache Configuration + +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +# CONFIG_SPIFFS_GC_STATS is not set +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +# CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +# CONFIG_SPIFFS_DBG is not set +# CONFIG_SPIFFS_API_DBG is not set +# CONFIG_SPIFFS_GC_DBG is not set +# CONFIG_SPIFFS_CACHE_DBG is not set +# CONFIG_SPIFFS_CHECK_DBG is not set +# CONFIG_SPIFFS_TEST_VISUALISATION is not set +# end of Debug Configuration +# end of SPIFFS Configuration + +# +# TCP Transport +# + +# +# Websocket +# +# CONFIG_WS_TRANSPORT is not set +# end of Websocket +# end of TCP Transport + +# +# Ultra Low Power (ULP) Co-processor +# +# CONFIG_ULP_COPROC_ENABLED is not set + +# +# ULP Debugging Options +# +# end of ULP Debugging Options +# end of Ultra Low Power (ULP) Co-processor + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +# CONFIG_UNITY_ENABLE_64BIT is not set +# CONFIG_UNITY_ENABLE_COLOR is not set +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +# CONFIG_UNITY_ENABLE_FIXTURE is not set +# CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set +# end of Unity unit testing library + +# +# USB-OTG +# +CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE=256 +CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED=y +# CONFIG_USB_HOST_HW_BUFFER_BIAS_IN is not set +# CONFIG_USB_HOST_HW_BUFFER_BIAS_PERIODIC_OUT is not set + +# +# Hub Driver Configuration +# + +# +# Root Port configuration +# +CONFIG_USB_HOST_DEBOUNCE_DELAY_MS=250 +CONFIG_USB_HOST_RESET_HOLD_MS=30 +CONFIG_USB_HOST_RESET_RECOVERY_MS=30 +CONFIG_USB_HOST_SET_ADDR_RECOVERY_MS=10 +# end of Root Port configuration + +# CONFIG_USB_HOST_HUBS_SUPPORTED is not set +# end of Hub Driver Configuration + +# CONFIG_USB_HOST_ENABLE_ENUM_FILTER_CALLBACK is not set +# CONFIG_USB_HOST_DWC_DMA_CAP_MEMORY_IN_PSRAM is not set +CONFIG_USB_OTG_SUPPORTED=y +# end of USB-OTG + +# +# Virtual file system +# +CONFIG_VFS_SUPPORT_IO=y +CONFIG_VFS_SUPPORT_DIR=y +CONFIG_VFS_SUPPORT_SELECT=y +CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_VFS_SELECT_IN_RAM=y +CONFIG_VFS_SUPPORT_TERMIOS=y +CONFIG_VFS_MAX_COUNT=8 + +# +# Host File System I/O (Semihosting) +# +CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +# end of Host File System I/O (Semihosting) + +CONFIG_VFS_INITIALIZE_DEV_NULL=y +# end of Virtual file system + +# +# Wear Levelling +# +# CONFIG_WL_SECTOR_SIZE_512 is not set +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 +# end of Wear Levelling + +# +# Wi-Fi Provisioning Manager +# +CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 +CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 +CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y +# CONFIG_WIFI_PROV_STA_FAST_SCAN is not set +# end of Wi-Fi Provisioning Manager + +# +# Toit +# +CONFIG_TOIT_WIFI_SSID="" +CONFIG_TOIT_WIFI_PASSWORD="" +CONFIG_TOIT_ENTRY_POINT="" +CONFIG_TOIT_ENTRY_POINT_PROJECT_ROOT="" +CONFIG_TOIT_ENTRY_POINT_ASSETS_FILE="" +CONFIG_TOIT_BYTE_DISPLAY=y +CONFIG_TOIT_BIT_DISPLAY=y +CONFIG_TOIT_FONT=y +CONFIG_TOIT_FATFS=y +CONFIG_TOIT_ZLIB_RLE=y +# CONFIG_TOIT_FULL_ZLIB is not set +CONFIG_TOIT_REPORT_UART_DATA_LOSS=y +CONFIG_TOIT_REPORT_I2S_DATA_LOSS=y + +# +# Advanced setup +# +CONFIG_TOIT_INTERPRETER_IN_IRAM=y +CONFIG_TOIT_INTERPRETER_HELPERS_IN_IRAM=y +CONFIG_TOIT_CRYPTO=y +# CONFIG_TOIT_CRYPTO_EXTRA is not set +CONFIG_TOIT_ENABLE_IP=y +CONFIG_TOIT_ENABLE_ETHERNET=y +CONFIG_TOIT_ENABLE_WIFI=y +CONFIG_TOIT_ENABLE_ESPNOW=y +CONFIG_TOIT_SPIRAM_HEAP=y +CONFIG_TOIT_SYSTEM_SOURCE="system/extensions/esp32/boot.toit" +CONFIG_TOIT_SYSTEM_SOURCE_PROJECT_ROOT="system" +CONFIG_RODATA_PADDING=2097152 +# end of Advanced setup +# end of Toit +# end of Component config + +# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set + +# Deprecated options for backward compatibility +# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set +# CONFIG_NO_BLOBS is not set +CONFIG_LOG_BOOTLOADER_LEVEL_NONE=y +# CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_INFO is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set +CONFIG_LOG_BOOTLOADER_LEVEL=0 +CONFIG_APP_ROLLBACK_ENABLE=y +# CONFIG_APP_ANTI_ROLLBACK is not set +# CONFIG_FLASH_ENCRYPTION_ENABLED is not set +# CONFIG_FLASHMODE_QIO is not set +# CONFIG_FLASHMODE_QOUT is not set +CONFIG_FLASHMODE_DIO=y +# CONFIG_FLASHMODE_DOUT is not set +CONFIG_MONITOR_BAUD=115200 +# CONFIG_OPTIMIZATION_LEVEL_DEBUG is not set +# CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG is not set +# CONFIG_COMPILER_OPTIMIZATION_DEFAULT is not set +CONFIG_OPTIMIZATION_LEVEL_RELEASE=y +CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE=y +# CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED is not set +# CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set +CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED=y +CONFIG_OPTIMIZATION_ASSERTION_LEVEL=0 +# CONFIG_CXX_EXCEPTIONS is not set +CONFIG_STACK_CHECK_NONE=y +# CONFIG_STACK_CHECK_NORM is not set +# CONFIG_STACK_CHECK_STRONG is not set +# CONFIG_STACK_CHECK_ALL is not set +# CONFIG_WARN_WRITE_STRINGS is not set +# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set +CONFIG_ESP32_APPTRACE_DEST_NONE=y +CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y +# CONFIG_CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE is not set +# CONFIG_CAM_CTLR_ISP_DVP_ISR_IRAM_SAFE is not set +# CONFIG_CAM_CTLR_DVP_CAM_ISR_IRAM_SAFE is not set +# CONFIG_MCPWM_ISR_IN_IRAM is not set +# CONFIG_EVENT_LOOP_PROFILING is not set +CONFIG_POST_EVENTS_FROM_ISR=y +CONFIG_POST_EVENTS_FROM_IRAM_ISR=y +CONFIG_GDBSTUB_SUPPORT_TASKS=y +CONFIG_GDBSTUB_MAX_TASKS=32 +# CONFIG_OTA_ALLOW_HTTP is not set +CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_MAIN_TASK_STACK_SIZE=3584 +CONFIG_CONSOLE_UART_DEFAULT=y +# CONFIG_CONSOLE_UART_CUSTOM is not set +# CONFIG_CONSOLE_UART_NONE is not set +# CONFIG_ESP_CONSOLE_UART_NONE is not set +CONFIG_CONSOLE_UART=y +CONFIG_CONSOLE_UART_NUM=0 +CONFIG_CONSOLE_UART_BAUDRATE=115200 +# CONFIG_INT_WDT is not set +# CONFIG_TASK_WDT is not set +# CONFIG_ESP_TASK_WDT is not set +# CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set +CONFIG_BROWNOUT_DET=y +CONFIG_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set +CONFIG_BROWNOUT_DET_LVL=7 +CONFIG_IPC_TASK_STACK_SIZE=1024 +CONFIG_TIMER_TASK_STACK_SIZE=3584 +# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set +# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set +CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y +CONFIG_TIMER_TASK_PRIORITY=1 +CONFIG_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_TIMER_QUEUE_LENGTH=10 +# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set +CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +# CONFIG_L2_TO_L3_COPY is not set +CONFIG_ESP_GRATUITOUS_ARP=y +CONFIG_GARP_TMR_INTERVAL=60 +CONFIG_TCPIP_RECVMBOX_SIZE=32 +CONFIG_TCP_MAXRTX=12 +CONFIG_TCP_SYNMAXRTX=6 +CONFIG_TCP_MSS=1440 +CONFIG_TCP_MSL=60000 +CONFIG_TCP_SND_BUF_DEFAULT=5760 +CONFIG_TCP_WND_DEFAULT=5760 +CONFIG_TCP_RECVMBOX_SIZE=6 +CONFIG_TCP_QUEUE_OOSEQ=y +CONFIG_TCP_OVERSIZE_MSS=y +# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_TCP_OVERSIZE_DISABLE is not set +CONFIG_UDP_RECVMBOX_SIZE=6 +CONFIG_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set +# CONFIG_TCPIP_TASK_AFFINITY_CPU1 is not set +CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_PPP_SUPPORT is not set +CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_ESP32_PTHREAD_STACK_MIN=768 +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y +# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0 is not set +# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1 is not set +CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set +CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_SUPPORT_TERMIOS=y +CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +# End of deprecated options diff --git a/toolchains/esp32p4/sdkconfig.defaults b/toolchains/esp32p4/sdkconfig.defaults new file mode 100644 index 000000000..f222a65bd --- /dev/null +++ b/toolchains/esp32p4/sdkconfig.defaults @@ -0,0 +1,50 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) 5.4.2 Project Minimal Configuration +# +CONFIG_IDF_TARGET="esp32p4" +CONFIG_BOOTLOADER_LOG_LEVEL_NONE=y +CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE=y +CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP=y +CONFIG_APP_COMPILE_TIME_DATE=n +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_COMPILER_OPTIMIZATION_SIZE=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE=y +CONFIG_COMPILER_ORPHAN_SECTIONS_PLACE=y +CONFIG_I2S_ISR_IRAM_SAFE=y +CONFIG_SPI_SLAVE_ISR_IN_IRAM=n +CONFIG_UART_ISR_IN_IRAM=y +CONFIG_ETH_SPI_ETHERNET_DM9051=y +CONFIG_ETH_SPI_ETHERNET_W5500=y +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=n +CONFIG_SPIRAM=y +CONFIG_SPIRAM_IGNORE_NOTFOUND=y +CONFIG_ESP_INT_WDT=n +CONFIG_ESP_TASK_WDT_INIT=n +CONFIG_FATFS_LFN_HEAP=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=3 +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1024 +CONFIG_FREERTOS_USE_TRACE_FACILITY=y +CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH=y +CONFIG_LOG_DEFAULT_LEVEL_ERROR=y +CONFIG_LWIP_LOCAL_HOSTNAME="toit" +CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=n +CONFIG_LWIP_TCP_SYNMAXRTX=6 +CONFIG_LWIP_HOOK_IP6_INPUT_NONE=y +CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=7800 +CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=3700 +CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK=y +CONFIG_MBEDTLS_ECP_RESTARTABLE=y +CONFIG_MBEDTLS_CMAC_C=y +CONFIG_MBEDTLS_HARDWARE_MPI=n +CONFIG_MBEDTLS_TLS_CLIENT_ONLY=y +CONFIG_MBEDTLS_ECP_FIXED_POINT_OPTIM=y +CONFIG_MBEDTLS_POLY1305_C=y +CONFIG_MBEDTLS_CHACHA20_C=y +CONFIG_MBEDTLS_CHACHAPOLY_C=y +CONFIG_MQTT_PROTOCOL_311=n +CONFIG_MQTT_TRANSPORT_SSL=n +CONFIG_SPI_FLASH_VERIFY_WRITE=y +CONFIG_SPI_FLASH_LOG_FAILED_WRITE=y +CONFIG_SPI_FLASH_WARN_SETTING_ZERO_TO_ONE=y +CONFIG_WS_TRANSPORT=n diff --git a/tools/firmware.toit b/tools/firmware.toit index a14925f83..abe5aef97 100644 --- a/tools/firmware.toit +++ b/tools/firmware.toit @@ -1060,7 +1060,7 @@ flash-cmd -> cli.Command: --required, cli.OptionInt "baud" --default=921600, - cli.OptionEnum "chip" ["esp32", "esp32c3", "esp32c6", "esp32s2", "esp32s3"] + cli.OptionEnum "chip" ["esp32", "esp32c3", "esp32c6", "esp32p4", "esp32s2", "esp32s3"] --hidden --help="Deprecated. Don't use this option.", cli.OptionPatterns "partition" @@ -1697,13 +1697,17 @@ class Esp32C6AddressMap implements AddressMap: drom-map-start ::= 0x42000000 drom-map-end ::= 0x43000000 +class Esp32P4AddressMap implements AddressMap: + drom-map-start ::= 0x40000000 + drom-map-end ::= 0x44000000 + class Esp32S2AddressMap implements AddressMap: drom-map-start ::= 0x3f000000 drom-map-end ::= 0x3ff80000 class Esp32S3AddressMap implements AddressMap: drom-map-start ::= 0x3c000000 - drom-map-end ::= 0x3d000000 + drom-map-end ::= 0x3e000000 class Esp32Binary: static MAGIC-OFFSET_ ::= 0 @@ -1720,6 +1724,7 @@ class Esp32Binary: static ESP-CHIP-ID-ESP32-C3 ::= 0x0005 // Chip ID: ESP32-C3. static ESP-CHIP-ID-ESP32-C6 ::= 0x000d // Chip ID: ESP32-C6. static ESP-CHIP-ID-ESP32-H2 ::= 0x000a // Chip ID: ESP32-H2. + static ESP-CHIP-ID-ESP32-P4 ::= 0x0012 // Chip ID: ESP32-P4. static ESP-CHIP-ID-ESP32-S2 ::= 0x0002 // Chip ID: ESP32-S2. static ESP-CHIP-ID-ESP32-S3 ::= 0x0009 // Chip ID: ESP32-S3. @@ -1727,6 +1732,7 @@ class Esp32Binary: ESP-CHIP-ID-ESP32 : Esp32AddressMap, ESP-CHIP-ID-ESP32-C3 : Esp32C3AddressMap, ESP-CHIP-ID-ESP32-C6 : Esp32C6AddressMap, + ESP-CHIP-ID-ESP32-P4 : Esp32P4AddressMap, ESP-CHIP-ID-ESP32-S2 : Esp32S2AddressMap, ESP-CHIP-ID-ESP32-S3 : Esp32S3AddressMap, } @@ -1736,6 +1742,7 @@ class Esp32Binary: ESP-CHIP-ID-ESP32-C3 : "esp32c3", ESP-CHIP-ID-ESP32-C6 : "esp32c6", ESP-CHIP-ID-ESP32-H2 : "esp32h2", + ESP-CHIP-ID-ESP32-P4 : "esp32p4", ESP-CHIP-ID-ESP32-S2 : "esp32s2", ESP-CHIP-ID-ESP32-S3 : "esp32s3", }