Fix read/write signal generation via U37

[tomstorey]

The input to U37's E pin should probably be the output of an AND gate whos inputs are the UDS/LDS signals, such that (and perhaps most specifically) write is only strobed to a peripheral once one of the xDS signals is asserted.

[tomstorey]

Things to keep in mind .. UDS is used to generate XA0, so chip selects for write cycles are delayed until one of the xDS signals is asserted.