Commit 0976199
Read the deferred high tile-data byte on the fetch's own schedule
When the push has to wait (occupied FIFO, or an object fetch pausing
the pipeline), the hardware background fetch still reads its high data
byte two dots after the low one - the wait defers only the push, not
the read. We read the high byte at the actual push tick, so register
writes landing during the wait (an LCDC.4 toggle around a sprite fetch,
an SCY write) leaked into data the hardware fetch had already read.
Diagnosed with wall-clock-aligned read traces against an instrumented
SameBoy on m3_lcdc_tile_sel_change line 100: the object fetch at x=8
interposed between our low and high byte reads, so the LCDC.4 pulse hit
our high byte one fetch early; hardware completes both reads before the
object fetch and catches the pulse on the *next* fetch's low byte
instead. With a free FIFO the push and the read still share the
HIGH_T2 tick, so the calibrated normal-flow timing is unchanged.
m3_lcdc_tile_sel_change 534 -> 0 (pixel-perfect), m3_scy_change
464 -> 152, m3_lcdc_tile_sel_win_change 478 -> 192. Mealybug DMG total
2684 -> 1552, 11 of 24 tests pixel-perfect. Full battery green
(mooneye 98, blargg, dmg-acid2, unit).
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01J1wLWscyUGS7CFwc3CjJR81 parent 2ace103 commit 0976199
2 files changed
Lines changed: 35 additions & 7 deletions
File tree
- core/src
- main/java/eu/rekawek/coffeegb/core/gpu
- test/java/eu/rekawek/coffeegb/core/integration/mealybug
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