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KanuaKKanuaK
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[compiler](docs) modify docs for compile options cleanup (#1902)
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‎docs/en/architecture_design_and_core_features.md‎

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@@ -70,24 +70,30 @@ This project extends the support for Huawei Ascend NPU (using the CANN software
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|No.| NPU Option | Hardware Platform | Description|
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| --- | --------------------------------------------- | ---------- | ----- |
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| 1 | multibuffer | NPU | Autotune option. It enables or disables the ping-pong pipeline. Enabled by default.|
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| 2 | enable_auto_bind_sub_block | NPU | Autotune option (CV-fused kernels only). It enables or disables auto-binding of sub-blocks.|
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| 3 | enable_hivm_auto_cv_balance | NPU | Autotune option (CV-fused kernels only). It enables or disables automatic CV balancing.|
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| 4 | sync_solver | NPU | Autotune option (CV-fused kernels only). It enables or disables the synchronization solver. |
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| 5 | unit_flag | NPU | Autotune option. It enables or disables the sync unit flag.|
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| 6 | inject_barrier_all | NPU | Autotune option. It enables or disables automatic injection of barriers for all operations.|
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| 7 | inject_block_all | NPU | Autotune option. It enables or disables automatic injection of blocks for all operations.|
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| 8 | limit_auto_multi_buffer_only_for_local_buffer | NPU | Autotune option. It restricts automatic multi-buffering only to local buffers.|
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| 9 | limit_auto_multi_buffer_of_local_buffer | NPU | Autotune option. It enables or disables automatic multi-buffering for local buffers.|
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| 10 | set_workspace_multibuffer | NPU | Autotune option. It enables or disables multi-buffering for the workspace.|
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| 11 | tile_mix_vector_loop | NPU | Autotune option (CV-fused kernels only). It enables or disables tiling for vector loops.|
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| 12 | tile_mix_cube_loop | NPU | Autotune option (CV-fused kernels only). It enables or disables tiling for cube loops.|
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| 13 | disable_auto_inject_block_sync | NPU | Autotune option (CV-fused kernels only). It enables or disables automatic injection of block synchronizations.|
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| 14 | stream | NPU | (Optional) Informs the compiler about the NPU stream to use.|
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| 15 | enable_linearize | NPU | Autotune option. It enables or disables the linearization pass.|
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| 16 | enable_nd2nz_on_vector | NPU | Autotune option (CV-fused kernels only). It enables or disables the ND (n-dimensional) to NZ (non-zero) layout transformation.|
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| 17 | auto_blockify_size | NPU | Autotune option. It enables or disables AutoBlockify pass. It is ignored when TRITON_ALL_BLOCKS_PARALLEL is not set |
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| 18 | compile_mode | NPU (950) | Compilation mode: `"unstructured_in_simt"` (default) / `"simd"` / `"simt_only"`. |
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| 1 | multibuffer | NPU | Enables or disables the ping-pong pipeline. Enabled by default.|
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| 2 | enable_graph_optimize | NPU | Enables or disables TTIR Graph Optimization.|
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| 3 | bisheng_options | NPU (950) | Forwards additional arguments to BiSheng compilation paths that support this option.|
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| 4 | enable_auto_bind_sub_block | NPU | Enables or disables automatic sub-block binding.|
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| 5 | enable_hivm_auto_cv_balance | NPU | Enables or disables automatic CV balancing.|
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| 6 | enable_cube_block_merge | NPU (950) | Controls Cube block merging in the DynamicCV pipeline.|
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| 7 | vf_fusion_mode | NPU (950) | Selects the VF fusion strategy.|
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| 8 | enable_vf_fusion | NPU (950) | Enables or disables VF fusion.|
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| 9 | hfusion_enable_multiple_consumer_fusion | NPU (950) | Enables or disables multiple-consumer HFusion.|
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| 10 | sync_solver | NPU | Enables or disables the synchronization solver.|
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| 11 | unit_flag | NPU | Enables or disables the sync unit flag.|
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| 12 | inject_barrier_all | NPU | Enables or disables automatic barrier injection.|
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| 13 | inject_block_all | NPU | Enables or disables automatic block injection.|
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| 14 | limit_auto_multi_buffer_only_for_local_buffer | NPU | Restricts automatic multi-buffering to local buffers.|
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| 15 | limit_auto_multi_buffer_of_local_buffer | NPU | Configures the local-buffer automatic multi-buffering scope.|
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| 16 | set_workspace_multibuffer | NPU | Configures workspace multi-buffering.|
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| 17 | tile_mix_vector_loop | NPU | Configures the Vector loop split count.|
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| 18 | tile_mix_cube_loop | NPU | Configures the Cube loop split count.|
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| 19 | buf_slot_num_of_veccore | NPU | Configures the number of vector-core-local buffer slots.|
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| 20 | buf_slot_num_of_crosscore | NPU | Configures the number of cross-core buffer slots.|
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| 21 | buf_slot_num_of_gm | NPU | Configures the number of GM load buffer slots.|
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| 22 | compile_mode | NPU | Compilation mode: `"simd_simt_template"` (default) / `"simd"` / `"simt_only"`; `"simt_only"` is supported only on Ascend 950.|
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See {ref}`Compiler Option Cleanup and Compatibility <compiler-option-cleanup-and-compatibility>` for deprecated-option compatibility and rename mappings.
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#### 3.2.2 SIMD Compiler
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@@ -216,7 +222,7 @@ Developers choose the compilation path via `compile_mode`.
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| `compile_mode` | Description | Compilation Path |
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|---|---|---|
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| `"simd"` | Pure SIMD: structured access via DMA; unstructured access via scalar loops | `Triton IR → Linalg IR → AscendNPU IR` |
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| `"unstructured_in_simt"` (**default**) | Hybrid: structured access stays on SIMD; discrete access prefers SIMT templates | `Triton IR → Linalg IR → AscendNPU IR` |
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| `"simd_simt_template"` (**default**) | Hybrid: structured access stays on SIMD; discrete access prefers SIMT templates | `Triton IR → Linalg IR → AscendNPU IR` |
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| `"simt_only"` | Pure SIMT: send Triton IR directly to AscendNPU IR | `Triton IR → AscendNPU IR` |
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Usage examples:
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kernel[grid](..., compile_mode="simd")
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# Hybrid (default; discrete access on 950 prefers SIMT)
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kernel[grid](..., compile_mode="unstructured_in_simt")
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kernel[grid](..., compile_mode="simd_simt_template")
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# Pure SIMT
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kernel[grid](..., compile_mode="simt_only", num_warps=32)
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```mermaid
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flowchart TD
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A[compile_mode] --> B["simd"]
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A --> C["unstructured_in_simt"]
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A --> C["simd_simt_template"]
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A --> D["simt_only"]
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%% simt_only branch
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B4 --> B5[TritonToLinalg]
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B5 --> B6[AscendNPU IR]
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%% unstructured_in_simt full path
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%% simd_simt_template full path
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C --> C1[discrete-mask-access-conversion]
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C1 --> C2[Mark when conditions are met and defer to downstream SIMT handling]
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C2 --> C3[triton-to-unstructured]
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class D,D1 simtOnly
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```
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| Stage | `"simd"` | `"unstructured_in_simt"` | `"simt_only"` |
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| Stage | `"simd"` | `"simd_simt_template"` | `"simt_only"` |
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|------|----------|--------------------------|---------------|
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| Discrete mask handling | Split into contiguous/discrete bounds and handle with load + select / store | On Ascend 950 with tensor rank ≤ 5: mark and defer to downstream; otherwise same as left | Not run |
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| Unstructured access | Expand to scalar loops | Prefer SIMT indirect access (rank ≤ 5); fall back to scalar loops on failure | Not run |

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